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| author | Ed Swierk <eswierk@aristanetworks.com> | 2008-10-29 14:54:36 +0000 |
|---|---|---|
| committer | Ed Swierk <eswierk@arastra.com> | 2008-10-29 14:54:36 +0000 |
| commit | c6bb6be6d27f95851cf6b7cbb67ddbd1ee5c8c5d (patch) | |
| tree | 8be6d62ad03774bcbfdc2bfb35cb384cc3443ae6 /util | |
| parent | bddc693e8d9cb3c66c2ef98da0b4de3c51aef94b (diff) | |
| download | coreboot-c6bb6be6d27f95851cf6b7cbb67ddbd1ee5c8c5d.tar.xz | |
Enable SPI boot flash support on EP80579, which has the ICH7 register set
(trivial).
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util')
| -rw-r--r-- | util/flashrom/chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c index 87b2380451..d7a5b024c1 100644 --- a/util/flashrom/chipset_enable.c +++ b/util/flashrom/chipset_enable.c @@ -767,7 +767,7 @@ static const FLASH_ENABLE enables[] = { {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x5031, "Intel EP80579", enable_flash_ich_dc}, + {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7}, {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7}, {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7}, {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7}, |