diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-17 08:45:36 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-23 09:16:31 +0000 |
| commit | 2b72e6bdfd63737d03efd02cb7f66a769243727f (patch) | |
| tree | b96fc47b44469e4054abea1f312d68590c9aad7d /util | |
| parent | 9a1bb36137921c751173d6726a06019c84b171f5 (diff) | |
| download | coreboot-2b72e6bdfd63737d03efd02cb7f66a769243727f.tar.xz | |
util/x86/x86_page_tables: update PAT mapping to match linux
The linux kernel uses the following mapping for PAT entries:
PTE encoding:
PAT
|PCD
||PWT PAT
||| slot
000 0 WB : _PAGE_CACHE_MODE_WB
001 1 WC : _PAGE_CACHE_MODE_WC
010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
011 3 UC : _PAGE_CACHE_MODE_UC
100 4 WB : Reserved
101 5 WP : _PAGE_CACHE_MODE_WP
110 6 UC-: Reserved
111 7 WT : _PAGE_CACHE_MODE_WT
Update the page table generator to match what the linux kernel is
using. This just makes things consistent with linux.
BUG=b:72728953
Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/x86/x86_page_tables.go | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/util/x86/x86_page_tables.go b/util/x86/x86_page_tables.go index 25ad6a2543..e03edeab19 100644 --- a/util/x86/x86_page_tables.go +++ b/util/x86/x86_page_tables.go @@ -185,16 +185,25 @@ func (cw *cWriter) WritePageEntry(data interface{}) error { return nil } -// This map represents what the IA32_PAT MSR +// This map represents what the IA32_PAT MSR should be at runtime. The indicies +// are what the linux kernel uses. Reserved entries are not used. +// 0 WB : _PAGE_CACHE_MODE_WB +// 1 WC : _PAGE_CACHE_MODE_WC +// 2 UC-: _PAGE_CACHE_MODE_UC_MINUS +// 3 UC : _PAGE_CACHE_MODE_UC +// 4 WB : Reserved +// 5 WP : _PAGE_CACHE_MODE_WP +// 6 UC-: Reserved +// 7 WT : _PAGE_CACHE_MODE_WT +// In order to use WP and WC then the IA32_PAT MSR needs to be updated +// as these are not the power on reset values. var patMsrIndexByType = map[uint]uint{ PAT_WB: 0, - PAT_WT: 1, + PAT_WC: 1, PAT_UCMINUS: 2, PAT_UC: 3, - // In order to use WP and WC then the IA32_PAT MSR needs to be updated - // as these are not the power on reset values. - PAT_WP: 6, - PAT_WC: 7, + PAT_WP: 5, + PAT_WT: 7, } type addressRange struct { |