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authorTaniya Das <tdas@codeaurora.org>2019-12-19 16:41:02 +0530
committerJulius Werner <jwerner@chromium.org>2020-02-07 23:12:00 +0000
commit91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0 (patch)
treed12a349c19549d7f1443fee76ba938a0dcccb416 /util
parentbcd62f5737f5022b1bbe0041d4222575851b3cb9 (diff)
downloadcoreboot-91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0.tar.xz
sc7180: clock: Fix QUP DFSR configuration for perf levels
Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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