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authorJason Wang <Qingpei.Wang@amd.com>2008-11-28 05:40:27 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-11-28 05:40:27 +0000
commitd95e43cc8f66203a8287f8a7c54ecc3ab74436e6 (patch)
tree03bb79378560bf63f1fb91a9572e1f7e7024804b /util
parent6f24cbc0833fd923238f516dd8964660807ef789 (diff)
downloadcoreboot-d95e43cc8f66203a8287f8a7c54ecc3ab74436e6.tar.xz
Add SST25VF080B flash chip support.
This is the first chip which uses the infrastructure for alternative erase commands, namely spi_chip_erase_60_c7(). Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util')
-rw-r--r--util/flashrom/flashchips.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/util/flashrom/flashchips.c b/util/flashrom/flashchips.c
index e7c57f6ddc..d6f399d715 100644
--- a/util/flashrom/flashchips.c
+++ b/util/flashrom/flashchips.c
@@ -110,6 +110,7 @@ struct flashchip flashchips[] = {
{"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
{"SST", "SST25VF032B", SST_ID, SST_25VF032B, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
{"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
+ {"SST", "SST25VF080B", SST_ID, SST_25VF080B, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_60_c7, spi_chip_write, spi_chip_read},
{"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040},
{"SST", "SST29EE010", SST_ID, SST_29EE010, 128, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec},
{"SST", "SST29LE010", SST_ID, SST_29LE010, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},