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authorAamir Bohra <aamir.bohra@intel.com>2019-04-03 14:42:26 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-04-11 11:26:37 +0000
commite05fe3166e69f8b23eb5a448052cea79e9e6a38a (patch)
tree2f747153775eef1e2c76be0b28a11d40622e95e8 /util
parent4577cd240399664d0b847ecc918d399338b7fd23 (diff)
downloadcoreboot-e05fe3166e69f8b23eb5a448052cea79e9e6a38a.tar.xz
soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups
This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1. BUG=b:121212459 TEST: Verified the GPIO MISCFG is getting set as per updated map. Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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