util/inteltool: Add support for mobile 5 chipset

Dump registers on mobile 5. Successfully tested on X201.

Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

6 files changed, 221 insertions, 1 deletions

diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 80e1ed69c3..87fc4711bb 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -888,6 +888,123 @@ int print_intel_core_msrs(void)
                 { 0x0600, "IA32_DS_AREA" },
         };
 
+	static const msr_entry_t model20650_global_msrs[] = {
+		{ 0x0000, "IA32_P5_MC_ADDR" },
+		{ 0x0001, "IA32_P5_MC_TYPE" },
+		{ 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+		{ 0x0017, "IA32_PLATFORM_ID" },
+		{ 0x002a, "MSR_EBC_HARD_POWERON" },
+// WRITE ONLY	{ 0x0079, "IA32_BIOS_UPDT_TRIG" },
+		{ 0x00ce, "IA32_MSR_PLATFORM_INFO" },
+		{ 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
+		{ 0x019c, "IA32_THERM_STATUS" },
+		{ 0x019d, "MSR_THERM2_CTL" },
+		{ 0x01a0, "IA32_MISC_ENABLE" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
+		{ 0x0300, "MSR_BPU_COUNTER0" },
+		{ 0x0301, "MSR_BPU_COUNTER1" },
+		/* Skipped through 0x3ff  for now*/
+
+		/* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
+		 * set in MCX_STATUS */
+		{ 0x400, "IA32_MC0_CTL" },
+		{ 0x401, "IA32_MC0_STATUS" },
+		{ 0x402, "IA32_MC0_ADDR" },
+		{ 0x403, "IA32_MC0_MISC" },
+		{ 0x404, "IA32_MC1_CTL" },
+		{ 0x405, "IA32_MC1_STATUS" },
+		{ 0x406, "IA32_MC1_ADDR" },
+		{ 0x407, "IA32_MC1_MISC" },
+		{ 0x408, "IA32_MC2_CTL" },
+		{ 0x409, "IA32_MC2_STATUS" },
+		{ 0x40a, "IA32_MC2_ADDR" },
+		{ 0x40c, "IA32_MC3_CTL" },
+		{ 0x40d, "IA32_MC3_STATUS" },
+		{ 0x40e, "IA32_MC3_ADDR" },
+		{ 0x410, "IA32_MC4_CTL" },
+		{ 0x411, "IA32_MC4_STATUS" },
+	};
+
+	static const msr_entry_t model20650_per_core_msrs[] = {
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x001b, "IA32_APIC_BASE" },
+		{ 0x003a, "IA32_FEATURE_CONTROL" },
+		{ 0x008b, "IA32_BIOS_SIGN_ID" },
+		{ 0x009b, "IA32_SMM_MONITOR_CTL" },
+		{ 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
+		{ 0x00fe, "IA32_MTRRCAP" },
+		{ 0x0174, "IA32_SYSENTER_CS" },
+		{ 0x0175, "IA32_SYSENTER_ESP" },
+		{ 0x0176, "IA32_SYSENTER_EIP" },
+		{ 0x0179, "IA32_MCG_CAP" },
+		{ 0x017a, "IA32_MCG_STATUS" },
+		{ 0x0186, "MSR_MCG_RBP" },
+		{ 0x0187, "MSR_MCG_RSP" },
+		{ 0x0188, "MSR_MCG_RFLAGS" },
+		{ 0x0189, "MSR_MCG_RIP" },
+		{ 0x0194, "MSR_MCG_R12" },
+		{ 0x0198, "IA32_PERF_STATUS" },
+		{ 0x0199, "IA32_PERF_CTL" },
+		{ 0x019a, "IA32_CLOCK_MODULATION" },
+		{ 0x019b, "IA32_THERM_INTERRUPT" },
+		{ 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
+		{ 0x01aa, "IA32_MISC_PWR_MGMT" },
+		{ 0x01d9, "MSR_DEBUGCTLA" },
+		{ 0x01fc, "MSR_POWER_CTL" },
+		{ 0x0277, "IA32_PAT" },
+		/** Virtualization
+		{ 0x480, "IA32_VMX_BASIC" },
+		  through
+		{ 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
+		  Not implemented in my CPU
+		*/
+		{ 0x0600, "IA32_DS_AREA" },
+		/* 0x0680 - 0x06cf Branch Records Skipped */
+
+		{ 0x3a, "IA32_FEATURE_CONTROL" },
+		{ 0x13c, "MSR_FEATURE_CONFIG" },
+		{ 0x194, "MSR_FLEX_RATIO" },
+		{ 0x1a0, "IA32_MISC_ENABLE" },
+		{ 0x1a2, "MSR_TEMPERATURE_TARGET" },
+		{ 0x199, "IA32_PERF_CTL" },
+		{ 0x19b, "IA32_THERM_INTERRUPT" },
+		{ 0x401, "IA32_MC0_STATUS" },
+		{ 0x2e, "MSR_PIC_MSG_CONTROL" },
+		{ 0xce, "MSR_PLATFORM_INFO" },
+		{ 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
+		{ 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
+		{ 0x1aa, "MSR_MISC_PWR_MGMT" },
+		{ 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
+		{ 0x1fc, "MSR_POWER_CTL" },
+	};
+
 	typedef struct {
 		unsigned int model;
 		const msr_entry_t *global_msrs;
@@ -904,6 +1021,7 @@ int print_intel_core_msrs(void)
 		{ 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
 		{ 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
 		{ 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
+		{ 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
 	};
 
 	cpu_t *cpu = NULL;
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 7ce9939f97..820e266826 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -523,6 +523,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 		size = ARRAY_SIZE(i631x_gpio_registers);
 		break;
 
+	case PCI_DEVICE_ID_INTEL_MOBILE_5:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = i631x_gpio_registers;
+		size = ARRAY_SIZE(i631x_gpio_registers);
+		break;
+
 	case PCI_DEVICE_ID_INTEL_82371XX:
 		printf("This southbridge has GPIOs in the PM unit.\n");
 		return 1;
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 5a6dcc8f0d..7872a5f4a1 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -60,6 +60,7 @@
 #define PCI_DEVICE_ID_INTEL_ICH9M		0x2919
 #define PCI_DEVICE_ID_INTEL_ICH9ME		0x2917
 #define PCI_DEVICE_ID_INTEL_ICH10R		0x3a16
+#define PCI_DEVICE_ID_INTEL_MOBILE_5		0x3b07
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC	0x8119
 #define PCI_DEVICE_ID_INTEL_Z68			0x1c44
 #define PCI_DEVICE_ID_INTEL_P67			0x1c46
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 506620d8ab..be8b0cb3bd 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -64,13 +64,97 @@ static const io_register_t sandybridge_mch_registers[] = {
 	{ 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
 };
 
+volatile uint8_t *mchbar;
+
+static void write_mchbar32 (uint32_t addr, uint32_t val)
+{
+	* (volatile uint32_t *) (mchbar + addr) = val;
+}
+
+static uint32_t read_mchbar32 (uint32_t addr)
+{
+	return * (volatile uint32_t *) (mchbar + addr);
+}
+
+static uint8_t read_mchbar8 (uint32_t addr)
+{
+	return * (volatile uint8_t *) (mchbar + addr);
+}
+
+static u16 read_500 (int channel, u16 addr, int split)
+{
+	uint32_t val;
+	write_mchbar32 (0x500 + (channel << 10), 0);
+	while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
+	write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
+	while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
+	val = read_mchbar32 (0x508 + (channel << 10));
+
+	return val & ((1 << split) - 1);
+}
+
+static inline u16 get_lane_offset (int slot, int rank, int lane)
+{
+	return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
+}
+
+static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank)
+{
+	const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
+	return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
+}
+
+static void write_1d0 (u32 val, u16 addr, int bits, int flag)
+{
+	write_mchbar32 (0x1d0, 0);
+	while (read_mchbar32 (0x1d0) & 0x800000);
+	write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
+	write_mchbar32 (0x1d0, 0x40000000 | addr);
+	while (read_mchbar32 (0x1d0) & 0x800000);
+}
+
+static u16 read_1d0 (u16 addr, int split)
+{
+	u32 val;
+	write_mchbar32 (0x1d0, 0);
+	while (read_mchbar32 (0x1d0) & 0x800000);
+	write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr));
+	while (read_mchbar32 (0x1d0) & 0x800000);
+	val = read_mchbar32 (0x1d8);
+	write_1d0 (0, 0x33d, 0, 0);
+	write_1d0 (0, 0x33d, 0, 0);
+	return val & ((1 << split) - 1);
+}
+
+static void dump_timings (void)
+{
+	int channel, slot, rank, lane, i;
+	printf ("Timings:\n");
+	for (channel = 0; channel < 2; channel++)
+		for (slot = 0; slot < 2; slot++)
+			for (rank = 0; rank < 2; rank++) {
+				printf ("channel %d, slot %d, rank %d\n", channel, slot, rank);
+				for (lane = 0; lane < 9; lane++) {
+					printf ("lane %d: ", lane);
+					for (i = 0; i < 4; i++) {
+						printf ("%x ", read_500 (channel,
+							get_timing_register_addr (lane, i, slot, rank), 9));
+					}
+				printf ("\n");
+				}
+			}
+
+	printf ("[178] = %x\n", read_1d0 (0x178, 7));
+	printf ("[10b] = %x\n", read_1d0 (0x10b, 6));
+}
+
+
 /*
  * (G)MCH MMIO Config Space
  */
 int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 {
 	int i, size = (16 * 1024);
-	volatile uint8_t *mchbar;
 	uint64_t mchbar_phys;
 	const io_register_t *mch_registers = NULL;
 	struct pci_dev *nb_device6; /* "overflow device" on i865 */
@@ -229,6 +313,10 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
 		}
 	}
 
+	if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) {
+		printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
+		dump_timings ();
+	}
 	unmap_physical((void *)mchbar, size);
 	return 0;
 }
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index f0f766449e..3c874db106 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -761,6 +761,12 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
 		size = ARRAY_SIZE(i63xx_pm_registers);
 		break;
 
+	case PCI_DEVICE_ID_INTEL_MOBILE_5:
+		pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+		pm_registers = i63xx_pm_registers;
+		size = ARRAY_SIZE(i63xx_pm_registers);
+		break;
+
 	case 0x1234: // Dummy for non-existent functionality
 		printf("This southbridge does not have PMBASE.\n");
 		return 1;
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 7cc55ded88..8cf2ffb22b 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -47,6 +47,7 @@ int print_rcba(struct pci_dev *sb)
 	case PCI_DEVICE_ID_INTEL_ICH10R:
 	case PCI_DEVICE_ID_INTEL_NM10:
 	case PCI_DEVICE_ID_INTEL_I63XX:
+	case PCI_DEVICE_ID_INTEL_MOBILE_5:
 	case PCI_DEVICE_ID_INTEL_Z68:
 	case PCI_DEVICE_ID_INTEL_P67:
 	case PCI_DEVICE_ID_INTEL_UM67: