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| author | Angel Pons <th3fanbus@gmail.com> | 2020-02-17 14:04:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:04:39 +0000 |
| commit | 31b7ee42016f7b54c24f30c271b4b93df16bfa10 (patch) | |
| tree | ae4d33670204b4e09e228ff3d28385e76da7210d /util | |
| parent | 95de2317c6c6379e43d3b3c27d34eb66198dbe0a (diff) | |
| download | coreboot-31b7ee42016f7b54c24f30c271b4b93df16bfa10.tar.xz | |
treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:
- Hillel: 32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics
This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.
Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
| -rwxr-xr-x | util/docker/coreboot.org-status/board-status.html/tohtml.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index fa89ae962b..2606af4065 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -471,7 +471,7 @@ EOF "") case $northbridge in INTEL_IRONLAKE) - cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" + cpu_nice="Intel® 1st Gen (Westmere) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610" |