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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-28 14:00:57 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-03 17:40:34 +0100 |
| commit | 7ff4fe12372ab613ebb1fb2957396910a67200e5 (patch) | |
| tree | 0a3db9a77d96bf4102925970b661968936fb3dd6 /util | |
| parent | a5798a9b8f0f2b5b026f4935bc8e2c3425e821a8 (diff) | |
| download | coreboot-7ff4fe12372ab613ebb1fb2957396910a67200e5.tar.xz | |
util/inteltool: Add ICH6-10 to BIOS_CNTL list
Without this change inteltool cannot read BIOS_CNTL values nor can it
read the SPIBAR values.
Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util')
| -rw-r--r-- | util/inteltool/spi.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 4bd3a33cee..8dc6ecb7ee 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -3,6 +3,20 @@ #include <stdlib.h> #include "inteltool.h" +static const io_register_t ich6_bios_cntl_registers[] = { + { 0x0, 1, "BIOSWE - write enable" }, + { 0x1, 1, "BLE - lock enable" }, + { 0x2, 6, "reserved" }, +}; + +static const io_register_t ich7_bios_cntl_registers[] = { + { 0x0, 1, "BIOSWE - write enable" }, + { 0x1, 1, "BLE - lock enable" }, + { 0x2, 2, "SPI Read configuration" }, + { 0x4, 1, "TopSwapStatus" }, + { 0x5, 3, "reserved" }, +}; + static const io_register_t pch_bios_cntl_registers[] = { { 0x0, 1, "BIOSWE - write enable" }, { 0x1, 1, "BLE - lock enable" }, @@ -74,6 +88,30 @@ int print_bioscntl(struct pci_dev *sb) printf("\n============= SPI / BIOS CNTL =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH6: + bios_cntl = pci_read_byte(sb, 0xdc); + bios_cntl_register = ich6_bios_cntl_registers; + size = ARRAY_SIZE(ich6_bios_cntl_registers); + break; + case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: + case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8ME: + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + case PCI_DEVICE_ID_INTEL_ICH10R: + case PCI_DEVICE_ID_INTEL_NM10: + bios_cntl = pci_read_byte(sb, 0xdc); + bios_cntl_register = ich7_bios_cntl_registers; + size = ARRAY_SIZE(ich7_bios_cntl_registers); + break; case PCI_DEVICE_ID_INTEL_3400: case PCI_DEVICE_ID_INTEL_3420: case PCI_DEVICE_ID_INTEL_3450: |