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| author | Jon Dufresne <jon.dufresne@gmail.com> | 2008-01-28 00:04:23 +0000 |
|---|---|---|
| committer | Corey Osgood <corey.osgood@gmail.com> | 2008-01-28 00:04:23 +0000 |
| commit | ca31bc3cd5bbc50eec9d22b6091c2a3e510c270b (patch) | |
| tree | 7e361dd255cfa13f1e4f86958c0599938a235573 /util | |
| parent | d27aa6eff5d48367be8c40d1e4b1a9385444078a (diff) | |
| download | coreboot-ca31bc3cd5bbc50eec9d22b6091c2a3e510c270b.tar.xz | |
Fix mptable util so the output will compile
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util')
| -rw-r--r-- | util/mptable/mptable.c | 48 |
1 files changed, 26 insertions, 22 deletions
diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c index 9c6b4f3127..0550981d0d 100644 --- a/util/mptable/mptable.c +++ b/util/mptable/mptable.c @@ -302,10 +302,10 @@ int noisy = 0; /* preamble to the mptable. This is fixed for all coreboots */ char *preamble[] = { +"#include <console/console.h>", "#include <arch/smp/mpspec.h>", +"#include <device/pci.h>", "#include <string.h>", -"#include <printk.h>", -"#include <pci.h>", "#include <stdint.h>", "", "void *smp_write_config_table(void *v)", @@ -361,31 +361,35 @@ char *postamble[] = { char *ioapic_code[] = { " smp_write_ioapic(mc, 2, 0x20, 0xfec00000);", " {", -" struct pci_dev *dev;", -" uint32_t base;", -" dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));", +" device_t dev;", +" struct resource *res;", +" dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));", " if (dev) {", -" pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);", -" base &= PCI_BASE_ADDRESS_MEM_MASK;", -" smp_write_ioapic(mc, 3, 0x20, base);", +" res = find_resource(dev, PCI_BASE_ADDRESS_0);", +" if (res) {", +" smp_write_ioapic(mc, 3, 0x20, res->base);", +" }", " }", -" dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));", +" dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));", " if (dev) {", -" pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);", -" base &= PCI_BASE_ADDRESS_MEM_MASK;", -" smp_write_ioapic(mc, 4, 0x20, base);", +" res = find_resource(dev, PCI_BASE_ADDRESS_0);", +" if (res) {", +" smp_write_ioapic(mc, 4, 0x20, res->base);", +" }", " }", -" dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));", +" dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));", " if (dev) {", -" pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);", -" base &= PCI_BASE_ADDRESS_MEM_MASK;", -" smp_write_ioapic(mc, 5, 0x20, base);", +" res = find_resource(dev, PCI_BASE_ADDRESS_0);", +" if (res) {", +" smp_write_ioapic(mc, 5, 0x20, res->base);", +" }", " }", -" dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));", +" dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));", " if (dev) {", -" pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);", -" base &= PCI_BASE_ADDRESS_MEM_MASK;", -" smp_write_ioapic(mc, 8, 0x20, base);", +" res = find_resource(dev, PCI_BASE_ADDRESS_0);", +" if (res) {", +" smp_write_ioapic(mc, 8, 0x20, res->base);", +" }", " }", " }", 0 @@ -1122,10 +1126,10 @@ char* intTypes[] = { }; char* polarityMode[] = { - "conforms", "MP_IRQ_POLARITY_HIGH", "reserved", "MP_IRQ_POLARITY_LOW" + "MP_IRQ_POLARITY_DEFAULT", "MP_IRQ_POLARITY_HIGH", "reserved", "MP_IRQ_POLARITY_LOW" }; char* triggerMode[] = { - "conforms", "MP_IRQ_TRIGGER_EDGE", "reserved", "MP_IRQ_TRIGGER_LEVEL" + "MP_IRQ_TRIGGER_DEFAULT", "MP_IRQ_TRIGGER_EDGE", "reserved", "MP_IRQ_TRIGGER_LEVEL" }; static void |