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authorAngel Pons <th3fanbus@gmail.com>2019-03-16 16:12:21 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-03-18 09:19:30 +0000
commit9b1ae44b28d23f67420d90ec6b60cc346d54832a (patch)
treebe6afad5355fd73f45726f86dd5ba36c9889898e /util
parentbfe4a59bc97d086dc5152e5e082caaa09740aef6 (diff)
downloadcoreboot-9b1ae44b28d23f67420d90ec6b60cc346d54832a.tar.xz
util/autoport: fix default headers
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'util')
-rw-r--r--util/autoport/bd82x6x.go14
1 files changed, 6 insertions, 8 deletions
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index c4dcf0dd28..265cb6f4b3 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -302,23 +302,21 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
sb := Create(ctx, "romstage.c")
defer sb.Close()
Add_gpl(sb)
- sb.WriteString(`#include <stdint.h>
+ sb.WriteString(`/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
#include <string.h>
-#include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/acpi.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
void pch_enable_lpc(void)
{