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authorVladimir Serbinenko <phcoder@gmail.com>2016-02-10 02:36:04 +0100
committerMartin Roth <martinroth@google.com>2016-02-12 17:09:05 +0100
commit144eea069726903d157f67a2f886dff4575d9b19 (patch)
tree995376822269c860e71fbae390a970fab3d587a7 /util
parentc37c7c8b1f3977e362e05945a48ddecf803e20a7 (diff)
downloadcoreboot-144eea069726903d157f67a2f886dff4575d9b19.tar.xz
Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util')
-rw-r--r--util/autoport/sandybridge.go1
-rwxr-xr-xutil/board_status/to-wiki/towiki.sh4
2 files changed, 3 insertions, 2 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 66d44d9426..4ef6609b45 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -114,6 +114,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true
+ KconfigBool["USE_NATIVE_RAMINIT"] = true
KconfigBool["INTEL_INT15"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true
diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh
index 922e470916..85334ef146 100755
--- a/util/board_status/to-wiki/towiki.sh
+++ b/util/board_status/to-wiki/towiki.sh
@@ -326,9 +326,9 @@ EOF
case $northbridge in
INTEL_HASWELL)
cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";;
- INTEL_IVYBRIDGE|INTEL_IVYBRIDGE_MRC|INTEL_FSP_IVYBRIDGE)
+ INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE)
cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";;
- INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_MRC)
+ INTEL_SANDYBRIDGE)
cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";;
*)
cpu_nice="$northbridge";;