diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-07-02 12:36:03 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-07-03 00:02:55 +0000 |
| commit | d0089c2b075121af401c428740962a7432759691 (patch) | |
| tree | 2cb1ceba6d8fab1fee29b83cbc1dbfe3eba77f0e /util | |
| parent | 899b28acdb0f65521405540b7a52b2ad05049720 (diff) | |
| download | coreboot-d0089c2b075121af401c428740962a7432759691.tar.xz | |
util/tmpl/puff: Allow USB2/3 wakeups to (un)plug events
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: Ib59108ec42955b5414f76b591cce5073f7dad1a9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42990
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
| -rw-r--r-- | util/mainboard/google/puff/template/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index 55ce5ea084..244e67840b 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -81,6 +81,18 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" |