summaryrefslogtreecommitdiff
path: root/util
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2018-06-28 13:21:10 -0500
committerNico Huber <nico.h@gmx.de>2018-06-30 15:11:25 +0000
commit0a36c2ce15fd44e03e78a8805e6cc30fb5a7b67c (patch)
tree362463f6892b4ab41b9b9eb460f82ef12a3d118d /util
parentcbe73ea28b874f20c3dd88924bad7959d806889a (diff)
downloadcoreboot-0a36c2ce15fd44e03e78a8805e6cc30fb5a7b67c.tar.xz
cbfstool: fix FIT entry checksum type value for ucode entries
commit c1072f2 [cbfstool: Update FIT entries in the second bootblock] incorrectly changed the value of type_checksum_valid for microcode entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on Skylake/FSP1.1 devices (and others?). Correct this by reverting to the previous value. Test: build/boot google/chell, observe FspTempRamInit no longer fails, device boots as expected. Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27266 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
-rw-r--r--util/cbfstool/fit.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index 31ab3dec82..ad9ab37855 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -182,8 +182,7 @@ static void update_fit_ucode_entry(struct fit_table *fit,
* rather from the MCU header, hence we can assign zero here
*/
entry->size_reserved = 0x0000;
- /* Checksum valid should be cleared for MCU */
- entry->type_checksum_valid = 0;
+ entry->type_checksum_valid = FIT_TYPE_MICROCODE;
entry->version = FIT_MICROCODE_VERSION;
entry->checksum = 0;
fit_entry_add_size(&fit->header, sizeof(struct fit_entry));