util/inteltool: Add support for Denverton

Used documents:
- C3000 Product Family Datasheet

Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae
Co-authored-by: Felix Singer <migy@darmstadt.ccc.de>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/30887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

5 files changed, 230 insertions, 0 deletions

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 9dc64dfa96..dd09214b54 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1026,6 +1026,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
 		break;
 	case PCI_DEVICE_ID_INTEL_B150:
 	case PCI_DEVICE_ID_INTEL_CM236:
+	case PCI_DEVICE_ID_INTEL_DNV_LPC:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
 	case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index dd20af600e..53a8eb9851 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -619,6 +619,227 @@ static const struct gpio_community *const sunrise_lp_communities[] = {
 	&sunrise_community_gpd, &sunrise_lp_community_fg,
 };
 
+static const char *const denverton_group_north_all_names[] = {
+	"NORTH_ALL_GBE0_SDP0",
+	"NORTH_ALL_GBE1_SDP0",
+	"NORTH_ALL_GBE0_SDP1",
+	"NORTH_ALL_GBE1_SDP1",
+	"NORTH_ALL_GBE0_SDP2",
+	"NORTH_ALL_GBE1_SDP2",
+	"NORTH_ALL_GBE0_SDP3",
+	"NORTH_ALL_GBE1_SDP3",
+	"NORTH_ALL_GBE2_LED0",
+	"NORTH_ALL_GBE2_LED1",
+	"NORTH_ALL_GBE0_I2C_CLK",
+	"NORTH_ALL_GBE0_I2C_DATA",
+	"NORTH_ALL_GBE1_I2C_CLK",
+	"NORTH_ALL_GBE1_I2C_DATA",
+	"NORTH_ALL_NCSI_RXD0",
+	"NORTH_ALL_NCSI_CLK_IN",
+	"NORTH_ALL_NCSI_RXD1",
+	"NORTH_ALL_NCSI_CRS_DV",
+	"NORTH_ALL_NCSI_ARB_IN",
+	"NORTH_ALL_NCSI_TX_EN",
+	"NORTH_ALL_NCSI_TXD0",
+	"NORTH_ALL_NCSI_TXD1",
+	"NORTH_ALL_NCSI_ARB_OUT",
+	"NORTH_ALL_GBE0_LED0",
+	"NORTH_ALL_GBE0_LED1",
+	"NORTH_ALL_GBE1_LED0",
+	"NORTH_ALL_GBE1_LED1",
+	"NORTH_ALL_GPIO_0",
+	"NORTH_ALL_PCIE_CLKREQ0_N",
+	"NORTH_ALL_PCIE_CLKREQ1_N",
+	"NORTH_ALL_PCIE_CLKREQ2_N",
+	"NORTH_ALL_PCIE_CLKREQ3_N",
+	"NORTH_ALL_PCIE_CLKREQ4_N",
+	"NORTH_ALL_GPIO_1",
+	"NORTH_ALL_GPIO_2",
+	"NORTH_ALL_SVID_ALERT_N",
+	"NORTH_ALL_SVID_DATA",
+	"NORTH_ALL_SVID_CLK",
+	"NORTH_ALL_THERMTRIP_N",
+	"NORTH_ALL_PROCHOT_N",
+	"NORTH_ALL_MEMHOT_N",
+};
+
+static const struct gpio_group denverton_group_north_all = {
+	.display	= "------- GPIO Group North All -------",
+	.pad_count	= ARRAY_SIZE(denverton_group_north_all_names) / 1,
+	.func_count	= 1,
+	.pad_names	= denverton_group_north_all_names,
+};
+
+static const struct gpio_group *const denverton_community_north_groups[] = {
+	&denverton_group_north_all,
+};
+
+static const struct gpio_community denverton_community_north = {
+	.name		= "------- GPIO Community 0 -------",
+	.pcr_port_id	= 0xc2,
+	.group_count	= ARRAY_SIZE(denverton_community_north_groups),
+	.groups		= denverton_community_north_groups,
+};
+
+static const char *const denverton_group_south_dfx_names[] = {
+	"SOUTH_DFX_DFX_PORT_CLK0",
+	"SOUTH_DFX_DFX_PORT_CLK1",
+	"SOUTH_DFX_DFX_PORT0",
+	"SOUTH_DFX_DFX_PORT1",
+	"SOUTH_DFX_DFX_PORT2",
+	"SOUTH_DFX_DFX_PORT3",
+	"SOUTH_DFX_DFX_PORT4",
+	"SOUTH_DFX_DFX_PORT5",
+	"SOUTH_DFX_DFX_PORT6",
+	"SOUTH_DFX_DFX_PORT7",
+	"SOUTH_DFX_DFX_PORT8",
+	"SOUTH_DFX_DFX_PORT9",
+	"SOUTH_DFX_DFX_PORT10",
+	"SOUTH_DFX_DFX_PORT11",
+	"SOUTH_DFX_DFX_PORT12",
+	"SOUTH_DFX_DFX_PORT13",
+	"SOUTH_DFX_DFX_PORT14",
+	"SOUTH_DFX_DFX_PORT15",
+};
+
+static const struct gpio_group denverton_group_south_dfx = {
+	.display	= "------- GPIO Group South DFX -------",
+	.pad_count	= ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
+	.func_count	= 1,
+	.pad_names	= denverton_group_south_dfx_names,
+};
+
+static const char *const denverton_group_south_group0_names[] = {
+	"SOUTH_GROUP0_GPIO_12",
+	"SOUTH_GROUP0_SMB5_GBE_ALRT_N",
+	"SOUTH_GROUP0_PCIE_CLKREQ5_N",
+	"SOUTH_GROUP0_PCIE_CLKREQ6_N",
+	"SOUTH_GROUP0_PCIE_CLKREQ7_N",
+	"SOUTH_GROUP0_UART0_RXD",
+	"SOUTH_GROUP0_UART0_TXD",
+	"SOUTH_GROUP0_SMB5_GBE_CLK",
+	"SOUTH_GROUP0_SMB5_GBE_DATA",
+	"SOUTH_GROUP0_ERROR2_N",
+	"SOUTH_GROUP0_ERROR1_N",
+	"SOUTH_GROUP0_ERROR0_N",
+	"SOUTH_GROUP0_IERR_N",
+	"SOUTH_GROUP0_MCERR_N",
+	"SOUTH_GROUP0_SMB0_LEG_CLK",
+	"SOUTH_GROUP0_SMB0_LEG_DATA",
+	"SOUTH_GROUP0_SMB0_LEG_ALRT_N",
+	"SOUTH_GROUP0_SMB1_HOST_DATA",
+	"SOUTH_GROUP0_SMB1_HOST_CLK",
+	"SOUTH_GROUP0_SMB2_PECI_DATA",
+	"SOUTH_GROUP0_SMB2_PECI_CLK",
+	"SOUTH_GROUP0_SMB4_CSME0_DATA",
+	"SOUTH_GROUP0_SMB4_CSME0_CLK",
+	"SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
+	"SOUTH_GROUP0_USB_OC0_N",
+	"SOUTH_GROUP0_FLEX_CLK_SE0",
+	"SOUTH_GROUP0_FLEX_CLK_SE1",
+	"SOUTH_GROUP0_GPIO_4",
+	"SOUTH_GROUP0_GPIO_5",
+	"SOUTH_GROUP0_GPIO_6",
+	"SOUTH_GROUP0_GPIO_7",
+	"SOUTH_GROUP0_SATA0_LED_N",
+	"SOUTH_GROUP0_SATA1_LED_N",
+	"SOUTH_GROUP0_SATA_PDETECT0",
+	"SOUTH_GROUP0_SATA_PDETECT1",
+	"SOUTH_GROUP0_SATA0_SDOUT",
+	"SOUTH_GROUP0_SATA1_SDOUT",
+	"SOUTH_GROUP0_UART1_RXD",
+	"SOUTH_GROUP0_UART1_TXD",
+	"SOUTH_GROUP0_GPIO_8",
+	"SOUTH_GROUP0_GPIO_9",
+	"SOUTH_GROUP0_TCK",
+	"SOUTH_GROUP0_TRST_N",
+	"SOUTH_GROUP0_TMS",
+	"SOUTH_GROUP0_TDI",
+	"SOUTH_GROUP0_TDO",
+	"SOUTH_GROUP0_CX_PRDY_N",
+	"SOUTH_GROUP0_CX_PREQ_N",
+	"SOUTH_GROUP0_CTBTRIGINOUT",
+	"SOUTH_GROUP0_CTBTRIGOUT",
+	"SOUTH_GROUP0_DFX_SPARE2",
+	"SOUTH_GROUP0_DFX_SPARE3",
+	"SOUTH_GROUP0_DFX_SPARE4",
+};
+
+static const struct gpio_group denverton_group_south_group0 = {
+	.display	= "------- GPIO Group South Group0 -------",
+	.pad_count	= ARRAY_SIZE(denverton_group_south_group0_names) / 1,
+	.func_count	= 1,
+	.pad_names	= denverton_group_south_group0_names,
+};
+
+static const char *const denverton_group_south_group1_names[] = {
+	"SOUTH_GROUP1_SUSPWRDNACK",
+	"SOUTH_GROUP1_PMU_SUSCLK",
+	"SOUTH_GROUP1_ADR_TRIGGER",
+	"SOUTH_GROUP1_PMU_SLP_S45_N",
+	"SOUTH_GROUP1_PMU_SLP_S3_N",
+	"SOUTH_GROUP1_PMU_WAKE_N",
+	"SOUTH_GROUP1_PMU_PWRBTN_N",
+	"SOUTH_GROUP1_PMU_RESETBUTTON_N",
+	"SOUTH_GROUP1_PMU_PLTRST_N",
+	"SOUTH_GROUP1_SUS_STAT_N",
+	"SOUTH_GROUP1_SLP_S0IX_N",
+	"SOUTH_GROUP1_SPI_CS0_N",
+	"SOUTH_GROUP1_SPI_CS1_N",
+	"SOUTH_GROUP1_SPI_MOSI_IO0",
+	"SOUTH_GROUP1_SPI_MISO_IO1",
+	"SOUTH_GROUP1_SPI_IO2",
+	"SOUTH_GROUP1_SPI_IO3",
+	"SOUTH_GROUP1_SPI_CLK",
+	"SOUTH_GROUP1_SPI_CLK_LOOPBK",
+	"SOUTH_GROUP1_ESPI_IO0",
+	"SOUTH_GROUP1_ESPI_IO1",
+	"SOUTH_GROUP1_ESPI_IO2",
+	"SOUTH_GROUP1_ESPI_IO3",
+	"SOUTH_GROUP1_ESPI_CS0_N",
+	"SOUTH_GROUP1_ESPI_CLK",
+	"SOUTH_GROUP1_ESPI_RST_N",
+	"SOUTH_GROUP1_ESPI_ALRT0_N",
+	"SOUTH_GROUP1_GPIO_10",
+	"SOUTH_GROUP1_GPIO_11",
+	"SOUTH_GROUP1_ESPI_CLK_LOOPBK",
+	"SOUTH_GROUP1_EMMC_CMD",
+	"SOUTH_GROUP1_EMMC_STROBE",
+	"SOUTH_GROUP1_EMMC_CLK",
+	"SOUTH_GROUP1_EMMC_D0",
+	"SOUTH_GROUP1_EMMC_D1",
+	"SOUTH_GROUP1_EMMC_D2",
+	"SOUTH_GROUP1_EMMC_D3",
+	"SOUTH_GROUP1_EMMC_D4",
+	"SOUTH_GROUP1_EMMC_D5",
+	"SOUTH_GROUP1_EMMC_D6",
+	"SOUTH_GROUP1_EMMC_D7",
+	"SOUTH_GROUP1_GPIO_3",
+};
+
+static const struct gpio_group denverton_group_south_group1 = {
+	.display	= "------- GPIO Group South Group1 -------",
+	.pad_count	= ARRAY_SIZE(denverton_group_south_group1_names) / 1,
+	.func_count	= 1,
+	.pad_names	= denverton_group_south_group1_names,
+};
+
+static const struct gpio_group *const denverton_community_south_groups[] = {
+	&denverton_group_south_dfx,
+	&denverton_group_south_group0,
+	&denverton_group_south_group1,
+};
+
+static const struct gpio_community denverton_community_south = {
+	.name		= "------- GPIO Community 1 -------",
+	.pcr_port_id	= 0xc5,
+	.group_count	= ARRAY_SIZE(denverton_community_south_groups),
+	.groups		= denverton_community_south_groups,
+};
+
+static const struct gpio_community *const denverton_communities[] = {
+	&denverton_community_north, &denverton_community_south,
+};
 
 static const char *decode_pad_mode(const struct gpio_group *const group,
 				   const size_t pad, const uint32_t dw0)
@@ -697,6 +918,11 @@ void print_gpio_groups(struct pci_dev *const sb)
 		communities = sunrise_lp_communities;
 		pcr_init(sb);
 		break;
+	case PCI_DEVICE_ID_INTEL_DNV_LPC:
+		community_count = ARRAY_SIZE(denverton_communities);
+		communities = denverton_communities;
+		pcr_init(sb);
+		break;
 	default:
 		return;
 	}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 9a58ed8f1e..93a7ffee16 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -266,6 +266,7 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
 	/* Intel GPUs */
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
 	  "Intel(R) G35 Express Chipset Family" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index d86ba3542f..fb6481102a 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -235,6 +235,7 @@ static inline uint32_t inl(unsigned port)
 #define CPUID_BAYTRAIL						0x30670
 
 #define PCI_DEVICE_ID_INTEL_APL_LPC		0x5ae8
+#define PCI_DEVICE_ID_INTEL_DNV_LPC		0x19dc
 
 /* Intel starts counting these generations with the integration of the DRAM controller */
 #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN	0xd132 /* Nehalem */
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 5d519afae3..5c97a6c536 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -97,6 +97,7 @@ void pcr_init(struct pci_dev *const sb)
 	case PCI_DEVICE_ID_INTEL_HM175:
 	case PCI_DEVICE_ID_INTEL_QM175:
 	case PCI_DEVICE_ID_INTEL_CM238:
+	case PCI_DEVICE_ID_INTEL_DNV_LPC:
 		p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
 		break;
 	case PCI_DEVICE_ID_INTEL_APL_LPC: