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-rw-r--r--src/soc/intel/common/block/include/intelblocks/chip.h2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/mmc.h (renamed from src/soc/intel/common/block/include/intelblocks/early_mmc.h)31
-rw-r--r--src/soc/intel/common/block/scs/Kconfig7
-rw-r--r--src/soc/intel/common/block/scs/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/scs/early_mmc.c35
-rw-r--r--src/soc/intel/common/block/scs/mmc.c95
6 files changed, 128 insertions, 43 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/chip.h
index 9fe165e5b1..1e830d5d17 100644
--- a/src/soc/intel/common/block/include/intelblocks/chip.h
+++ b/src/soc/intel/common/block/include/intelblocks/chip.h
@@ -18,6 +18,7 @@
#include <intelblocks/gspi.h>
#include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/mmc.h>
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
@@ -35,6 +36,7 @@ struct soc_intel_common_config {
struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/* PCH Thermal Trip Temperature in deg C */
uint8_t pch_thermal_trip;
+ struct mmc_dll_params emmc_dll;
};
/* This function to retrieve soc config structure required by common code */
diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/mmc.h
index 39aaf58fcf..a8776ea842 100644
--- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h
+++ b/src/soc/intel/common/block/include/intelblocks/mmc.h
@@ -13,18 +13,12 @@
* GNU General Public License for more details.
*/
-#ifndef SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H
-#define SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H
+#ifndef SOC_INTEL_COMMON_BLOCK_MMC_H
+#define SOC_INTEL_COMMON_BLOCK_MMC_H
#include <stdint.h>
/*
- * Following should be defined in soc/iomap.h
- * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's
- PCI BAR.
- */
-
-/*
* Structure for the following delay registers
* emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h
* emmc_tx_data_cntl2: Tx Delay Control 2 (Tx_DATA_dly_2)-Offset 828h
@@ -60,9 +54,28 @@ int soc_configure_mmc_gpios(void);
* returns 0, if able to get register settings; otherwise returns -1
*/
int soc_get_mmc_dll(struct mmc_dll_params *params);
+/*
+ * Set mmc delay register settings.
+ * bar: eMMC controller MMIO base address.
+ * returns 0, if able to set register settings; otherwise returns -1
+ */
+int set_mmc_dll(void *bar);
+
+#define EMMC_TX_CMD_CNTL_OFFSET 0x820
+#define EMMC_TX_DATA_CNTL1_OFFSET 0x824
+#define EMMC_TX_DATA_CNTL2_OFFSET 0x828
+#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C
+#define EMMC_RX_STROBE_CNTL_OFFSET 0x830
+#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834
#if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE)
/*
+ * Following should be defined in soc/iomap.h
+ * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's
+ PCI BAR.
+ */
+
+/*
* Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card.
* In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS
* and sets it to 1. Payload can start by sending CMD1, there is no need to
@@ -77,4 +90,4 @@ static inline int early_mmc_wake_hw(void)
return -1;
}
#endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */
-#endif /* SOC_INTEL_COMMON_BLOCK_EARLY_MMC_H */
+#endif /* SOC_INTEL_COMMON_BLOCK_MMC_H */
diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig
index 06ad8e4fa8..192425c4a0 100644
--- a/src/soc/intel/common/block/scs/Kconfig
+++ b/src/soc/intel/common/block/scs/Kconfig
@@ -12,3 +12,10 @@ config SOC_INTEL_COMMON_EARLY_MMC_WAKE
help
Send CMD1 early in romstage to improve boot time. It requires emmc
DLL tuning parameters to be added to devicetree.cb
+
+config SOC_INTEL_COMMON_MMC_OVERRIDE
+ bool
+ default n
+ help
+ Override the MMC settings after FSP-S.
+ It should be used only when there is no FSP UPDs for certain setting.
diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc
index 1160802d03..707a3342ad 100644
--- a/src/soc/intel/common/block/scs/Makefile.inc
+++ b/src/soc/intel/common/block/scs/Makefile.inc
@@ -1,2 +1,3 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c
romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c
diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c
index 8f47ec7d9e..80364500b9 100644
--- a/src/soc/intel/common/block/scs/early_mmc.c
+++ b/src/soc/intel/common/block/scs/early_mmc.c
@@ -21,18 +21,11 @@
#include <compiler.h>
#include <console/console.h>
#include <device/pci.h>
-#include <intelblocks/early_mmc.h>
+#include <intelblocks/mmc.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <string.h>
-#define EMMC_TX_CMD_CNTL_OFFSET 0x820
-#define EMMC_TX_DATA_CNTL1_OFFSET 0x824
-#define EMMC_TX_DATA_CNTL2_OFFSET 0x828
-#define EMMC_RX_CMD_DATA_CNTL1_OFFSET 0x82C
-#define EMMC_RX_STROBE_CNTL_OFFSET 0x830
-#define EMMC_RX_CMD_DATA_CNTL2_OFFSET 0x834
-
void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr)
{
uint32_t f_min, f_max;
@@ -62,32 +55,6 @@ static void disable_mmc_controller_bar(void)
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
}
-static int set_mmc_dll(void *ioaddr)
-{
- struct mmc_dll_params dll_params;
-
- if (soc_get_mmc_dll(&dll_params) < 0) {
- printk(BIOS_ERR,
- "MMC early init: failed to get mmc DLL parameters\n");
- return -1;
- }
-
- write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET,
- dll_params.emmc_tx_data_cntl1);
- write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET,
- dll_params.emmc_tx_data_cntl2);
- write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET,
- dll_params.emmc_rx_cmd_data_cntl1);
- write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET,
- dll_params.emmc_rx_cmd_data_cntl2);
- write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET,
- dll_params.emmc_rx_strobe_cntl);
- write32(ioaddr + EMMC_TX_CMD_CNTL_OFFSET,
- dll_params.emmc_tx_cmd_cntl);
-
- return 0;
-}
-
static void set_early_mmc_wake_status(int32_t status)
{
int32_t *ms_cbmem;
diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c
new file mode 100644
index 0000000000..5b2e2c7d33
--- /dev/null
+++ b/src/soc/intel/common/block/scs/mmc.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <intelblocks/chip.h>
+#include <intelblocks/mmc.h>
+
+static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val)
+{
+ int ret = 0;
+ if (val) {
+ write32(bar + reg, val);
+ ret = 1;
+ }
+ return ret;
+}
+
+int set_mmc_dll(void *bar)
+{
+ const struct soc_intel_common_config *common_config;
+ const struct mmc_dll_params *dll_params;
+ int override = 0;
+
+ common_config = chip_get_common_soc_structure();
+ dll_params = &common_config->emmc_dll;
+
+ override |= mmc_write_dll_reg(bar, EMMC_TX_CMD_CNTL_OFFSET,
+ dll_params->emmc_tx_cmd_cntl);
+
+ override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL1_OFFSET,
+ dll_params->emmc_tx_data_cntl1);
+
+ override |= mmc_write_dll_reg(bar, EMMC_TX_DATA_CNTL2_OFFSET,
+ dll_params->emmc_tx_data_cntl2);
+
+ override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL1_OFFSET,
+ dll_params->emmc_rx_cmd_data_cntl1);
+
+ override |= mmc_write_dll_reg(bar, EMMC_RX_STROBE_CNTL_OFFSET,
+ dll_params->emmc_rx_strobe_cntl);
+
+ override |= mmc_write_dll_reg(bar, EMMC_RX_CMD_DATA_CNTL2_OFFSET,
+ dll_params->emmc_rx_cmd_data_cntl2);
+
+ if (override == 0) {
+ printk(BIOS_INFO, "Skip Emmc dll value programming\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void mmc_soc_init(struct device *dev)
+{
+ const struct resource *res;
+
+ if (!CONFIG(SOC_INTEL_COMMON_MMC_OVERRIDE))
+ return;
+
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ set_mmc_dll((void *)(uintptr_t)(res->base));
+}
+
+static struct device_operations dev_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = mmc_soc_init,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_CMP_EMMC,
+ 0
+};
+
+static const struct pci_driver pch_sd __pci_driver = {
+ .ops = &dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};