diff options
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h | 1952 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h | 1790 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h | 136 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h | 96 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h | 6052 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h | 9674 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h | 404 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h | 504 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h | 144 |
9 files changed, 10376 insertions, 10376 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index d0421723eb..b5b83630c3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1,976 +1,976 @@ -/** @file
-
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Platform Reserved Memory Size
- The minimum platform memory size required to pass control into DXE
-**/
- UINT64 PlatformMemorySize;
-
-/** Offset 0x0048 - SPD Data Length
- Length of SPD Data
- 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
-**/
- UINT16 MemorySpdDataLen;
-
-/** Offset 0x004A - Reserved
-**/
- UINT8 Reserved0[2];
-
-/** Offset 0x004C - MemorySpdPtr00
-**/
- UINT32 MemorySpdPtr00;
-
-/** Offset 0x0050 - MemorySpdPtr01
-**/
- UINT32 MemorySpdPtr01;
-
-/** Offset 0x0054 - MemorySpdPtr02
-**/
- UINT32 MemorySpdPtr02;
-
-/** Offset 0x0058 - MemorySpdPtr03
-**/
- UINT32 MemorySpdPtr03;
-
-/** Offset 0x005C - MemorySpdPtr04
-**/
- UINT32 MemorySpdPtr04;
-
-/** Offset 0x0060 - MemorySpdPtr05
-**/
- UINT32 MemorySpdPtr05;
-
-/** Offset 0x0064 - MemorySpdPtr06
-**/
- UINT32 MemorySpdPtr06;
-
-/** Offset 0x0068 - MemorySpdPtr07
-**/
- UINT32 MemorySpdPtr07;
-
-/** Offset 0x006C - MemorySpdPtr08
-**/
- UINT32 MemorySpdPtr08;
-
-/** Offset 0x0070 - MemorySpdPtr09
-**/
- UINT32 MemorySpdPtr09;
-
-/** Offset 0x0074 - MemorySpdPtr10
-**/
- UINT32 MemorySpdPtr10;
-
-/** Offset 0x0078 - MemorySpdPtr11
-**/
- UINT32 MemorySpdPtr11;
-
-/** Offset 0x007C - MemorySpdPtr12
-**/
- UINT32 MemorySpdPtr12;
-
-/** Offset 0x0080 - MemorySpdPtr13
-**/
- UINT32 MemorySpdPtr13;
-
-/** Offset 0x0084 - MemorySpdPtr14
-**/
- UINT32 MemorySpdPtr14;
-
-/** Offset 0x0088 - MemorySpdPtr15
-**/
- UINT32 MemorySpdPtr15;
-
-/** Offset 0x008C - RcompResistor settings
- Indicates RcompResistor settings: Board-dependent
-**/
- UINT16 RcompResistor;
-
-/** Offset 0x008E - RcompTarget settings
- RcompTarget settings: board-dependent
-**/
- UINT16 RcompTarget[5];
-
-/** Offset 0x0098 - DqsMapCpu2DramCh0
-**/
- UINT8 DqsMapCpu2DramCh0[2];
-
-/** Offset 0x009A - DqsMapCpu2DramCh1
-**/
- UINT8 DqsMapCpu2DramCh1[2];
-
-/** Offset 0x009C - DqsMapCpu2DramCh2
-**/
- UINT8 DqsMapCpu2DramCh2[2];
-
-/** Offset 0x009E - DqsMapCpu2DramCh3
-**/
- UINT8 DqsMapCpu2DramCh3[2];
-
-/** Offset 0x00A0 - DqsMapCpu2DramCh4
-**/
- UINT8 DqsMapCpu2DramCh4[2];
-
-/** Offset 0x00A2 - DqsMapCpu2DramCh5
-**/
- UINT8 DqsMapCpu2DramCh5[2];
-
-/** Offset 0x00A4 - DqsMapCpu2DramCh6
-**/
- UINT8 DqsMapCpu2DramCh6[2];
-
-/** Offset 0x00A6 - DqsMapCpu2DramCh7
-**/
- UINT8 DqsMapCpu2DramCh7[2];
-
-/** Offset 0x00A8 - DqMapCpu2DramCh0
-**/
- UINT8 DqMapCpu2DramCh0[16];
-
-/** Offset 0x00B8 - DqMapCpu2DramCh1
-**/
- UINT8 DqMapCpu2DramCh1[16];
-
-/** Offset 0x00C8 - DqMapCpu2DramCh2
-**/
- UINT8 DqMapCpu2DramCh2[16];
-
-/** Offset 0x00D8 - DqMapCpu2DramCh3
-**/
- UINT8 DqMapCpu2DramCh3[16];
-
-/** Offset 0x00E8 - DqMapCpu2DramCh4
-**/
- UINT8 DqMapCpu2DramCh4[16];
-
-/** Offset 0x00F8 - DqMapCpu2DramCh5
-**/
- UINT8 DqMapCpu2DramCh5[16];
-
-/** Offset 0x0108 - DqMapCpu2DramCh6
-**/
- UINT8 DqMapCpu2DramCh6[16];
-
-/** Offset 0x0118 - DqMapCpu2DramCh7
-**/
- UINT8 DqMapCpu2DramCh7[16];
-
-/** Offset 0x0128 - Dqs Pins Interleaved Setting
- Indicates DqPinsInterleaved setting: board-dependent
- $EN_DIS
-**/
- UINT8 DqPinsInterleaved;
-
-/** Offset 0x0129 - Reserved
-**/
- UINT8 Reserved1[7];
-
-/** Offset 0x0130 - Tseg Size
- Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
- 0x0400000:4MB, 0x01000000:16MB
-**/
- UINT32 TsegSize;
-
-/** Offset 0x0134 - Reserved
-**/
- UINT8 Reserved2[3];
-
-/** Offset 0x0137 - Enable SMBus
- Enable/disable SMBus controller.
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x0138 - Spd Address Tabl
- Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
- if SPD Address is 00
-**/
- UINT8 SpdAddressTable[16];
-
-/** Offset 0x0148 - Platform Debug Consent
- Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks
- s0ix\n
- Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix
- is viable\n
- Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users
- 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual
-**/
- UINT8 PlatformDebugConsent;
-
-/** Offset 0x0149 - Reserved
-**/
- UINT8 Reserved3[14];
-
-/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1=Enable/Set
- $EN_DIS
-**/
- UINT8 X2ApicOptOut;
-
-/** Offset 0x0158 - Reserved
-**/
- UINT8 Reserved4[40];
-
-/** Offset 0x0180 - Disable VT-d
- 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
- $EN_DIS
-**/
- UINT8 VtdDisable;
-
-/** Offset 0x0181 - Reserved
-**/
- UINT8 Reserved5[4];
-
-/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
- Size of memory preallocated for internal graphics.
- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
- 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
- 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x0186 - Internal Graphics
- Enable/disable internal graphics.
- $EN_DIS
-**/
- UINT8 InternalGfx;
-
-/** Offset 0x0187 - Reserved
-**/
- UINT8 Reserved6;
-
-/** Offset 0x0188 - Board Type
- MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
- Halo, 7=UP Server
- 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
-**/
- UINT8 UserBd;
-
-/** Offset 0x0189 - Reserved
-**/
- UINT8 Reserved7[3];
-
-/** Offset 0x018C - SA GV
- System Agent dynamic frequency support and when enabled memory will be training
- at three different frequencies.
- 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
-**/
- UINT8 SaGv;
-
-/** Offset 0x018D - Reserved
-**/
- UINT8 Reserved8[2];
-
-/** Offset 0x018F - Rank Margin Tool
- Enable/disable Rank Margin Tool.
- $EN_DIS
-**/
- UINT8 RMT;
-
-/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch0;
-
-/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch1;
-
-/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control
- Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch2;
-
-/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control
- Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch3;
-
-/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch0;
-
-/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch1;
-
-/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control
- Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch2;
-
-/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control
- Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch3;
-
-/** Offset 0x0198 - Reserved
-**/
- UINT8 Reserved9[2];
-
-/** Offset 0x019A - Memory Reference Clock
- 100MHz, 133MHz.
- 0:133MHz, 1:100MHz
-**/
- UINT8 RefClk;
-
-/** Offset 0x019B - Reserved
-**/
- UINT8 Reserved10[22];
-
-/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
- 0: Disable, 1: Enable (Default) Azalia controller
- $EN_DIS
-**/
- UINT8 PchHdaEnable;
-
-/** Offset 0x01B2 - Enable PCH ISH Controller
- 0: Disable, 1: Enable (Default) ISH Controller
- $EN_DIS
-**/
- UINT8 PchIshEnable;
-
-/** Offset 0x01B3 - Reserved
-**/
- UINT8 Reserved11[107];
-
-/** Offset 0x021E - IMGU CLKOUT Configuration
- The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 ImguClkOutEn[6];
-
-/** Offset 0x0224 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 CpuPcieRpEnableMask;
-
-/** Offset 0x0228 - Reserved
-**/
- UINT8 Reserved12;
-
-/** Offset 0x0229 - RpClockReqMsgEnable
-**/
- UINT8 RpClockReqMsgEnable[3];
-
-/** Offset 0x022C - RpPcieThresholdBytes
-**/
- UINT8 RpPcieThresholdBytes[4];
-
-/** Offset 0x0230 - Reserved
-**/
- UINT8 Reserved13;
-
-/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device
- 0=Disabled,1(Default)=eDP, 2=MIPI DSI
- 0:Disabled, 1:eDP, 2:MIPI DSI
-**/
- UINT8 DdiPortAConfig;
-
-/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device
- 0(Default)=Disabled,1=eDP, 2=MIPI DSI
- 0:Disabled, 1:eDP, 2:MIPI DSI
-**/
- UINT8 DdiPortBConfig;
-
-/** Offset 0x0233 - Enable or disable HPD of DDI port A
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortAHpd;
-
-/** Offset 0x0234 - Enable or disable HPD of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBHpd;
-
-/** Offset 0x0235 - Enable or disable HPD of DDI port C
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCHpd;
-
-/** Offset 0x0236 - Enable or disable HPD of DDI port 1
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort1Hpd;
-
-/** Offset 0x0237 - Enable or disable HPD of DDI port 2
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort2Hpd;
-
-/** Offset 0x0238 - Enable or disable HPD of DDI port 3
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort3Hpd;
-
-/** Offset 0x0239 - Enable or disable HPD of DDI port 4
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort4Hpd;
-
-/** Offset 0x023A - Enable or disable DDC of DDI port A
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortADdc;
-
-/** Offset 0x023B - Enable or disable DDC of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBDdc;
-
-/** Offset 0x023C - Enable or disable DDC of DDI port C
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCDdc;
-
-/** Offset 0x023D - Enable DDC setting of DDI Port 1
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort1Ddc;
-
-/** Offset 0x023E - Enable DDC setting of DDI Port 2
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort2Ddc;
-
-/** Offset 0x023F - Enable DDC setting of DDI Port 3
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort3Ddc;
-
-/** Offset 0x0240 - Enable DDC setting of DDI Port 4
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort4Ddc;
-
-/** Offset 0x0241 - Reserved
-**/
- UINT8 Reserved14[141];
-
-/** Offset 0x02CE - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 DmiGen3RootPortPreset[8];
-
-/** Offset 0x02D6 - Reserved
-**/
- UINT8 Reserved15[150];
-
-/** Offset 0x036C - C6DRAM power gating feature
- This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
- power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
- feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
- $EN_DIS
-**/
- UINT8 EnableC6Dram;
-
-/** Offset 0x036D - Reserved
-**/
- UINT8 Reserved16[5];
-
-/** Offset 0x0372 - Hyper Threading Enable/Disable
- Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 HyperThreading;
-
-/** Offset 0x0373 - Reserved
-**/
- UINT8 Reserved17;
-
-/** Offset 0x0374 - CPU ratio value
- CPU ratio value. Valid Range 0 to 63
-**/
- UINT8 CpuRatio;
-
-/** Offset 0x0375 - Reserved
-**/
- UINT8 Reserved18[2];
-
-/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting
- <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
- 2: 400 MHz. - 3: Reserved
- 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
-**/
- UINT8 FClkFrequency;
-
-/** Offset 0x0378 - Reserved
-**/
- UINT8 Reserved19;
-
-/** Offset 0x0379 - Enable or Disable VMX
- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x037A - Reserved
-**/
- UINT8 Reserved20[20];
-
-/** Offset 0x038E - Enable or Disable TME
- Enable or Disable TME; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 TmeEnable;
-
-/** Offset 0x038F - Reserved
-**/
- UINT8 Reserved21[3];
-
-/** Offset 0x0392 - BiosGuard
- Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
- $EN_DIS
-**/
- UINT8 BiosGuard;
-
-/** Offset 0x0393
-**/
- UINT8 BiosGuardToolsInterface;
-
-/** Offset 0x0394 - Reserved
-**/
- UINT8 Reserved22[4];
-
-/** Offset 0x0398 - PrmrrSize
- Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
-**/
- UINT32 PrmrrSize;
-
-/** Offset 0x039C - SinitMemorySize
- Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
-**/
- UINT32 SinitMemorySize;
-
-/** Offset 0x03A0 - Reserved
-**/
- UINT8 Reserved23[8];
-
-/** Offset 0x03A8 - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x03AC - TxtDprMemorySize
- Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
-**/
- UINT32 TxtDprMemorySize;
-
-/** Offset 0x03B0 - Reserved
-**/
- UINT8 Reserved24[625];
-
-/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
- The number of elements in the RsvdSmbusAddressTable.
-**/
- UINT8 PchNumRsvdSmbusAddresses;
-
-/** Offset 0x0622 - Reserved
-**/
- UINT8 Reserved25[3];
-
-/** Offset 0x0625 - Usage type for ClkSrc
- 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
- (free running), 0xFF: not used
-**/
- UINT8 PcieClkSrcUsage[18];
-
-/** Offset 0x0637 - Reserved
-**/
- UINT8 Reserved26[14];
-
-/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
- Number of ClkReq signal assigned to ClkSrc
-**/
- UINT8 PcieClkSrcClkReq[18];
-
-/** Offset 0x0657 - Reserved
-**/
- UINT8 Reserved27[93];
-
-/** Offset 0x06B4 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpEnableMask;
-
-/** Offset 0x06B8 - Reserved
-**/
- UINT8 Reserved28[2];
-
-/** Offset 0x06BA - Enable HD Audio Link
- Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkHdaEnable;
-
-/** Offset 0x06BB - Reserved
-**/
- UINT8 Reserved29[3];
-
-/** Offset 0x06BE - Enable HD Audio DMIC_N Link
- Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
-**/
- UINT8 PchHdaAudioLinkDmicEnable[2];
-
-/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
-**/
- UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-
-/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
-**/
- UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-
-/** Offset 0x06D0 - Enable HD Audio DSP
- Enable/disable HD Audio DSP feature.
- $EN_DIS
-**/
- UINT8 PchHdaDspEnable;
-
-/** Offset 0x06D1 - Reserved
-**/
- UINT8 Reserved30[3];
-
-/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
- Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
-**/
- UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-
-/** Offset 0x06DC - Enable HD Audio SSP0 Link
- Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
-**/
- UINT8 PchHdaAudioLinkSspEnable[6];
-
-/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
- Enable/disable HD Audio SNDW#N link. Muxed with HDA.
-**/
- UINT8 PchHdaAudioLinkSndwEnable[4];
-
-/** Offset 0x06E6 - iDisp-Link Frequency
- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
- 4: 96MHz, 3: 48MHz
-**/
- UINT8 PchHdaIDispLinkFrequency;
-
-/** Offset 0x06E7 - iDisp-Link T-mode
- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
- 0: 2T, 2: 4T, 3: 8T, 4: 16T
-**/
- UINT8 PchHdaIDispLinkTmode;
-
-/** Offset 0x06E8 - iDisplay Audio Codec disconnection
- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
- $EN_DIS
-**/
- UINT8 PchHdaIDispCodecDisconnect;
-
-/** Offset 0x06E9 - Debug Interfaces
- Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
- BIT2 - Not used.
-**/
- UINT8 PcdDebugInterfaceFlags;
-
-/** Offset 0x06EA - Serial Io Uart Debug Controller Number
- Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
- Core interface, it cannot be used for debug purpose.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 SerialIoUartDebugControllerNumber;
-
-/** Offset 0x06EB - Reserved
-**/
- UINT8 Reserved31[13];
-
-/** Offset 0x06F8 - ISA Serial Base selection
- Select ISA Serial Base address. Default is 0x3F8.
- 0:0x3F8, 1:0x2F8
-**/
- UINT8 PcdIsaSerialUartBase;
-
-/** Offset 0x06F9 - Reserved
-**/
- UINT8 Reserved32[4];
-
-/** Offset 0x06FD - MRC Safe Config
- Enables/Disable MRC Safe Config
- $EN_DIS
-**/
- UINT8 MrcSafeConfig;
-
-/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
- Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie0En;
-
-/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
- Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie1En;
-
-/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
- Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie2En;
-
-/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
- Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie3En;
-
-/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
- Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
- $EN_DIS
-**/
- UINT8 TcssXhciEn;
-
-/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
- Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
- $EN_DIS
-**/
- UINT8 TcssXdciEn;
-
-/** Offset 0x0704 - TCSS DMA0 Enable
- Set TCSS DMA0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma0En;
-
-/** Offset 0x0705 - TCSS DMA1 Enable
- Set TCSS DMA1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma1En;
-
-/** Offset 0x0706 - Reserved
-**/
- UINT8 Reserved33[2];
-
-/** Offset 0x0708 - Early Command Training
- Enables/Disable Early Command Training
- $EN_DIS
-**/
- UINT8 ECT;
-
-/** Offset 0x0709 - Reserved
-**/
- UINT8 Reserved34[65];
-
-/** Offset 0x074A - Ch Hash Mask
- Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
- BITS [19:6] Default is 0x30CC
-**/
- UINT16 ChHashMask;
-
-/** Offset 0x074C - Reserved
-**/
- UINT8 Reserved35[66];
-
-/** Offset 0x078E - PcdSerialDebugLevel
- Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
- Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
- Info & Verbose.
- 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
-**/
- UINT8 PcdSerialDebugLevel;
-
-/** Offset 0x078F - Reserved
-**/
- UINT8 Reserved36[2];
-
-/** Offset 0x0791 - Safe Mode Support
- This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
- $EN_DIS
-**/
- UINT8 SafeMode;
-
-/** Offset 0x0792 - Reserved
-**/
- UINT8 Reserved37[2];
-
-/** Offset 0x0794 - TCSS USB Port Enable
- Bitmap for per port enabling
-**/
- UINT8 UsbTcPortEnPreMem;
-
-/** Offset 0x0795 - Reserved
-**/
- UINT8 Reserved38[33];
-
-/** Offset 0x07B6 - Command Pins Mapping
- BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
- 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
-**/
- UINT8 Lp5CccConfig;
-
-/** Offset 0x07B7 - Reserved
-**/
- UINT8 Reserved39[12];
-
-/** Offset 0x07C3 - Skip external display device scanning
- Enable: Do not scan for external display device, Disable (Default): Scan external
- display devices
- $EN_DIS
-**/
- UINT8 SkipExtGfxScan;
-
-/** Offset 0x07C4 - Reserved
-**/
- UINT8 Reserved40;
-
-/** Offset 0x07C5 - Lock PCU Thermal Management registers
- Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 LockPTMregs;
-
-/** Offset 0x07C6 - Reserved
-**/
- UINT8 Reserved41[131];
-
-/** Offset 0x0849 - Skip CPU replacement check
- Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
- $EN_DIS
-**/
- UINT8 SkipCpuReplacementCheck;
-
-/** Offset 0x084A - Reserved
-**/
- UINT8 Reserved42[292];
-
-/** Offset 0x096E - Serial Io Uart Debug Mode
- Select SerialIo Uart Controller mode
- 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 SerialIoUartDebugMode;
-
-/** Offset 0x096F - Reserved
-**/
- UINT8 Reserved43[185];
-
-/** Offset 0x0A28 - GPIO Override
- Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
- before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
- configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
-**/
- UINT8 GpioOverride;
-
-/** Offset 0x0A29 - Reserved
-**/
- UINT8 Reserved44[23];
-} FSP_M_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x0A40
-**/
- UINT8 UnusedUpdSpace25[6];
-
-/** Offset 0x0A46
-**/
- UINT16 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved0[2]; + +/** Offset 0x004C - MemorySpdPtr00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - MemorySpdPtr01 +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0054 - MemorySpdPtr02 +**/ + UINT32 MemorySpdPtr02; + +/** Offset 0x0058 - MemorySpdPtr03 +**/ + UINT32 MemorySpdPtr03; + +/** Offset 0x005C - MemorySpdPtr04 +**/ + UINT32 MemorySpdPtr04; + +/** Offset 0x0060 - MemorySpdPtr05 +**/ + UINT32 MemorySpdPtr05; + +/** Offset 0x0064 - MemorySpdPtr06 +**/ + UINT32 MemorySpdPtr06; + +/** Offset 0x0068 - MemorySpdPtr07 +**/ + UINT32 MemorySpdPtr07; + +/** Offset 0x006C - MemorySpdPtr08 +**/ + UINT32 MemorySpdPtr08; + +/** Offset 0x0070 - MemorySpdPtr09 +**/ + UINT32 MemorySpdPtr09; + +/** Offset 0x0074 - MemorySpdPtr10 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0078 - MemorySpdPtr11 +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x007C - MemorySpdPtr12 +**/ + UINT32 MemorySpdPtr12; + +/** Offset 0x0080 - MemorySpdPtr13 +**/ + UINT32 MemorySpdPtr13; + +/** Offset 0x0084 - MemorySpdPtr14 +**/ + UINT32 MemorySpdPtr14; + +/** Offset 0x0088 - MemorySpdPtr15 +**/ + UINT32 MemorySpdPtr15; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - DqsMapCpu2DramCh0 +**/ + UINT8 DqsMapCpu2DramCh0[2]; + +/** Offset 0x009A - DqsMapCpu2DramCh1 +**/ + UINT8 DqsMapCpu2DramCh1[2]; + +/** Offset 0x009C - DqsMapCpu2DramCh2 +**/ + UINT8 DqsMapCpu2DramCh2[2]; + +/** Offset 0x009E - DqsMapCpu2DramCh3 +**/ + UINT8 DqsMapCpu2DramCh3[2]; + +/** Offset 0x00A0 - DqsMapCpu2DramCh4 +**/ + UINT8 DqsMapCpu2DramCh4[2]; + +/** Offset 0x00A2 - DqsMapCpu2DramCh5 +**/ + UINT8 DqsMapCpu2DramCh5[2]; + +/** Offset 0x00A4 - DqsMapCpu2DramCh6 +**/ + UINT8 DqsMapCpu2DramCh6[2]; + +/** Offset 0x00A6 - DqsMapCpu2DramCh7 +**/ + UINT8 DqsMapCpu2DramCh7[2]; + +/** Offset 0x00A8 - DqMapCpu2DramCh0 +**/ + UINT8 DqMapCpu2DramCh0[16]; + +/** Offset 0x00B8 - DqMapCpu2DramCh1 +**/ + UINT8 DqMapCpu2DramCh1[16]; + +/** Offset 0x00C8 - DqMapCpu2DramCh2 +**/ + UINT8 DqMapCpu2DramCh2[16]; + +/** Offset 0x00D8 - DqMapCpu2DramCh3 +**/ + UINT8 DqMapCpu2DramCh3[16]; + +/** Offset 0x00E8 - DqMapCpu2DramCh4 +**/ + UINT8 DqMapCpu2DramCh4[16]; + +/** Offset 0x00F8 - DqMapCpu2DramCh5 +**/ + UINT8 DqMapCpu2DramCh5[16]; + +/** Offset 0x0108 - DqMapCpu2DramCh6 +**/ + UINT8 DqMapCpu2DramCh6[16]; + +/** Offset 0x0118 - DqMapCpu2DramCh7 +**/ + UINT8 DqMapCpu2DramCh7[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Reserved +**/ + UINT8 Reserved1[7]; + +/** Offset 0x0130 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0134 - Reserved +**/ + UINT8 Reserved2[3]; + +/** Offset 0x0137 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0138 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0148 - Platform Debug Consent + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix + is viable\n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x0149 - Reserved +**/ + UINT8 Reserved3[14]; + +/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x0158 - Reserved +**/ + UINT8 Reserved4[40]; + +/** Offset 0x0180 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0181 - Reserved +**/ + UINT8 Reserved5[4]; + +/** Offset 0x0185 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x0186 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x0187 - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x0188 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x0189 - Reserved +**/ + UINT8 Reserved7[3]; + +/** Offset 0x018C - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x018D - Reserved +**/ + UINT8 Reserved8[2]; + +/** Offset 0x018F - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control + Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch0; + +/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control + Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch1; + +/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control + Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch2; + +/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control + Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc0Ch3; + +/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control + Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch0; + +/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control + Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch1; + +/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control + Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch2; + +/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control + Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmMc1Ch3; + +/** Offset 0x0198 - Reserved +**/ + UINT8 Reserved9[2]; + +/** Offset 0x019A - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x019B - Reserved +**/ + UINT8 Reserved10[22]; + +/** Offset 0x01B1 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01B2 - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01B3 - Reserved +**/ + UINT8 Reserved11[107]; + +/** Offset 0x021E - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x0224 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0228 - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x0229 - RpClockReqMsgEnable +**/ + UINT8 RpClockReqMsgEnable[3]; + +/** Offset 0x022C - RpPcieThresholdBytes +**/ + UINT8 RpPcieThresholdBytes[4]; + +/** Offset 0x0230 - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x0233 - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x0234 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0235 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0236 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0237 - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0238 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0239 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x023A - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x023B - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x023C - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x023D - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x023E - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x023F - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0240 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0241 - Reserved +**/ + UINT8 Reserved14[141]; + +/** Offset 0x02CE - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x02D6 - Reserved +**/ + UINT8 Reserved15[150]; + +/** Offset 0x036C - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x036D - Reserved +**/ + UINT8 Reserved16[5]; + +/** Offset 0x0372 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0373 - Reserved +**/ + UINT8 Reserved17; + +/** Offset 0x0374 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0375 - Reserved +**/ + UINT8 Reserved18[2]; + +/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting + <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x0378 - Reserved +**/ + UINT8 Reserved19; + +/** Offset 0x0379 - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x037A - Reserved +**/ + UINT8 Reserved20[20]; + +/** Offset 0x038E - Enable or Disable TME + Enable or Disable TME; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x038F - Reserved +**/ + UINT8 Reserved21[3]; + +/** Offset 0x0392 - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x0393 +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x0394 - Reserved +**/ + UINT8 Reserved22[4]; + +/** Offset 0x0398 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x039C - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x03A0 - Reserved +**/ + UINT8 Reserved23[8]; + +/** Offset 0x03A8 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x03AC - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x03B0 - Reserved +**/ + UINT8 Reserved24[625]; + +/** Offset 0x0621 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0622 - Reserved +**/ + UINT8 Reserved25[3]; + +/** Offset 0x0625 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x0637 - Reserved +**/ + UINT8 Reserved26[14]; + +/** Offset 0x0645 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x0657 - Reserved +**/ + UINT8 Reserved27[93]; + +/** Offset 0x06B4 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x06B8 - Reserved +**/ + UINT8 Reserved28[2]; + +/** Offset 0x06BA - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x06BB - Reserved +**/ + UINT8 Reserved29[3]; + +/** Offset 0x06BE - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number) + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x06D0 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x06D1 - Reserved +**/ + UINT8 Reserved30[3]; + +/** Offset 0x06D4 - DMIC<N> Data Pin Muxing + Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x06DC - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x06E6 - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x06E7 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x06E8 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x06E9 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x06EA - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x06EB - Reserved +**/ + UINT8 Reserved31[13]; + +/** Offset 0x06F8 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x06F9 - Reserved +**/ + UINT8 Reserved32[4]; + +/** Offset 0x06FD - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x0704 - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x0705 - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x0706 - Reserved +**/ + UINT8 Reserved33[2]; + +/** Offset 0x0708 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0709 - Reserved +**/ + UINT8 Reserved34[65]; + +/** Offset 0x074A - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x074C - Reserved +**/ + UINT8 Reserved35[66]; + +/** Offset 0x078E - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x078F - Reserved +**/ + UINT8 Reserved36[2]; + +/** Offset 0x0791 - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x0792 - Reserved +**/ + UINT8 Reserved37[2]; + +/** Offset 0x0794 - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x0795 - Reserved +**/ + UINT8 Reserved38[33]; + +/** Offset 0x07B6 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x07B7 - Reserved +**/ + UINT8 Reserved39[12]; + +/** Offset 0x07C3 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x07C4 - Reserved +**/ + UINT8 Reserved40; + +/** Offset 0x07C5 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x07C6 - Reserved +**/ + UINT8 Reserved41[131]; + +/** Offset 0x0849 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x084A - Reserved +**/ + UINT8 Reserved42[292]; + +/** Offset 0x096E - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x096F - Reserved +**/ + UINT8 Reserved43[185]; + +/** Offset 0x0A28 - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x0A29 - Reserved +**/ + UINT8 Reserved44[23]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0A40 +**/ + UINT8 UnusedUpdSpace25[6]; + +/** Offset 0x0A46 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 8a92e001af..cb3c95838c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1,895 +1,895 @@ -/** @file
-
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Reserved
-**/
- UINT8 Reserved0[16];
-
-/** Offset 0x0050 - Graphics Configuration Ptr
- Points to VBT
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x0054 - Enable Device 4
- Enable/disable Device 4
- $EN_DIS
-**/
- UINT8 Device4Enable;
-
-/** Offset 0x0055 - Reserved
-**/
- UINT8 Reserved1[3];
-
-/** Offset 0x0058 - MicrocodeRegionBase
- Memory Base of Microcode Updates
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x005C - MicrocodeRegionSize
- Size of Microcode Updates
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0060 - Reserved
-**/
- UINT8 Reserved2;
-
-/** Offset 0x0061 - Enable SATA SALP Support
- Enable/disable SATA Aggressive Link Power Management.
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0062 - Enable SATA ports
- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
- and so on.
-**/
- UINT8 SataPortsEnable[8];
-
-/** Offset 0x006A - Enable SATA DEVSLP Feature
- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
- port, byte0 for port0, byte1 for port1, and so on.
-**/
- UINT8 SataPortsDevSlp[8];
-
-/** Offset 0x0072 - Reserved
-**/
- UINT8 Reserved3[34];
-
-/** Offset 0x0094 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb20Enable[16];
-
-/** Offset 0x00A4 - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb30Enable[10];
-
-/** Offset 0x00AE - Enable xDCI controller
- Enable/disable to xDCI controller.
- $EN_DIS
-**/
- UINT8 XdciEnable;
-
-/** Offset 0x00AF - Reserved
-**/
- UINT8 Reserved4[26];
-
-/** Offset 0x00C9 - Enable SATA
- Enable/disable SATA controller.
- $EN_DIS
-**/
- UINT8 SataEnable;
-
-/** Offset 0x00CA - SATA Mode
- Select SATA controller working mode.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x00CB - SPIn Device Mode
- Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
- modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
-**/
- UINT8 SerialIoSpiMode[7];
-
-/** Offset 0x00D2 - Reserved
-**/
- UINT8 Reserved5[35];
-
-/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW
- Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
- SPI1, ... Available options: 0:HW, 1:SW
-**/
- UINT8 SerialIoSpiCsMode[7];
-
-/** Offset 0x00FC - SPIn Default Chip Select State Low/High
- Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
- Available options: 0:Low, 1:High
-**/
- UINT8 SerialIoSpiCsState[7];
-
-/** Offset 0x0103 - UARTn Device Mode
- Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
- modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 SerialIoUartMode[7];
-
-/** Offset 0x010A - Reserved
-**/
- UINT8 Reserved6[65];
-
-/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines
- Enables UART hardware flow control, CTS and RTS lines.
-**/
- UINT8 SerialIoUartAutoFlow[7];
-
-/** Offset 0x0152 - Reserved
-**/
- UINT8 Reserved7[2];
-
-/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
- Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
- for possible values.
-**/
- UINT32 SerialIoUartRtsPinMuxPolicy[7];
-
-/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy
- Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
- for possible values.
-**/
- UINT32 SerialIoUartCtsPinMuxPolicy[7];
-
-/** Offset 0x018C - SerialIoUartRxPinMuxPolicy
- Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
- possible values.
-**/
- UINT32 SerialIoUartRxPinMuxPolicy[7];
-
-/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy
- Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
- possible values.
-**/
- UINT32 SerialIoUartTxPinMuxPolicy[7];
-
-/** Offset 0x01C4 - UART Number For Debug Purpose
- UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
- 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
- for debug purpose.
- 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
-**/
- UINT8 SerialIoDebugUartNumber;
-
-/** Offset 0x01C5 - Reserved
-**/
- UINT8 Reserved8[7];
-
-/** Offset 0x01CC - I2Cn Device Mode
- Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
- modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
-**/
- UINT8 SerialIoI2cMode[8];
-
-/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing
- Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSdaPinMux[8];
-
-/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing
- Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSclPinMux[8];
-
-/** Offset 0x0214 - Reserved
-**/
- UINT8 Reserved9[192];
-
-/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias
- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
-**/
- UINT8 Usb2PhyPetxiset[16];
-
-/** Offset 0x02E4 - USB Per Port HS Transmitter Bias
- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
-**/
- UINT8 Usb2PhyTxiset[16];
-
-/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis
- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
-**/
- UINT8 Usb2PhyPredeemp[16];
-
-/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis
- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
- One byte for each port.
-**/
- UINT8 Usb2PhyPehalfbit[16];
-
-/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmphEnable[10];
-
-/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmph[10];
-
-/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-
-/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment
- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
- = 00h</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmp[10];
-
-/** Offset 0x033C - Reserved
-**/
- UINT8 Reserved10[80];
-
-/** Offset 0x038C - Enable LAN
- Enable/disable LAN controller.
- $EN_DIS
-**/
- UINT8 PchLanEnable;
-
-/** Offset 0x038D - Reserved
-**/
- UINT8 Reserved11[11];
-
-/** Offset 0x0398 - PCIe PTM enable/disable
- Enable/disable Precision Time Measurement for PCIE Root Ports.
-**/
- UINT8 PciePtm[28];
-
-/** Offset 0x03B4 - Reserved
-**/
- UINT8 Reserved12[81];
-
-/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to low current mode voltage.
-**/
- UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
-
-/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to retention mode voltage.
-**/
- UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-
-/** Offset 0x0407 - Reserved
-**/
- UINT8 Reserved13;
-
-/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
- This field has 1us resolution. When value is 0 Transition to 0V is disabled.
-**/
- UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
-
-/** Offset 0x040A - Reserved
-**/
- UINT8 Reserved14[50];
-
-/** Offset 0x043C - CNVi Configuration
- This option allows for automatic detection of Connectivity Solution. [Auto Detection]
- assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
- 0:Disable, 1:Auto
-**/
- UINT8 CnviMode;
-
-/** Offset 0x043D - Reserved
-**/
- UINT8 Reserved15;
-
-/** Offset 0x043E - CNVi BT Core
- Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtCore;
-
-/** Offset 0x043F - CNVi BT Audio Offload
- Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtAudioOffload;
-
-/** Offset 0x0440 - Reserved
-**/
- UINT8 Reserved16[4];
-
-/** Offset 0x0444 - CNVi RF_RESET pin muxing
- Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
- or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
-**/
- UINT32 CnviRfResetPinMux;
-
-/** Offset 0x0448 - CNVi CLKREQ pin muxing
- Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
- or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
- in GpioPins*.h.
-**/
- UINT32 CnviClkreqPinMux;
-
-/** Offset 0x044C - Reserved
-**/
- UINT8 Reserved17[172];
-
-/** Offset 0x04F8 - CdClock Frequency selection
- 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
- 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
- 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
- 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
-**/
- UINT8 CdClock;
-
-/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
- <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
- Disable: FSP will NOT initialize the framebuffer.
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x04FA - Enable D3 Hot in TCSS
- This policy will enable/disable D3 hot support in IOM
- $EN_DIS
-**/
- UINT8 D3HotEnable;
-
-/** Offset 0x04FB - Reserved
-**/
- UINT8 Reserved18;
-
-/** Offset 0x04FC - TypeC port GPIO setting
- GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
- in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
- = AlderLake)
-**/
- UINT32 IomTypeCPortPadCfg[8];
-
-/** Offset 0x051C - Reserved
-**/
- UINT8 Reserved19[8];
-
-/** Offset 0x0524 - Enable D3 Cold in TCSS
- This policy will enable/disable D3 cold support in IOM
- $EN_DIS
-**/
- UINT8 D3ColdEnable;
-
-/** Offset 0x0525 - Reserved
-**/
- UINT8 Reserved20[16];
-
-/** Offset 0x0535 - Enable VMD controller
- Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
- $EN_DIS
-**/
- UINT8 VmdEnable;
-
-/** Offset 0x0536 - Reserved
-**/
- UINT8 Reserved21[120];
-
-/** Offset 0x05AE - TCSS Aux Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssAuxOri;
-
-/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssHslOri;
-
-/** Offset 0x05B2 - Reserved
-**/
- UINT8 Reserved22;
-
-/** Offset 0x05B3 - ITBT Root Port Enable
- ITBT Root Port Enable, 0:Disable, 1:Enable
- 0:Disable, 1:Enable
-**/
- UINT8 ITbtPcieRootPortEn[4];
-
-/** Offset 0x05B7 - Reserved
-**/
- UINT8 Reserved23[3];
-
-/** Offset 0x05BA - ITbtConnectTopology Timeout value
- ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
- is 0-10000. 100 = 100 ms.
-**/
- UINT16 ITbtConnectTopologyTimeoutInMs;
-
-/** Offset 0x05BC - Reserved
-**/
- UINT8 Reserved24[7];
-
-/** Offset 0x05C3 - Enable/Disable PTM
- This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
- $EN_DIS
-**/
- UINT8 PtmEnabled[4];
-
-/** Offset 0x05C7 - Reserved
-**/
- UINT8 Reserved25[200];
-
-/** Offset 0x068F - Skip Multi-Processor Initialization
- When this is skipped, boot loader must initialize processors before SilicionInit
- API. </b>0: Initialize; <b>1: Skip
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x0690 - Reserved
-**/
- UINT8 Reserved26[8];
-
-/** Offset 0x0698 - CpuMpPpi
- <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
- If not NULL, FSP will use the boot loader's implementation of multiprocessing.
- See section 5.1.4 of the FSP Integration Guide for more details.
-**/
- UINT32 CpuMpPpi;
-
-/** Offset 0x069C - Reserved
-**/
- UINT8 Reserved27[70];
-
-/** Offset 0x06E2 - Enable Power Optimizer
- Enable DMI Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 PchPwrOptEnable;
-
-/** Offset 0x06E3 - Reserved
-**/
- UINT8 Reserved28[33];
-
-/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
- Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshSpiCs0Enable[1];
-
-/** Offset 0x0705 - Reserved
-**/
- UINT8 Reserved29[2];
-
-/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
- Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshSpiEnable[1];
-
-/** Offset 0x0708 - Enable PCH ISH UART pins assigned
- Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshUartEnable[2];
-
-/** Offset 0x070A - Enable PCH ISH I2C pins assigned
- Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshI2cEnable[3];
-
-/** Offset 0x070D - Enable PCH ISH GP pins assigned
- Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshGpEnable[8];
-
-/** Offset 0x0715 - Reserved
-**/
- UINT8 Reserved30[2];
-
-/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
- protection.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosLock;
-
-/** Offset 0x0718 - Reserved
-**/
- UINT8 Reserved31[2];
-
-/** Offset 0x071A - RTC Cmos Memory Lock
- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
- and and lower 128-byte bank of RTC RAM.
- $EN_DIS
-**/
- UINT8 RtcMemoryLock;
-
-/** Offset 0x071B - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 PcieRpHotPlug[28];
-
-/** Offset 0x0737 - Reserved
-**/
- UINT8 Reserved32[56];
-
-/** Offset 0x076F - Enable PCIE RP Clk Req Detect
- Probe CLKREQ# signal before enabling CLKREQ# based power management.
-**/
- UINT8 PcieRpClkReqDetect[28];
-
-/** Offset 0x078B - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 PcieRpAdvancedErrorReporting[28];
-
-/** Offset 0x07A7 - Reserved
-**/
- UINT8 Reserved33[196];
-
-/** Offset 0x086B - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 PcieRpMaxPayload[28];
-
-/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
- Assign THC Port 0
- 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
-**/
- UINT8 ThcPort0Assignment;
-
-/** Offset 0x0888 - Reserved
-**/
- UINT8 Reserved34[5];
-
-/** Offset 0x088D - Touch Host Controller Port 1 Assignment
- Assign THC Port 1
- 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
-**/
- UINT8 ThcPort1Assignment;
-
-/** Offset 0x088E - Reserved
-**/
- UINT8 Reserved35[91];
-
-/** Offset 0x08E9 - PCIE RP Aspm
- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
- PchPcieAspmAutoConfig.
-**/
- UINT8 PcieRpAspm[28];
-
-/** Offset 0x0905 - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
- Default is PchPcieL1SubstatesL1_1_2.
-**/
- UINT8 PcieRpL1Substates[28];
-
-/** Offset 0x0921 - Reserved
-**/
- UINT8 Reserved36[28];
-
-/** Offset 0x093D - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 PcieRpLtrEnable[28];
-
-/** Offset 0x0959 - Reserved
-**/
- UINT8 Reserved37[132];
-
-/** Offset 0x09DD - PCH Sata Pwr Opt Enable
- SATA Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x09DE - Reserved
-**/
- UINT8 Reserved38[50];
-
-/** Offset 0x0A10 - Enable SATA Port DmVal
- DITO multiplier. Default is 15.
-**/
- UINT8 SataPortsDmVal[8];
-
-/** Offset 0x0A18 - Enable SATA Port DmVal
- DEVSLP Idle Timeout (DITO), Default is 625.
-**/
- UINT16 SataPortsDitoVal[8];
-
-/** Offset 0x0A28 - Reserved
-**/
- UINT8 Reserved39[62];
-
-/** Offset 0x0A66 - USB2 Port Over Current Pin
- Describe the specific over current pin number of USB 2.0 Port N.
-**/
- UINT8 Usb2OverCurrentPin[16];
-
-/** Offset 0x0A76 - USB3 Port Over Current Pin
- Describe the specific over current pin number of USB 3.0 Port N.
-**/
- UINT8 Usb3OverCurrentPin[10];
-
-/** Offset 0x0A80 - Reserved
-**/
- UINT8 Reserved40[16];
-
-/** Offset 0x0A90 - Enable 8254 Static Clock Gating
- Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
- might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
- legacy OS using 8254 timer. Also enable this while S0ix is enabled.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGating;
-
-/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
- This is only applicable when Enable8254ClockGating is disabled. FSP will do the
- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
- avoids the SMI requirement for the programming.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGatingOnS3;
-
-/** Offset 0x0A92 - Reserved
-**/
- UINT8 Reserved41;
-
-/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
- Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
- Default is 0: Disabled
- 0: Disabled, 1: Dynamic Configuration
-**/
- UINT8 HybridStorageMode;
-
-/** Offset 0x0A94 - Reserved
-**/
- UINT8 Reserved42[93];
-
-/** Offset 0x0AF1 - Enable PS_ON.
- PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
- target that will be required by the California Energy Commission (CEC). When FALSE,
- PS_ON is to be disabled.
- $EN_DIS
-**/
- UINT8 PsOnEnable;
-
-/** Offset 0x0AF2 - Reserved
-**/
- UINT8 Reserved43[318];
-
-/** Offset 0x0C30 - RpPtmBytes
-**/
- UINT8 RpPtmBytes[4];
-
-/** Offset 0x0C34 - Reserved
-**/
- UINT8 Reserved44[95];
-
-/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x0C94 - Reserved
-**/
- UINT8 Reserved45;
-
-/** Offset 0x0C95 - GT Frequency Limit
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
-**/
- UINT8 GtFreqMax;
-
-/** Offset 0x0C96 - Reserved
-**/
- UINT8 Reserved46[24];
-
-/** Offset 0x0CAE - Enable or Disable HWP
- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
- 2-3:Reserved
- $EN_DIS
-**/
- UINT8 Hwp;
-
-/** Offset 0x0CAF - Reserved
-**/
- UINT8 Reserved47[8];
-
-/** Offset 0x0CB7 - TCC Activation Offset
- TCC Activation Offset. Offset from factory set TCC activation temperature at which
- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
- Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
- <b>10</b>, For all other SKUs the recommended default are <b>0</b>
-**/
- UINT8 TccActivationOffset;
-
-/** Offset 0x0CB8 - Reserved
-**/
- UINT8 Reserved48[34];
-
-/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Cx;
-
-/** Offset 0x0CDB - Reserved
-**/
- UINT8 Reserved49[196];
-
-/** Offset 0x0D9F - Enable LOCKDOWN SMI
- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
- $EN_DIS
-**/
- UINT8 PchLockDownGlobalSmi;
-
-/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosInterface;
-
-/** Offset 0x0DA1 - Unlock all GPIO pads
- Force all GPIO pads to be unlocked for debug purpose.
- $EN_DIS
-**/
- UINT8 PchUnlockGpioPads;
-
-/** Offset 0x0DA2 - Reserved
-**/
- UINT8 Reserved50[2];
-
-/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[28];
-
-/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxNoSnoopLatency[28];
-
-/** Offset 0x0E14 - Reserved
-**/
- UINT8 Reserved51[313];
-
-/** Offset 0x0F4D - LpmStateEnableMask
-**/
- UINT8 LpmStateEnableMask;
-
-/** Offset 0x0F4E - Reserved
-**/
- UINT8 Reserved52[122];
-} FSP_S_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPS_ARCH_UPD FspsArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x0FC8
-**/
- UINT8 UnusedUpdSpace43[6];
-
-/** Offset 0x0FCE
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Reserved +**/ + UINT8 Reserved0[16]; + +/** Offset 0x0050 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0054 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0055 - Reserved +**/ + UINT8 Reserved1[3]; + +/** Offset 0x0058 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x005C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0060 - Reserved +**/ + UINT8 Reserved2; + +/** Offset 0x0061 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0062 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x006A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0072 - Reserved +**/ + UINT8 Reserved3[34]; + +/** Offset 0x0094 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x00A4 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x00AE - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x00AF - Reserved +**/ + UINT8 Reserved4[26]; + +/** Offset 0x00C9 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x00CA - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x00CB - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x00D2 - Reserved +**/ + UINT8 Reserved5[35]; + +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x00FC - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x0103 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x010A - Reserved +**/ + UINT8 Reserved6[65]; + +/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x0152 - Reserved +**/ + UINT8 Reserved7[2]; + +/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x018C - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x01C4 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x01C5 - Reserved +**/ + UINT8 Reserved8[7]; + +/** Offset 0x01CC - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x0214 - Reserved +**/ + UINT8 Reserved9[192]; + +/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02E4 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default + = 00h</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x033C - Reserved +**/ + UINT8 Reserved10[80]; + +/** Offset 0x038C - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x038D - Reserved +**/ + UINT8 Reserved11[11]; + +/** Offset 0x0398 - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[28]; + +/** Offset 0x03B4 - Reserved +**/ + UINT8 Reserved12[81]; + +/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x0407 - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x040A - Reserved +**/ + UINT8 Reserved14[50]; + +/** Offset 0x043C - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x043D - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x043E - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x043F - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x0440 - Reserved +**/ + UINT8 Reserved16[4]; + +/** Offset 0x0444 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0448 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* + in GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x044C - Reserved +**/ + UINT8 Reserved17[172]; + +/** Offset 0x04F8 - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: + 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, + 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit + <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x04FA - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x04FB - Reserved +**/ + UINT8 Reserved18; + +/** Offset 0x04FC - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl + = AlderLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x051C - Reserved +**/ + UINT8 Reserved19[8]; + +/** Offset 0x0524 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x0525 - Reserved +**/ + UINT8 Reserved20[16]; + +/** Offset 0x0535 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0536 - Reserved +**/ + UINT8 Reserved21[120]; + +/** Offset 0x05AE - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x05B0 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x05B2 - Reserved +**/ + UINT8 Reserved22; + +/** Offset 0x05B3 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x05B7 - Reserved +**/ + UINT8 Reserved23[3]; + +/** Offset 0x05BA - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x05BC - Reserved +**/ + UINT8 Reserved24[7]; + +/** Offset 0x05C3 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x05C7 - Reserved +**/ + UINT8 Reserved25[200]; + +/** Offset 0x068F - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. </b>0: Initialize; <b>1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x0690 - Reserved +**/ + UINT8 Reserved26[8]; + +/** Offset 0x0698 - CpuMpPpi + <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x069C - Reserved +**/ + UINT8 Reserved27[70]; + +/** Offset 0x06E2 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x06E3 - Reserved +**/ + UINT8 Reserved28[33]; + +/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x0705 - Reserved +**/ + UINT8 Reserved29[2]; + +/** Offset 0x0707 - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiEnable[1]; + +/** Offset 0x0708 - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshUartEnable[2]; + +/** Offset 0x070A - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshI2cEnable[3]; + +/** Offset 0x070D - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshGpEnable[8]; + +/** Offset 0x0715 - Reserved +**/ + UINT8 Reserved30[2]; + +/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x0718 - Reserved +**/ + UINT8 Reserved31[2]; + +/** Offset 0x071A - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x071B - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[28]; + +/** Offset 0x0737 - Reserved +**/ + UINT8 Reserved32[56]; + +/** Offset 0x076F - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[28]; + +/** Offset 0x078B - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[28]; + +/** Offset 0x07A7 - Reserved +**/ + UINT8 Reserved33[196]; + +/** Offset 0x086B - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[28]; + +/** Offset 0x0887 - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 +**/ + UINT8 ThcPort0Assignment; + +/** Offset 0x0888 - Reserved +**/ + UINT8 Reserved34[5]; + +/** Offset 0x088D - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x088E - Reserved +**/ + UINT8 Reserved35[91]; + +/** Offset 0x08E9 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[28]; + +/** Offset 0x0905 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[28]; + +/** Offset 0x0921 - Reserved +**/ + UINT8 Reserved36[28]; + +/** Offset 0x093D - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[28]; + +/** Offset 0x0959 - Reserved +**/ + UINT8 Reserved37[132]; + +/** Offset 0x09DD - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x09DE - Reserved +**/ + UINT8 Reserved38[50]; + +/** Offset 0x0A10 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x0A18 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x0A28 - Reserved +**/ + UINT8 Reserved39[62]; + +/** Offset 0x0A66 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x0A76 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0A80 - Reserved +**/ + UINT8 Reserved40[16]; + +/** Offset 0x0A90 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0A92 - Reserved +**/ + UINT8 Reserved41; + +/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x0A94 - Reserved +**/ + UINT8 Reserved42[93]; + +/** Offset 0x0AF1 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0AF2 - Reserved +**/ + UINT8 Reserved43[318]; + +/** Offset 0x0C30 - RpPtmBytes +**/ + UINT8 RpPtmBytes[4]; + +/** Offset 0x0C34 - Reserved +**/ + UINT8 Reserved44[95]; + +/** Offset 0x0C93 - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0C94 - Reserved +**/ + UINT8 Reserved45; + +/** Offset 0x0C95 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x0C96 - Reserved +**/ + UINT8 Reserved46[24]; + +/** Offset 0x0CAE - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x0CAF - Reserved +**/ + UINT8 Reserved47[8]; + +/** Offset 0x0CB7 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + <b>10</b>, For all other SKUs the recommended default are <b>0</b> +**/ + UINT8 TccActivationOffset; + +/** Offset 0x0CB8 - Reserved +**/ + UINT8 Reserved48[34]; + +/** Offset 0x0CDA - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0CDB - Reserved +**/ + UINT8 Reserved49[196]; + +/** Offset 0x0D9F - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0DA1 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0DA2 - Reserved +**/ + UINT8 Reserved50[2]; + +/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[28]; + +/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; + +/** Offset 0x0E14 - Reserved +**/ + UINT8 Reserved51[313]; + +/** Offset 0x0F4D - LpmStateEnableMask +**/ + UINT8 LpmStateEnableMask; + +/** Offset 0x0F4E - Reserved +**/ + UINT8 Reserved52[122]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0FC8 +**/ + UINT8 UnusedUpdSpace43[6]; + +/** Offset 0x0FCE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h index 57194fab92..98a16d7752 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h @@ -1,68 +1,68 @@ -/** @file
- Header file for Firmware Version Information
-
- @copyright
- Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
- UINT8 Count; ///< Offset 28 Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
+/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h index e6fe83622a..ca86ade6db 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h @@ -1,48 +1,48 @@ -/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE 0x545F4450554C4845 /* 'EHLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4845 /* 'EHLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE 0x535F4450554C4845 /* 'EHLUPD_S' */
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C4845 /* 'EHLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4845 /* 'EHLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C4845 /* 'EHLUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h index c9fe5dbe0b..5b91afeea2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h @@ -1,3026 +1,3026 @@ -/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Platform Reserved Memory Size
- The minimum platform memory size required to pass control into DXE
-**/
- UINT64 PlatformMemorySize;
-
-/** Offset 0x0048 - SPD Data Length
- Length of SPD Data
- 0x100:256 Bytes, 0x200:512 Bytes
-**/
- UINT16 MemorySpdDataLen;
-
-/** Offset 0x004A - Enable above 4GB MMIO resource support
- Enable/disable above 4GB MMIO resource support
- $EN_DIS
-**/
- UINT8 EnableAbove4GBMmio;
-
-/** Offset 0x004B - Enable/Disable CrashLog Device 10
- Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
- $EN_DIS
-**/
- UINT8 CpuCrashLogDevice;
-
-/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr00;
-
-/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr01;
-
-/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr10;
-
-/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr11;
-
-/** Offset 0x005C - Dq Byte Map CH0
- Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqByteMapCh0[12];
-
-/** Offset 0x0068 - Dq Byte Map CH1
- Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqByteMapCh1[12];
-
-/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0
- Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh0[8];
-
-/** Offset 0x007C - Dqs Map CPU to DRAM CH 1
- Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh1[8];
-
-/** Offset 0x0084 - RcompResister settings
- Indicates RcompReister settings: Board-dependent
-**/
- UINT16 RcompResistor[3];
-
-/** Offset 0x008A - RcompTarget settings
- RcompTarget settings: board-dependent
-**/
- UINT16 RcompTarget[5];
-
-/** Offset 0x0094 - VREF_CA
- CA Vref routing: board-dependent
- 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
- 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
-**/
- UINT8 CaVrefConfig;
-
-/** Offset 0x0095 - Smram Mask
- The SMM Regions AB-SEG and/or H-SEG reserved
- 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
-**/
- UINT8 SmramMask;
-
-/** Offset 0x0096 - Dqs Pins Interleaved Setting
- Indicates DqPinsInterleaved setting: board-dependent
- $EN_DIS
-**/
- UINT8 DqPinsInterleaved;
-
-/** Offset 0x0097 - LPDDR4 Write DQ/DQS Retraining
- Enables/Disable LPDDR4 Write DQ/DQS Retraining
- $EN_DIS
-**/
- UINT8 Lp4DqsOscEn;
-
-/** Offset 0x0098 - Ibecc
- Enables/Disable Ibecc
- $EN_DIS
-**/
- UINT8 Ibecc;
-
-/** Offset 0x0099 - IbeccParity
- In-Band ECC Parity Control
- $EN_DIS
-**/
- UINT8 IbeccParity;
-
-/** Offset 0x009A - IbeccOperationMode
- In-Band ECC Operation Mode
- 0:Protect base on address range, 1: Non-protected, 2: All protected
-**/
- UINT8 IbeccOperationMode;
-
-/** Offset 0x009B - IbeccErrorInj Note: Modification accepts the disclaimer shown in the Help text
- Disclaimer: Warning: This must NOT be enabled for production!!! Enabling Error Injection
- allows attackers who have access to the Host Operating System to inject IBECC errors
- that can cause unintended memory corruption and enable the leak of security data
- in the BIOS stolen memory regions.
- $EN_DIS
-**/
- UINT8 IbeccErrorInj;
-
-/** Offset 0x009C - IbeccProtectedRegionEnable
- In-Band ECC Protected Region Enable
- $EN_DIS
-**/
- UINT8 IbeccProtectedRegionEnable[8];
-
-/** Offset 0x00A4 - IbeccProtectedRegionBases
- IBECC Protected Region Bases
-**/
- UINT16 IbeccProtectedRegionBase[8];
-
-/** Offset 0x00B4 - IbeccProtectedRegionMasks
- IBECC Protected Region Masks
-**/
- UINT16 IbeccProtectedRegionMask[8];
-
-/** Offset 0x00C4 - MrcTaskDebugPrintEnable
- Mrc Task Debug Print Enable. 0(Default)=Disable, non-Zero=Enable Task Debug print
-**/
- UINT8 MrcTaskDebugEnable;
-
-/** Offset 0x00C5 - Rank Margin Tool per Task
- This option enables the user to execute Rank Margin Tool per major training step
- in the MRC.
- $EN_DIS
-**/
- UINT8 RmtPerTask;
-
-/** Offset 0x00C6 - Training Trace
- This option enables the trained state tracing feature in MRC. This feature will
- print out the key training parameters state across major training steps.
- $EN_DIS
-**/
- UINT8 TrainTrace;
-
-/** Offset 0x00C7
-**/
- UINT8 UnusedUpdSpace0;
-
-/** Offset 0x00C8 - Intel Enhanced Debug
- Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
- 0 : Disable, 0x400000 : Enable
-**/
- UINT32 IedSize;
-
-/** Offset 0x00CC - Tseg Size
- Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
- 0x0400000:4MB, 0x01000000:16MB
-**/
- UINT32 TsegSize;
-
-/** Offset 0x00D0 - MMIO Size
- Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
-**/
- UINT16 MmioSize;
-
-/** Offset 0x00D2 - LowSupplyEnData
- Enable: Enable Low Supply for LPDDR4 Data, Disable(Default)
- $EN_DIS
-**/
- UINT8 LowSupplyEnData;
-
-/** Offset 0x00D3 - LowSupplyEnCcc
- Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default)
- $EN_DIS
-**/
- UINT8 LowSupplyEnCcc;
-
-/** Offset 0x00D4 - Memory Test on Warm Boot
- Run Base Memory Test on Warm Boot
- 0:Disable, 1:Enable
-**/
- UINT8 MemTestOnWarmBoot;
-
-/** Offset 0x00D5 - Probeless Trace
- Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
- This also requires IED to be enabled.
- $EN_DIS
-**/
- UINT8 ProbelessTrace;
-
-/** Offset 0x00D6 - Enable SMBus
- Enable/disable SMBus controller.
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x00D7 - Spd Address Tabl
- Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
- if SPD Address is 00
-**/
- UINT8 SpdAddressTable[4];
-
-/** Offset 0x00DB - Platform Debug Consent
- To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
- Enabling this BIOS option may alter the default value of other debug-related BIOS
- options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
- policies, but the user must set each debug option manually, aimed at advanced users.\n
- Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
- 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
-**/
- UINT8 PlatformDebugConsent;
-
-/** Offset 0x00DC - DCI Enable
- Determine if to enable DCI debug from host
- $EN_DIS
-**/
- UINT8 DciEn;
-
-/** Offset 0x00DD - DCI DbC Mode
- Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
- Set both USB2/3DBCEN; No Change: Comply with HW value
- 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
-**/
- UINT8 DciDbcMode;
-
-/** Offset 0x00DE - Enable DCI ModPHY Pwoer Gate
- Enable ModPHY Pwoer Gate when DCI is enabled
- $EN_DIS
-**/
- UINT8 DciModphyPg;
-
-/** Offset 0x00DF - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
- This BIOS option enables kernel and platform debug for USB3 interface over a UFP
- Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
- 0:Disabled, 1:Enabled, 2:No Change
-**/
- UINT8 DciUsb3TypecUfpDbg;
-
-/** Offset 0x00E0 - PCH Trace Hub Mode
- Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
- if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
- 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
-**/
- UINT8 PchTraceHubMode;
-
-/** Offset 0x00E1 - PCH Trace Hub Memory Region 0 buffer Size
- Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 PchTraceHubMemReg0Size;
-
-/** Offset 0x00E2 - PCH Trace Hub Memory Region 1 buffer Size
- Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 PchTraceHubMemReg1Size;
-
-/** Offset 0x00E3 - PchPreMemRsvd
- Reserved for PCH Pre-Mem Reserved
- $EN_DIS
-**/
- UINT8 PchPreMemRsvd[7];
-
-/** Offset 0x00EA - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1=Enable/Set
- $EN_DIS
-**/
- UINT8 X2ApicOptOut;
-
-/** Offset 0x00EB - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
- 0=Disable/Clear, 1=Enable/Set
- $EN_DIS
-**/
- UINT8 DmaControlGuarantee;
-
-/** Offset 0x00EC - Base addresses for VT-d function MMIO access
- Base addresses for VT-d MMIO access per VT-d engine
-**/
- UINT32 VtdBaseAddress[9];
-
-/** Offset 0x0110 - Disable VT-d
- 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
- $EN_DIS
-**/
- UINT8 VtdDisable;
-
-/** Offset 0x0111 - Vtd Programming for Igd
- 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar
- programming disabled)
- $EN_DIS
-**/
- UINT8 VtdIgdEnable;
-
-/** Offset 0x0112 - Vtd Programming for Ipu
- 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar
- programming disabled)
- $EN_DIS
-**/
- UINT8 VtdIpuEnable;
-
-/** Offset 0x0113 - Vtd Programming for Iop
- 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar
- programming disabled)
- $EN_DIS
-**/
- UINT8 VtdIopEnable;
-
-/** Offset 0x0114 - Vtd Programming for ITbt
- 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar
- programming disabled)
- $EN_DIS
-**/
- UINT8 VtdItbtEnable;
-
-/** Offset 0x0115 - Disable Te Igd
- 0=Enable/FALSE(Te Igd enabled), 1=Disable/TRUE (Te Igd disabled)
- $EN_DIS
-**/
- UINT8 DisableTeIgd;
-
-/** Offset 0x0116 - Internal Graphics Pre-allocated Memory
- Size of memory preallocated for internal graphics.
- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
- 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
- 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x0117 - Internal Graphics
- Enable/disable internal graphics.
- $EN_DIS
-**/
- UINT8 InternalGfx;
-
-/** Offset 0x0118 - Aperture Size
- Select the Aperture Size.
- 0:128 MB, 1:256 MB, 2:512 MB
-**/
- UINT8 ApertureSize;
-
-/** Offset 0x0119 - Board Type
- MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
- Halo, 7=UP Server
- 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
-**/
- UINT8 UserBd;
-
-/** Offset 0x011A - DDR Frequency Limit
- Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
- 2133, 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 DdrFreqLimit;
-
-/** Offset 0x011C - SA GV
- System Agent dynamic frequency support and when enabled memory will be training
- at three different frequencies.
- 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
-**/
- UINT8 SaGv;
-
-/** Offset 0x011D - DDR Speed Control
- DDR Frequency and Gear control for all SAGV points.
- 0:Auto, 1:Manual
-**/
- UINT8 DdrSpeedControl;
-
-/** Offset 0x011E - Low Frequency
- SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
- 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 FreqSaGvLow;
-
-/** Offset 0x0120 - Mid Frequency
- SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
- 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 FreqSaGvMid;
-
-/** Offset 0x0122 - Channel A DIMM Control
- Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmChannel0;
-
-/** Offset 0x0123 - Channel B DIMM Control
- Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmChannel1;
-
-/** Offset 0x0124 - Scrambler Support
- This option enables data scrambling in memory.
- $EN_DIS
-**/
- UINT8 ScramblerSupport;
-
-/** Offset 0x0125 - Ddr4OneDpc
- DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
- or on both (default)
- 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
-**/
- UINT8 Ddr4OneDpc;
-
-/** Offset 0x0126
-**/
- UINT8 UnusedUpdSpace1[2];
-
-/** Offset 0x0128 - MMA Test Content Pointer
- Pointer to MMA Test Content in Memory
-**/
- UINT32 MmaTestContentPtr;
-
-/** Offset 0x012C - MMA Test Content Size
- Size of MMA Test Content in Memory
-**/
- UINT32 MmaTestContentSize;
-
-/** Offset 0x0130 - MMA Test Config Pointer
- Pointer to MMA Test Config in Memory
-**/
- UINT32 MmaTestConfigPtr;
-
-/** Offset 0x0134 - MMA Test Config Size
- Size of MMA Test Config in Memory
-**/
- UINT32 MmaTestConfigSize;
-
-/** Offset 0x0138 - SPD Profile Selected
- Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
- Profile 1, 3=XMP Profile 2
- 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
-**/
- UINT8 SpdProfileSelected;
-
-/** Offset 0x0139
-**/
- UINT8 UnusedUpdSpace2;
-
-/** Offset 0x013A - Memory Voltage
- Memory Voltage Override (Vddq). Default = no override
- 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
- Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
-**/
- UINT16 VddVoltage;
-
-/** Offset 0x013C - Memory Reference Clock
- 100MHz, 133MHz.
- 0:133MHz, 1:100MHz
-**/
- UINT8 RefClk;
-
-/** Offset 0x013D - Memory Ratio
- Automatic or the frequency will equal ratio times reference clock. Set to Auto to
- recalculate memory timings listed below.
- 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
-**/
- UINT8 Ratio;
-
-/** Offset 0x013E - tCL
- CAS Latency, 0: AUTO, max: 31
-**/
- UINT8 tCL;
-
-/** Offset 0x013F - tCWL
- Min CAS Write Latency Delay Time, 0: AUTO, max: 34
-**/
- UINT8 tCWL;
-
-/** Offset 0x0140 - tFAW
- Min Four Activate Window Delay Time, 0: AUTO, max: 63
-**/
- UINT16 tFAW;
-
-/** Offset 0x0142 - tRAS
- RAS Active Time, 0: AUTO, max: 64
-**/
- UINT16 tRAS;
-
-/** Offset 0x0144 - tRCD/tRP
- RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
-**/
- UINT8 tRCDtRP;
-
-/** Offset 0x0145
-**/
- UINT8 UnusedUpdSpace3;
-
-/** Offset 0x0146 - tREFI
- Refresh Interval, 0: AUTO, max: 65535
-**/
- UINT16 tREFI;
-
-/** Offset 0x0148 - tRFC
- Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
-**/
- UINT16 tRFC;
-
-/** Offset 0x014A - tRRD
- Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
-**/
- UINT8 tRRD;
-
-/** Offset 0x014B - tRTP
- Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
- values: 5, 6, 7, 8, 9, 10, 12
-**/
- UINT8 tRTP;
-
-/** Offset 0x014C - tWR
- Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
- 20, 24, 30, 34, 40
- 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
- 34:34, 40:40
-**/
- UINT8 tWR;
-
-/** Offset 0x014D - tWTR
- Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
-**/
- UINT8 tWTR;
-
-/** Offset 0x014E - NMode
- System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
-**/
- UINT8 NModeSupport;
-
-/** Offset 0x014F - DllBwEn[0]
- DllBwEn[0], for 1067 (0..7)
-**/
- UINT8 DllBwEn0;
-
-/** Offset 0x0150 - DllBwEn[1]
- DllBwEn[1], for 1333 (0..7)
-**/
- UINT8 DllBwEn1;
-
-/** Offset 0x0151 - DllBwEn[2]
- DllBwEn[2], for 1600 (0..7)
-**/
- UINT8 DllBwEn2;
-
-/** Offset 0x0152 - DllBwEn[3]
- DllBwEn[3], for 1867 and up (0..7)
-**/
- UINT8 DllBwEn3;
-
-/** Offset 0x0153 - ISVT IO Port Address
- ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
-**/
- UINT8 IsvtIoPort;
-
-/** Offset 0x0154 - Enable Intel HD Audio (Azalia)
- 0: Disable, 1: Enable (Default) Azalia controller
- $EN_DIS
-**/
- UINT8 PchHdaEnable;
-
-/** Offset 0x0155 - Enable PSE Controller
- 0: Disable; 1: Enable (Default) PSE controller
- $EN_DIS
-**/
- UINT8 PchPseEnable;
-
-/** Offset 0x0156 - CPU Trace Hub Mode
- Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
- if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
- 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
-**/
- UINT8 CpuTraceHubMode;
-
-/** Offset 0x0157 - CPU Trace Hub Memory Region 0
- CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 CpuTraceHubMemReg0Size;
-
-/** Offset 0x0158 - CPU Trace Hub Memory Region 1
- CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 CpuTraceHubMemReg1Size;
-
-/** Offset 0x0159 - SA GV Low Gear
- Gear Selection for SAGV Low point
- 0:Gear1, 1:Gear2
-**/
- UINT8 SaGvLowGear2;
-
-/** Offset 0x015A - SA GV Mid Gear
- Gear Selection for SAGV Mid point
- 0:Gear1, 1:Gear2
-**/
- UINT8 SaGvMidGear2;
-
-/** Offset 0x015B - SA GV High Gear
- Gear Selection for SAGV High point, or when SAGV is disabled
- 0:Gear1, 1:Gear2
-**/
- UINT8 SaGvHighGear2;
-
-/** Offset 0x015C - HECI Timeouts
- 0: Disable, 1: Enable (Default) timeout check for HECI
- $EN_DIS
-**/
- UINT8 HeciTimeouts;
-
-/** Offset 0x015D
-**/
- UINT8 UnusedUpdSpace4[3];
-
-/** Offset 0x0160 - HECI1 BAR address
- BAR address of HECI1
-**/
- UINT32 Heci1BarAddress;
-
-/** Offset 0x0164 - HECI2 BAR address
- BAR address of HECI2
-**/
- UINT32 Heci2BarAddress;
-
-/** Offset 0x0168 - HECI3 BAR address
- BAR address of HECI3
-**/
- UINT32 Heci3BarAddress;
-
-/** Offset 0x016C - HG dGPU Power Delay
- HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
- 300=300 microseconds
-**/
- UINT16 HgDelayAfterPwrEn;
-
-/** Offset 0x016E - HG dGPU Reset Delay
- HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
- microseconds
-**/
- UINT16 HgDelayAfterHoldReset;
-
-/** Offset 0x0170 - MMIO size adjustment for AUTO mode
- Positive number means increasing MMIO size, Negative value means decreasing MMIO
- size: 0 (Default)=no change to AUTO mode MMIO size
-**/
- UINT16 MmioSizeAdjustment;
-
-/** Offset 0x0172 - PCIe ASPM programming will happen in relation to the Oprom
- Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
- Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
- Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
- 0:Before, 1:After
-**/
- UINT8 InitPcieAspmAfterOprom;
-
-/** Offset 0x0173 - Selection of the primary display device
- 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics
- 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics
-**/
- UINT8 PrimaryDisplay;
-
-/** Offset 0x0174 - Selection of PSMI Region size
- 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
- 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
-**/
- UINT8 PsmiRegionSize;
-
-/** Offset 0x0175
-**/
- UINT8 UnusedUpdSpace5[3];
-
-/** Offset 0x0178 - Temporary MMIO address for GMADR
- The reference code will use this as Temporary MMIO address space to access GMADR
- Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
- (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
- - 0x1) (Where ApertureSize = 256MB)
-**/
- UINT32 GmAdr;
-
-/** Offset 0x017C - Temporary MMIO address for GTTMMADR
- The reference code will use this as Temporary MMIO address space to access GTTMMADR
- Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
- to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
- + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
-**/
- UINT32 GttMmAdr;
-
-/** Offset 0x0180 - Selection of iGFX GTT Memory size
- 1=2MB, 2=4MB, 3=8MB, Default is 3
- 1:2MB, 2:4MB, 3:8MB
-**/
- UINT16 GttSize;
-
-/** Offset 0x0182 - Hybrid Graphics GPIO information for PEG 0
- Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
-**/
- UINT8 CpuPcie0Rtd3Gpio[24];
-
-/** Offset 0x019A - Enable/Disable MRC TXT dependency
- When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
- MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
- $EN_DIS
-**/
- UINT8 TxtImplemented;
-
-/** Offset 0x019B - Enable/Disable SA OcSupport
- Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
- $EN_DIS
-**/
- UINT8 SaOcSupport;
-
-/** Offset 0x019C - GT slice Voltage Mode
- 0(Default): Adaptive, 1: Override
- 0: Adaptive, 1: Override
-**/
- UINT8 GtVoltageMode;
-
-/** Offset 0x019D - Maximum GTs turbo ratio override
- 0(Default)=Minimal/Auto, 60=Maximum
-**/
- UINT8 GtMaxOcRatio;
-
-/** Offset 0x019E - The voltage offset applied to GT slice
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 GtVoltageOffset;
-
-/** Offset 0x01A0 - The GT slice voltage override which is applied to the entire range of GT frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtVoltageOverride;
-
-/** Offset 0x01A2 - adaptive voltage applied during turbo frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtExtraTurboVoltage;
-
-/** Offset 0x01A4 - voltage offset applied to the SA
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 SaVoltageOffset;
-
-/** Offset 0x01A6 - PCIe root port Function number for Hybrid Graphics dGPU
- Root port Index number to indicate which PCIe root port has dGPU
-**/
- UINT8 RootPortIndex;
-
-/** Offset 0x01A7 - Realtime Memory Timing
- 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
- realtime memory timing changes after MRC_DONE.
- 0: Disabled, 1: Enabled
-**/
- UINT8 RealtimeMemoryTiming;
-
-/** Offset 0x01A8 - This is policy to control iTBT PCIe Multiple Segment setting.
- When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
- TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieMultipleSegmentEnabled;
-
-/** Offset 0x01A9 - Enable/Disable SA IPU
- Enable(Default): Enable SA IPU, Disable: Disable SA IPU
- $EN_DIS
-**/
- UINT8 SaIpuEnable;
-
-/** Offset 0x01AA - IPU IMR Configuration
- 0:IPU Camera, 1:IPU Gen Default is 0
- 0:IPU Camera, 1:IPU Gen
-**/
- UINT8 SaIpuImrConfiguration;
-
-/** Offset 0x01AB - IMGU CLKOUT Configuration
- The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 ImguClkOutEn[5];
-
-/** Offset 0x01B0 - IPU FUSA Configuration
- 0:FUSA Disable, 1:FUSA Enable Default is 0
- 0:FUSA Disable, 1:FUSA Enable
-**/
- UINT8 SaIpuFusaConfigEnable;
-
-/** Offset 0x01B1
-**/
- UINT8 UnusedUpdSpace6[3];
-
-/** Offset 0x01B4 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 CpuPcieRpEnableMask;
-
-/** Offset 0x01B8 - Assertion on Link Down GPIOs
- GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
- GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
- 0:Disable, 1:Enable
-**/
- UINT8 CpuPcieRpLinkDownGpios;
-
-/** Offset 0x01B9 - Enable ClockReq Messaging
- ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default):
- Enable ClockReq Messaging
- 0:Disable, 1:Enable
-**/
- UINT8 CpuPcieRpClockReqMsgEnable;
-
-/** Offset 0x01BA - PCIE RP Pcie Speed
- Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
- 4: Gen4 (see: CPU_PCIE_SPEED).
-**/
- UINT8 CpuPcieRpPcieSpeed[4];
-
-/** Offset 0x01BE - Selection of PSMI Support On/Off
- 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
- $EN_DIS
-**/
- UINT8 GtPsmiSupport;
-
-/** Offset 0x01BF - Selection of DiSM Region Size
- DiSM Size to be allocated for 2LM Sku Default is 0
- 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB
-**/
- UINT8 DismSize;
-
-/** Offset 0x01C0 - Pram Size
- Persisted Ram Size. Default is Disabled
- 0x30:Disable, 0x31:4MB, 0x32:16MB, 0x33:64MB
-**/
- UINT8 PramSize;
-
-/** Offset 0x01C1 - SaPreMemProductionRsvd
- Reserved for SA Pre-Mem Production
- $EN_DIS
-**/
- UINT8 SaPreMemProductionRsvd[138];
-
-/** Offset 0x024B - DMI Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 DmiMaxLinkSpeed;
-
-/** Offset 0x024C - DMI Equalization Phase 2
- DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
- AUTO - Use the current default method
- 0:Disable phase2, 1:Enable phase2, 2:Auto
-**/
- UINT8 DmiGen3EqPh2Enable;
-
-/** Offset 0x024D - DMI Gen3 Equalization Phase3
- DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 DmiGen3EqPh3Method;
-
-/** Offset 0x024E - Enable/Disable DMI GEN3 Static EQ Phase1 programming
- Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
- Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 DmiGen3ProgramStaticEq;
-
-/** Offset 0x024F - DeEmphasis control for DMI
- DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
- 0: -6dB, 1: -3.5dB
-**/
- UINT8 DmiDeEmphasis;
-
-/** Offset 0x0250 - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 DmiGen3RootPortPreset[8];
-
-/** Offset 0x0258 - DMI Gen3 End port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
-**/
- UINT8 DmiGen3EndPointPreset[8];
-
-/** Offset 0x0260 - DMI Gen3 End port Hint values per lane
- Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 DmiGen3EndPointHint[8];
-
-/** Offset 0x0268 - DMI Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
-**/
- UINT8 DmiGen3RxCtlePeaking[4];
-
-/** Offset 0x026C - BIST on Reset
- Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 BistOnReset;
-
-/** Offset 0x026D - Skip Stop PBET Timer Enable/Disable
- Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 SkipStopPbet;
-
-/** Offset 0x026E - Over clocking support
- Over clocking support; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 OcSupport;
-
-/** Offset 0x026F - Over clocking Lock
- Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 OcLock;
-
-/** Offset 0x0270 - Maximum Core Turbo Ratio Override
- Maximum core turbo ratio override allows to increase CPU core frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
-**/
- UINT8 CoreMaxOcRatio;
-
-/** Offset 0x0271 - Core voltage mode
- Core voltage mode; <b>0: Adaptive</b>; 1: Override.
- $EN_DIS
-**/
- UINT8 CoreVoltageMode;
-
-/** Offset 0x0272 - Maximum clr turbo ratio override
- Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
-**/
- UINT8 RingMaxOcRatio;
-
-/** Offset 0x0273 - Hyper Threading Enable/Disable
- Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 HyperThreading;
-
-/** Offset 0x0274 - Enable or Disable CPU Ratio Override
- Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 CpuRatioOverride;
-
-/** Offset 0x0275 - CPU ratio value
- CPU ratio value. Valid Range 0 to 63
-**/
- UINT8 CpuRatio;
-
-/** Offset 0x0276 - Boot frequency
- Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
- <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
- is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
- 0:0, 1:1, 2:2
-**/
- UINT8 BootFrequency;
-
-/** Offset 0x0277 - Number of active cores
- Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
- 2 </b>;<b>3: 3 </b>
- 0:All, 1:1, 2:2, 3:3
-**/
- UINT8 ActiveCoreCount;
-
-/** Offset 0x0278 - Processor Early Power On Configuration FCLK setting
- <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
- 2: 400 MHz. - 3: Reserved
- 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
-**/
- UINT8 FClkFrequency;
-
-/** Offset 0x0279 - Set JTAG power in C10 and deeper power states
- False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
- and deeper power states for debug purpose. <b>0: False</b>; 1: True.
- 0: False, 1: True
-**/
- UINT8 JtagC10PowerGateDisable;
-
-/** Offset 0x027A - Enable or Disable VMX
- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x027B - AVX2 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx2RatioOffset;
-
-/** Offset 0x027C - AVX3 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx3RatioOffset;
-
-/** Offset 0x027D - BCLK Adaptive Voltage Enable
- When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
- Disable;<b> 1: Enable
- $EN_DIS
-**/
- UINT8 BclkAdaptiveVoltage;
-
-/** Offset 0x027E - core voltage override
- The core voltage override which is applied to the entire range of cpu core frequencies.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageOverride;
-
-/** Offset 0x0280 - Core Turbo voltage Adaptive
- Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageAdaptive;
-
-/** Offset 0x0282 - Core Turbo voltage Offset
- The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
-**/
- UINT16 CoreVoltageOffset;
-
-/** Offset 0x0284 - Core PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 CorePllVoltageOffset;
-
-/** Offset 0x0285 - Ring Downbin
- Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
- lower than the core ratio.0: Disable; <b>1: Enable.</b>
- $EN_DIS
-**/
- UINT8 RingDownBin;
-
-/** Offset 0x0286 - Ring voltage mode
- Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
- $EN_DIS
-**/
- UINT8 RingVoltageMode;
-
-/** Offset 0x0287 - TjMax Offset
- TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
- TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
-**/
- UINT8 TjMaxOffset;
-
-/** Offset 0x0288 - Ring voltage override
- The ring voltage override which is applied to the entire range of cpu ring frequencies.
- Valid Range 0 to 2000
-**/
- UINT16 RingVoltageOverride;
-
-/** Offset 0x028A - Ring Turbo voltage Adaptive
- Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
- Valid Range 0 to 2000
-**/
- UINT16 RingVoltageAdaptive;
-
-/** Offset 0x028C - Ring Turbo voltage Offset
- The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
-**/
- UINT16 RingVoltageOffset;
-
-/** Offset 0x028E
-**/
- UINT8 UnusedUpdSpace7[2];
-
-/** Offset 0x0290 - ElixirSpringsPatchAddr
- Address of Elixir Springs Patches
-**/
- UINT32 ElixirSpringsPatchAddr;
-
-/** Offset 0x0294 - ElixirSpringsPatchSize
- Size of Elixir Springs Patches
-**/
- UINT32 ElixirSpringsPatchSize;
-
-/** Offset 0x0298 - CPU Run Control
- Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
- No Change</b>
- 0:Disabled, 1:Enabled, 2:No Change
-**/
- UINT8 DebugInterfaceEnable;
-
-/** Offset 0x0299 - CPU Run Control Lock
- Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DebugInterfaceLockEnable;
-
-/** Offset 0x029A - BiosGuard
- Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
- $EN_DIS
-**/
- UINT8 BiosGuard;
-
-/** Offset 0x029B
-**/
- UINT8 BiosGuardToolsInterface;
-
-/** Offset 0x029C - EnableSgx
- Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
- 0: Disable, 1: Enable, 2: Software Control
-**/
- UINT8 EnableSgx;
-
-/** Offset 0x029D - Txt
- Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
- $EN_DIS
-**/
- UINT8 Txt;
-
-/** Offset 0x029E
-**/
- UINT8 UnusedUpdSpace8[2];
-
-/** Offset 0x02A0 - PrmrrSize
- Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
-**/
- UINT32 PrmrrSize;
-
-/** Offset 0x02A4 - SinitMemorySize
- Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
-**/
- UINT32 SinitMemorySize;
-
-/** Offset 0x02A8 - TxtDprMemoryBase
- Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
-**/
- UINT64 TxtDprMemoryBase;
-
-/** Offset 0x02B0 - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x02B4 - TxtDprMemorySize
- Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
-**/
- UINT32 TxtDprMemorySize;
-
-/** Offset 0x02B8 - BiosAcmBase
- Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
-**/
- UINT32 BiosAcmBase;
-
-/** Offset 0x02BC - BiosAcmSize
- Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
-**/
- UINT32 BiosAcmSize;
-
-/** Offset 0x02C0 - ApStartupBase
- Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
-**/
- UINT32 ApStartupBase;
-
-/** Offset 0x02C4 - TgaSize
- Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
-**/
- UINT32 TgaSize;
-
-/** Offset 0x02C8 - TxtLcpPdBase
- Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
-**/
- UINT64 TxtLcpPdBase;
-
-/** Offset 0x02D0 - TxtLcpPdSize
- Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
-**/
- UINT64 TxtLcpPdSize;
-
-/** Offset 0x02D8 - IsTPMPresence
- IsTPMPresence default values
-**/
- UINT8 IsTPMPresence;
-
-/** Offset 0x02D9 - ReservedSecurityPreMem
- Reserved for Security Pre-Mem
- $EN_DIS
-**/
- UINT8 ReservedSecurityPreMem[6];
-
-/** Offset 0x02DF - PCH Master Clock Gating Control
- Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default
- $EN_DIS
-**/
- UINT8 PchMasterClockGating;
-
-/** Offset 0x02E0 - PCH Master Power Gating Control
- Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default
- $EN_DIS
-**/
- UINT8 PchMasterPowerGating;
-
-/** Offset 0x02E1
-**/
- UINT8 UnusedUpdSpace9;
-
-/** Offset 0x02E2 - FIA Lane Reversal Enable/Disable config mask
- Enable/Disable. 0: Disable, 1: enable, Enable or disable Lane Reversal. If Enabled,
- the x2 FIA Lane will be flipped
-**/
- UINT16 FiaLaneReversalEnable;
-
-/** Offset 0x02E4 - Enable PCH HSIO PCIE Rx Set Ctle
- Enable PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtleEnable[24];
-
-/** Offset 0x02FC - PCH HSIO PCIE Rx Set Ctle Value
- PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtle[24];
-
-/** Offset 0x0314 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
-
-/** Offset 0x032C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
-
-/** Offset 0x0344 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
-
-/** Offset 0x035C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
-
-/** Offset 0x0374 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
-
-/** Offset 0x038C - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
-
-/** Offset 0x03A4 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
-
-/** Offset 0x03BC - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
- PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen1DeEmph[24];
-
-/** Offset 0x03D4 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
-
-/** Offset 0x03EC - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
-
-/** Offset 0x0404 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
-
-/** Offset 0x041C - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
-
-/** Offset 0x0434 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-
-/** Offset 0x043C - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMag[8];
-
-/** Offset 0x0444 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-
-/** Offset 0x044C - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMag[8];
-
-/** Offset 0x0454 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-
-/** Offset 0x045C - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMag[8];
-
-/** Offset 0x0464 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-
-/** Offset 0x046C - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-
-/** Offset 0x0474 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-
-/** Offset 0x047C - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-
-/** Offset 0x0484 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-
-/** Offset 0x048C - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-
-/** Offset 0x0494 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-
-/** Offset 0x049C - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen1DeEmph[8];
-
-/** Offset 0x04A4 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-
-/** Offset 0x04AC - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen2DeEmph[8];
-
-/** Offset 0x04B4 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-
-/** Offset 0x04BC - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen3DeEmph[8];
-
-/** Offset 0x04C4 - PCH LPC Enhance the port 8xh decoding
- Original LPC only decodes one byte of port 80h.
- $EN_DIS
-**/
- UINT8 PchLpcEnhancePort8xhDecoding;
-
-/** Offset 0x04C5 - PCH Port80 Route
- Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
- $EN_DIS
-**/
- UINT8 PchPort80Route;
-
-/** Offset 0x04C6 - Enable SMBus ARP support
- Enable SMBus ARP support.
- $EN_DIS
-**/
- UINT8 SmbusArpEnable;
-
-/** Offset 0x04C7 - Number of RsvdSmbusAddressTable.
- The number of elements in the RsvdSmbusAddressTable.
-**/
- UINT8 PchNumRsvdSmbusAddresses;
-
-/** Offset 0x04C8 - SMBUS Base Address
- SMBUS Base Address (IO space).
-**/
- UINT16 PchSmbusIoBase;
-
-/** Offset 0x04CA - Enable SMBus Alert Pin
- Enable SMBus Alert Pin.
- $EN_DIS
-**/
- UINT8 PchSmbAlertEnable;
-
-/** Offset 0x04CB - Usage type for ClkSrc
- 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
- (free running), 0xFF: not used
-**/
- UINT8 PcieClkSrcUsage[16];
-
-/** Offset 0x04DB - ClkReq-to-ClkSrc mapping
- Number of ClkReq signal assigned to ClkSrc
-**/
- UINT8 PcieClkSrcClkReq[16];
-
-/** Offset 0x04EB
-**/
- UINT8 UnusedUpdSpace10;
-
-/** Offset 0x04EC - Point of RsvdSmbusAddressTable
- Array of addresses reserved for non-ARP-capable SMBus devices.
-**/
- UINT32 RsvdSmbusAddressTablePtr;
-
-/** Offset 0x04F0 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpEnableMask;
-
-/** Offset 0x04F4 - Debug Interfaces
- Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
- BIT2 - Not used.
-**/
- UINT8 PcdDebugInterfaceFlags;
-
-/** Offset 0x04F5 - Serial Io Uart Debug Controller Number
- Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
- Core interface, it cannot be used for debug purpose.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 SerialIoUartDebugControllerNumber;
-
-/** Offset 0x04F6 - Serial Io Uart Debug Auto Flow
- Enables UART hardware flow control, CTS and RTS lines.
- $EN_DIS
-**/
- UINT8 SerialIoUartDebugAutoFlow;
-
-/** Offset 0x04F7
-**/
- UINT8 UnusedUpdSpace11;
-
-/** Offset 0x04F8 - Serial Io Uart Debug BaudRate
- Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
- 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
-**/
- UINT32 SerialIoUartDebugBaudRate;
-
-/** Offset 0x04FC - Serial Io Uart Debug Parity
- Set default Parity.
- 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
- UINT8 SerialIoUartDebugParity;
-
-/** Offset 0x04FD - Serial Io Uart Debug Stop Bits
- Set default stop bits.
- 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
- UINT8 SerialIoUartDebugStopBits;
-
-/** Offset 0x04FE - Serial Io Uart Debug Data Bits
- Set default word length. 0: Default, 5,6,7,8
- 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
-**/
- UINT8 SerialIoUartDebugDataBits;
-
-/** Offset 0x04FF
-**/
- UINT8 UnusedUpdSpace12;
-
-/** Offset 0x0500 - Serial Io Uart Debug Mmio Base
- Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
- = SerialIoUartPci.
-**/
- UINT32 SerialIoUartDebugMmioBase;
-
-/** Offset 0x0504 - ISA Serial Base selection
- Select ISA Serial Base address. Default is 0x3F8.
- 0:0x3F8, 1:0x2F8
-**/
- UINT8 PcdIsaSerialUartBase;
-
-/** Offset 0x0505 - GT PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 GtPllVoltageOffset;
-
-/** Offset 0x0506 - Ring PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 RingPllVoltageOffset;
-
-/** Offset 0x0507 - System Agent PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 SaPllVoltageOffset;
-
-/** Offset 0x0508 - Memory Controller PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 McPllVoltageOffset;
-
-/** Offset 0x0509 - MRC Safe Config
- Enables/Disable MRC Safe Config
- $EN_DIS
-**/
- UINT8 MrcSafeConfig;
-
-/** Offset 0x050A - TCSS Thunderbolt PCIE Root Port 0 Enable
- Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie0En;
-
-/** Offset 0x050B - TCSS Thunderbolt PCIE Root Port 1 Enable
- Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie1En;
-
-/** Offset 0x050C - TCSS Thunderbolt PCIE Root Port 2 Enable
- Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie2En;
-
-/** Offset 0x050D - TCSS Thunderbolt PCIE Root Port 3 Enable
- Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie3En;
-
-/** Offset 0x050E - TCSS USB HOST (xHCI) Enable
- Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
- $EN_DIS
-**/
- UINT8 TcssXhciEn;
-
-/** Offset 0x050F - TCSS USB DEVICE (xDCI) Enable
- Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
- $EN_DIS
-**/
- UINT8 TcssXdciEn;
-
-/** Offset 0x0510 - TCSS DMA0 Enable
- Set TCSS DMA0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma0En;
-
-/** Offset 0x0511 - TCSS DMA1 Enable
- Set TCSS DMA1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma1En;
-
-/** Offset 0x0512 - PcdSerialDebugBaudRate
- Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
- 3:9600, 4:19200, 6:56700, 7:115200
-**/
- UINT8 PcdSerialDebugBaudRate;
-
-/** Offset 0x0513 - HobBufferSize
- Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
- total HOB size).
- 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
-**/
- UINT8 HobBufferSize;
-
-/** Offset 0x0514 - Early Command Training
- Enables/Disable Early Command Training
- $EN_DIS
-**/
- UINT8 ECT;
-
-/** Offset 0x0515 - SenseAmp Offset Training
- Enables/Disable SenseAmp Offset Training
- $EN_DIS
-**/
- UINT8 SOT;
-
-/** Offset 0x0516 - Early ReadMPR Timing Centering 2D
- Enables/Disable Early ReadMPR Timing Centering 2D
- $EN_DIS
-**/
- UINT8 ERDMPRTC2D;
-
-/** Offset 0x0517 - Read MPR Training
- Enables/Disable Read MPR Training
- $EN_DIS
-**/
- UINT8 RDMPRT;
-
-/** Offset 0x0518 - Receive Enable Training
- Enables/Disable Receive Enable Training
- $EN_DIS
-**/
- UINT8 RCVET;
-
-/** Offset 0x0519 - Jedec Write Leveling
- Enables/Disable Jedec Write Leveling
- $EN_DIS
-**/
- UINT8 JWRL;
-
-/** Offset 0x051A - Early Write Time Centering 2D
- Enables/Disable Early Write Time Centering 2D
- $EN_DIS
-**/
- UINT8 EWRTC2D;
-
-/** Offset 0x051B - Early Read Time Centering 2D
- Enables/Disable Early Read Time Centering 2D
- $EN_DIS
-**/
- UINT8 ERDTC2D;
-
-/** Offset 0x051C - Write Timing Centering 1D
- Enables/Disable Write Timing Centering 1D
- $EN_DIS
-**/
- UINT8 WRTC1D;
-
-/** Offset 0x051D - Write Voltage Centering 1D
- Enables/Disable Write Voltage Centering 1D
- $EN_DIS
-**/
- UINT8 WRVC1D;
-
-/** Offset 0x051E - Read Timing Centering 1D
- Enables/Disable Read Timing Centering 1D
- $EN_DIS
-**/
- UINT8 RDTC1D;
-
-/** Offset 0x051F - Dimm ODT Training
- Enables/Disable Dimm ODT Training
- $EN_DIS
-**/
- UINT8 DIMMODTT;
-
-/** Offset 0x0520 - DIMM RON Training
- Enables/Disable DIMM RON Training
- $EN_DIS
-**/
- UINT8 DIMMRONT;
-
-/** Offset 0x0521 - Write Drive Strength/Equalization 2D
- Enables/Disable Write Drive Strength/Equalization 2D
- $EN_DIS
-**/
- UINT8 WRDSEQT;
-
-/** Offset 0x0522 - Write Slew Rate Training
- Enables/Disable Write Slew Rate Training
- $EN_DIS
-**/
- UINT8 WRSRT;
-
-/** Offset 0x0523 - Read ODT Training
- Enables/Disable Read ODT Training
- $EN_DIS
-**/
- UINT8 RDODTT;
-
-/** Offset 0x0524 - Read Equalization Training
- Enables/Disable Read Equalization Training
- $EN_DIS
-**/
- UINT8 RDEQT;
-
-/** Offset 0x0525 - Read Amplifier Training
- Enables/Disable Read Amplifier Training
- $EN_DIS
-**/
- UINT8 RDAPT;
-
-/** Offset 0x0526 - Write Timing Centering 2D
- Enables/Disable Write Timing Centering 2D
- $EN_DIS
-**/
- UINT8 WRTC2D;
-
-/** Offset 0x0527 - Read Timing Centering 2D
- Enables/Disable Read Timing Centering 2D
- $EN_DIS
-**/
- UINT8 RDTC2D;
-
-/** Offset 0x0528 - Write Voltage Centering 2D
- Enables/Disable Write Voltage Centering 2D
- $EN_DIS
-**/
- UINT8 WRVC2D;
-
-/** Offset 0x0529 - Read Voltage Centering 2D
- Enables/Disable Read Voltage Centering 2D
- $EN_DIS
-**/
- UINT8 RDVC2D;
-
-/** Offset 0x052A - Command Voltage Centering
- Enables/Disable Command Voltage Centering
- $EN_DIS
-**/
- UINT8 CMDVC;
-
-/** Offset 0x052B - Late Command Training
- Enables/Disable Late Command Training
- $EN_DIS
-**/
- UINT8 LCT;
-
-/** Offset 0x052C - Round Trip Latency Training
- Enables/Disable Round Trip Latency Training
- $EN_DIS
-**/
- UINT8 RTL;
-
-/** Offset 0x052D - Turn Around Timing Training
- Enables/Disable Turn Around Timing Training
- $EN_DIS
-**/
- UINT8 TAT;
-
-/** Offset 0x052E - Receive Enable Centering 1D
- Enables/Disable Receive Enable Centering 1D
- $EN_DIS
-**/
- UINT8 RCVENC1D;
-
-/** Offset 0x052F - Rank Margin Tool
- Enable/disable Rank Margin Tool.
- $EN_DIS
-**/
- UINT8 RMT;
-
-/** Offset 0x0530 - Margin Limit Check
- Margin Limit Check. Choose level of margin check
- 0:Disable, 1:L1, 2:L2, 3:Both
-**/
- UINT8 MarginLimitCheck;
-
-/** Offset 0x0531
-**/
- UINT8 UnusedUpdSpace13;
-
-/** Offset 0x0532 - Margin Limit L2
- % of L1 check for margin limit check
-**/
- UINT16 MarginLimitL2;
-
-/** Offset 0x0534 - Memory Test
- Enables/Disable Memory Test
- $EN_DIS
-**/
- UINT8 MEMTST;
-
-/** Offset 0x0535 - DIMM SPD Alias Test
- Enables/Disable DIMM SPD Alias Test
- $EN_DIS
-**/
- UINT8 ALIASCHK;
-
-/** Offset 0x0536 - Retrain Margin Check
- Enables/Disable Retrain Margin Check
- $EN_DIS
-**/
- UINT8 RMC;
-
-/** Offset 0x0537 - Write Drive Strength Up/Dn independently
- Enables/Disable Write Drive Strength Up/Dn independently
- $EN_DIS
-**/
- UINT8 WRDSUDT;
-
-/** Offset 0x0538 - Command Slew Rate Training
- Enables/Disable Command Slew Rate Training
- $EN_DIS
-**/
- UINT8 CMDSR;
-
-/** Offset 0x0539 - Command Drive Strength and Equalization 2D
- Enables/Disable Command Drive Strength and Equalization 2D
- $EN_DIS
-**/
- UINT8 CMDDSEQ;
-
-/** Offset 0x053A - Command Normalization
- Enables/Disable Command Normalization
- $EN_DIS
-**/
- UINT8 CMDNORM;
-
-/** Offset 0x053B - Early DQ Write Drive Strength and Equalization Training
- Enables/Disable Early DQ Write Drive Strength and Equalization Training
- $EN_DIS
-**/
- UINT8 EWRDSEQ;
-
-/** Offset 0x053C - Read Voltage Centering
- Enables/Disable Read Voltage Centering
- $EN_DIS
-**/
- UINT8 RDVC1D;
-
-/** Offset 0x053D - Write TCO Comp Training
- Enables/Disable Write TCO Comp Training
- $EN_DIS
-**/
- UINT8 TXTCO;
-
-/** Offset 0x053E - Clock TCO Comp Training
- Enables/Disable Clock TCO Comp Training
- $EN_DIS
-**/
- UINT8 CLKTCO;
-
-/** Offset 0x053F - Dimm ODT CA Training
- Enables/Disable Dimm ODT CA Training
- $EN_DIS
-**/
- UINT8 DIMMODTCA;
-
-/** Offset 0x0540 - Write TCO Dqs Training
- Enables/Disable Write TCO Dqs Training
- $EN_DIS
-**/
- UINT8 TXTCODQS;
-
-/** Offset 0x0541 - Duty Cycle Correction
- Enables/Disable Duty Cycle Correction
- $EN_DIS
-**/
- UINT8 DCC;
-
-/** Offset 0x0542 - DQ DFE Training
- Enable/Disable DQ DFE Training
- $EN_DIS
-**/
- UINT8 DQDFE;
-
-/** Offset 0x0543 - Sense Amplifier Correction Training
- Enable/Disable Sense Amplifier Correction Training
- $EN_DIS
-**/
- UINT8 SOTC;
-
-/** Offset 0x0544 - ECC Support
- Enables/Disable ECC Support
- $EN_DIS
-**/
- UINT8 EccSupport;
-
-/** Offset 0x0545 - Memory Remap
- Enables/Disable Memory Remap
- $EN_DIS
-**/
- UINT8 RemapEnable;
-
-/** Offset 0x0546 - MRC Time Measure
- Enable/Disable MRC Time Measure
- $EN_DIS
-**/
- UINT8 MrcTimeMeasure;
-
-/** Offset 0x0547 - MRC Fast Boot
- Enable/Disable MRC Fast flow
- $EN_DIS
-**/
- UINT8 MrcFastBoot;
-
-/** Offset 0x0548 - MRC Force Training on Warm
- Enables/Disable the MRC training on warm boot
- $EN_DIS
-**/
- UINT8 MrcTrainOnWarm;
-
-/** Offset 0x0549 - Rank Interleave support
- Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
- the same time.
- $EN_DIS
-**/
- UINT8 RankInterleave;
-
-/** Offset 0x054A - Enhanced Interleave support
- Enables/Disable Enhanced Interleave support
- $EN_DIS
-**/
- UINT8 EnhancedInterleave;
-
-/** Offset 0x054B - Memory Trace
- Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
- equal size. This option may change TOLUD and REMAP values as needed.
- $EN_DIS
-**/
- UINT8 MemoryTrace;
-
-/** Offset 0x054C - Ch Hash Support
- Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
- $EN_DIS
-**/
- UINT8 ChHashEnable;
-
-/** Offset 0x054D - Extern Therm Status
- Enables/Disable Extern Therm Status
- $EN_DIS
-**/
- UINT8 EnableExtts;
-
-/** Offset 0x054E - Closed Loop Therm Manage
- Enables/Disable Closed Loop Therm Manage
- $EN_DIS
-**/
- UINT8 EnableCltm;
-
-/** Offset 0x054F - Open Loop Therm Manage
- Enables/Disable Open Loop Therm Manage
- $EN_DIS
-**/
- UINT8 EnableOltm;
-
-/** Offset 0x0550 - DDR PowerDown and idle counter
- Enables/Disable DDR PowerDown and idle counter
- $EN_DIS
-**/
- UINT8 EnablePwrDn;
-
-/** Offset 0x0551 - DDR PowerDown and idle counter - LPDDR
- Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
- $EN_DIS
-**/
- UINT8 EnablePwrDnLpddr;
-
-/** Offset 0x0552 - Use user provided power weights, scale factor, and channel power floor values
- Enables/Disable Use user provided power weights, scale factor, and channel power
- floor values
- $EN_DIS
-**/
- UINT8 UserPowerWeightsEn;
-
-/** Offset 0x0553 - RAPL PL Lock
- Enables/Disable RAPL PL Lock
- $EN_DIS
-**/
- UINT8 RaplLim2Lock;
-
-/** Offset 0x0554 - RAPL PL 2 enable
- Enables/Disable RAPL PL 2 enable
- $EN_DIS
-**/
- UINT8 RaplLim2Ena;
-
-/** Offset 0x0555 - RAPL PL 1 enable
- Enables/Disable RAPL PL 1 enable
- $EN_DIS
-**/
- UINT8 RaplLim1Ena;
-
-/** Offset 0x0556 - SelfRefresh Enable
- Enables/Disable SelfRefresh Enable
- $EN_DIS
-**/
- UINT8 SrefCfgEna;
-
-/** Offset 0x0557 - Throttler CKEMin Defeature - LPDDR
- Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
- $EN_DIS
-**/
- UINT8 ThrtCkeMinDefeatLpddr;
-
-/** Offset 0x0558 - Throttler CKEMin Defeature
- Enables/Disable Throttler CKEMin Defeature
- $EN_DIS
-**/
- UINT8 ThrtCkeMinDefeat;
-
-/** Offset 0x0559 - Enable RH Prevention
- Enables/Disable RH Prevention
- $EN_DIS
-**/
- UINT8 RhPrevention;
-
-/** Offset 0x055A - Exit On Failure (MRC)
- Enables/Disable Exit On Failure (MRC)
- $EN_DIS
-**/
- UINT8 ExitOnFailure;
-
-/** Offset 0x055B - LPDDR Thermal Sensor
- Enables/Disable LPDDR Thermal Sensor
- $EN_DIS
-**/
- UINT8 DdrThermalSensor;
-
-/** Offset 0x055C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
- Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
- $EN_DIS
-**/
- UINT8 Ddr4DdpSharedClock;
-
-/** Offset 0x055D - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
- ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
- $EN_DIS
-**/
- UINT8 Ddr4DdpSharedZq;
-
-/** Offset 0x055E
-**/
- UINT8 UnusedUpdSpace14[2];
-
-/** Offset 0x0560 - Base reference clock value
- Base reference clock value, in Hertz(Default is 125Hz)
- 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
-**/
- UINT32 BClkFrequency;
-
-/** Offset 0x0564 - Ch Hash Interleaved Bit
- Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
- the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
- 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
-**/
- UINT8 ChHashInterleaveBit;
-
-/** Offset 0x0565
-**/
- UINT8 UnusedUpdSpace15;
-
-/** Offset 0x0566 - Ch Hash Mask
- Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
- BITS [19:6] Default is 0x30CC
-**/
- UINT16 ChHashMask;
-
-/** Offset 0x0568 - Extended Bank Hashing
- Eanble/Disable ExtendedBankHashing
- $EN_DIS
-**/
- UINT8 ExtendedBankHashing;
-
-/** Offset 0x0569 - Energy Scale Factor
- Energy Scale Factor, Default is 4
-**/
- UINT8 EnergyScaleFact;
-
-/** Offset 0x056A - EPG DIMM Idd3N
- Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
- a per DIMM basis. Default is 26
-**/
- UINT16 Idd3n;
-
-/** Offset 0x056C - EPG DIMM Idd3P
- Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
- on a per DIMM basis. Default is 11
-**/
- UINT16 Idd3p;
-
-/** Offset 0x056E - RH Activation Probability
- RH Activation Probability, Probability value is 1/2^(inputvalue)
-**/
- UINT8 RhActProbability;
-
-/** Offset 0x056F - RAPL PL 2 WindowX
- Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim2WindX;
-
-/** Offset 0x0570 - RAPL PL 2 WindowY
- Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim2WindY;
-
-/** Offset 0x0571 - RAPL PL 1 WindowX
- Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim1WindX;
-
-/** Offset 0x0572 - RAPL PL 1 WindowY
- Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim1WindY;
-
-/** Offset 0x0573
-**/
- UINT8 UnusedUpdSpace16;
-
-/** Offset 0x0574 - RAPL PL 2 Power
- range[0;2^14-1]= [2047.875;0]in W, (224= Def)
-**/
- UINT16 RaplLim2Pwr;
-
-/** Offset 0x0576 - RAPL PL 1 Power
- range[0;2^14-1]= [2047.875;0]in W, (224= Def)
-**/
- UINT16 RaplLim1Pwr;
-
-/** Offset 0x0578 - Warm Threshold Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 WarmThresholdCh0Dimm0;
-
-/** Offset 0x0579 - Warm Threshold Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 WarmThresholdCh0Dimm1;
-
-/** Offset 0x057A - Warm Threshold Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 WarmThresholdCh1Dimm0;
-
-/** Offset 0x057B - Warm Threshold Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 WarmThresholdCh1Dimm1;
-
-/** Offset 0x057C - Hot Threshold Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 HotThresholdCh0Dimm0;
-
-/** Offset 0x057D - Hot Threshold Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 HotThresholdCh0Dimm1;
-
-/** Offset 0x057E - Hot Threshold Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 HotThresholdCh1Dimm0;
-
-/** Offset 0x057F - Hot Threshold Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
-**/
- UINT8 HotThresholdCh1Dimm1;
-
-/** Offset 0x0580 - Warm Budget Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh0Dimm0;
-
-/** Offset 0x0581 - Warm Budget Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh0Dimm1;
-
-/** Offset 0x0582 - Warm Budget Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh1Dimm0;
-
-/** Offset 0x0583 - Warm Budget Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh1Dimm1;
-
-/** Offset 0x0584 - Hot Budget Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh0Dimm0;
-
-/** Offset 0x0585 - Hot Budget Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh0Dimm1;
-
-/** Offset 0x0586 - Hot Budget Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh1Dimm0;
-
-/** Offset 0x0587 - Hot Budget Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh1Dimm1;
-
-/** Offset 0x0588 - Idle Energy Ch0Dimm0
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh0Dimm0;
-
-/** Offset 0x0589 - Idle Energy Ch0Dimm1
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh0Dimm1;
-
-/** Offset 0x058A - Idle Energy Ch1Dimm0
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh1Dimm0;
-
-/** Offset 0x058B - Idle Energy Ch1Dimm1
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh1Dimm1;
-
-/** Offset 0x058C - PowerDown Energy Ch0Dimm0
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh0Dimm0;
-
-/** Offset 0x058D - PowerDown Energy Ch0Dimm1
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh0Dimm1;
-
-/** Offset 0x058E - PowerDown Energy Ch1Dimm0
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh1Dimm0;
-
-/** Offset 0x058F - PowerDown Energy Ch1Dimm1
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh1Dimm1;
-
-/** Offset 0x0590 - Activate Energy Ch0Dimm0
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh0Dimm0;
-
-/** Offset 0x0591 - Activate Energy Ch0Dimm1
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh0Dimm1;
-
-/** Offset 0x0592 - Activate Energy Ch1Dimm0
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh1Dimm0;
-
-/** Offset 0x0593 - Activate Energy Ch1Dimm1
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh1Dimm1;
-
-/** Offset 0x0594 - Read Energy Ch0Dimm0
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh0Dimm0;
-
-/** Offset 0x0595 - Read Energy Ch0Dimm1
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh0Dimm1;
-
-/** Offset 0x0596 - Read Energy Ch1Dimm0
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh1Dimm0;
-
-/** Offset 0x0597 - Read Energy Ch1Dimm1
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh1Dimm1;
-
-/** Offset 0x0598 - Write Energy Ch0Dimm0
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh0Dimm0;
-
-/** Offset 0x0599 - Write Energy Ch0Dimm1
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh0Dimm1;
-
-/** Offset 0x059A - Write Energy Ch1Dimm0
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh1Dimm0;
-
-/** Offset 0x059B - Write Energy Ch1Dimm1
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh1Dimm1;
-
-/** Offset 0x059C - Throttler CKEMin Timer
- Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
- Dfault is 0x30
-**/
- UINT8 ThrtCkeMinTmr;
-
-/** Offset 0x059D - Cke Rank Mapping
- Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
- which rank CKE[i] goes to.
-**/
- UINT8 CkeRankMapping;
-
-/** Offset 0x059E - Rapl Power Floor Ch0
- Power budget ,range[255;0],(0= 5.3W Def)
-**/
- UINT8 RaplPwrFlCh0;
-
-/** Offset 0x059F - Rapl Power Floor Ch1
- Power budget ,range[255;0],(0= 5.3W Def)
-**/
- UINT8 RaplPwrFlCh1;
-
-/** Offset 0x05A0 - Command Rate Support
- CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
- 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
-**/
- UINT8 EnCmdRate;
-
-/** Offset 0x05A1 - REFRESH_2X_MODE
- 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
- 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
-**/
- UINT8 Refresh2X;
-
-/** Offset 0x05A2 - Energy Performance Gain
- Enable/disable(default) Energy Performance Gain.
- $EN_DIS
-**/
- UINT8 EpgEnable;
-
-/** Offset 0x05A3 - Row Hammer Solution
- Type of method used to prevent Row Hammer. Default is 2x Refresh
- 0:Hardware RHP, 1:2x Refresh
-**/
- UINT8 RhSolution;
-
-/** Offset 0x05A4 - User Manual Threshold
- Disabled: Predefined threshold will be used.\n
- Enabled: User Input will be used.
- $EN_DIS
-**/
- UINT8 UserThresholdEnable;
-
-/** Offset 0x05A5 - User Manual Budget
- Disabled: Configuration of memories will defined the Budget value.\n
- Enabled: User Input will be used.
- $EN_DIS
-**/
- UINT8 UserBudgetEnable;
-
-/** Offset 0x05A6 - Power Down Mode
- This option controls command bus tristating during idle periods
- 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
-**/
- UINT8 PowerDownMode;
-
-/** Offset 0x05A7 - TcritMax
- Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
- has to be greater than THIGHMax .\n
- Critical temperature will be TcritMax
-**/
- UINT8 TsodTcritMax;
-
-/** Offset 0x05A8 - Event mode
- Disable:Comparator mode.\n
- Enable:Interrupt mode
- $EN_DIS
-**/
- UINT8 TsodEventMode;
-
-/** Offset 0x05A9 - EVENT polarity
- Disable:Active LOW.\n
- Enable:Active HIGH
- $EN_DIS
-**/
- UINT8 TsodEventPolarity;
-
-/** Offset 0x05AA - Critical event only
- Disable:Trips on alarm or critical.\n
- Enable:Trips only if criticaal temperature is reached
- $EN_DIS
-**/
- UINT8 TsodCriticalEventOnly;
-
-/** Offset 0x05AB - Event output control
- Disable:Event output disable.\n
- Enable:Event output enabled
- $EN_DIS
-**/
- UINT8 TsodEventOutputControl;
-
-/** Offset 0x05AC - Alarm window lock bit
- Disable:Alarm trips are not locked and can be changed.\n
- Enable:Alarm trips are locked and cannot be changed
- $EN_DIS
-**/
- UINT8 TsodAlarmwindowLockBit;
-
-/** Offset 0x05AD - Critical trip lock bit
- Disable:Critical trip is not locked and can be changed.\n
- Enable:Critical trip is locked and cannot be changed
- $EN_DIS
-**/
- UINT8 TsodCriticaltripLockBit;
-
-/** Offset 0x05AE - Shutdown mode
- Disable:Temperature sensor enable.\n
- Enable:Temperature sensor disable
- $EN_DIS
-**/
- UINT8 TsodShutdownMode;
-
-/** Offset 0x05AF - ThighMax
- Thigh = ThighMax (Default is 93)
-**/
- UINT8 TsodThigMax;
-
-/** Offset 0x05B0 - User Manual Thig and Tcrit
- Disabled(Default): Temperature will be given by the configuration of memories and
- 1x or 2xrefresh rate.\n
- Enabled: User Input will define for Thigh and Tcrit.
- $EN_DIS
-**/
- UINT8 TsodManualEnable;
-
-/** Offset 0x05B1 - Force OLTM or 2X Refresh when needed
- Disabled(Default): = Force OLTM.\n
- Enabled: = Force 2x Refresh.
- $EN_DIS
-**/
- UINT8 ForceOltmOrRefresh2x;
-
-/** Offset 0x05B2 - Pwr Down Idle Timer
- The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
- AUTO: 64 for ULX/ULT, 128 for DT/Halo
-**/
- UINT8 PwdwnIdleCounter;
-
-/** Offset 0x05B3 - Page Close Idle Timeout
- This option controls Page Close Idle Timeout
- 0:Enabled, 1:Disabled
-**/
- UINT8 DisPgCloseIdleTimeout;
-
-/** Offset 0x05B4 - Bitmask of ranks that have CA bus terminated
- Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
- Rank0 is terminating and Rank1 is non-terminating</b>
-**/
- UINT8 CmdRanksTerminated;
-
-/** Offset 0x05B5 - RMTLoopCount
- Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
-**/
- UINT8 RMTLoopCount;
-
-/** Offset 0x05B6 - Throttler CKEMin Timer for LPDDR
- LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH
- (4). Dfault is 0x40
-**/
- UINT8 ThrtCkeMinTmrLpddr;
-
-/** Offset 0x05B7 - Retrain on Fast Fail
- Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled
- $EN_DIS
-**/
- UINT8 RetrainOnFastFail;
-
-/** Offset 0x05B8 - Rank Margin Tool Per Bit
- Enable/disable Rank Margin Tool Per Bit.
- $EN_DIS
-**/
- UINT8 RMTBIT;
-
-/** Offset 0x05B9 - Read Timing Optimization
- Enables/Disable Read Timing Optimization
- $EN_DIS
-**/
- UINT8 RDTOPT;
-
-/** Offset 0x05BA - REFRESH_PANIC_WM
- Refresh Panic Watermark, range 1-9, Default is 9
-**/
- UINT8 RefreshPanicWm;
-
-/** Offset 0x05BB - REFRESH_HP_WM
- Refresh High Priority Watermark, range 1-9, Default is 8
-**/
- UINT8 RefreshHpWm;
-
-/** Offset 0x05BC - PcdSerialDebugLevel
- Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
- Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
- Info & Verbose.
- 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info, 5:Load Error Warnings Info and Verbose
-**/
- UINT8 PcdSerialDebugLevel;
-
-/** Offset 0x05BD - Fivr Faults
- Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
- $EN_DIS
-**/
- UINT8 FivrFaults;
-
-/** Offset 0x05BE - Fivr Efficiency
- Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
- $EN_DIS
-**/
- UINT8 FivrEfficiency;
-
-/** Offset 0x05BF - Safe Mode Support
- This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
- $EN_DIS
-**/
- UINT8 SafeMode;
-
-/** Offset 0x05C0 - Ask MRC to clear memory content
- Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
- $EN_DIS
-**/
- UINT8 CleanMemory;
-
-/** Offset 0x05C1 - TCSS USB Port Enable
- Bitmap for per port enabling
-**/
- UINT8 UsbTcPortEnPreMem;
-
-/** Offset 0x05C2 - Post Code Output Port
- This option configures Post Code Output Port
-**/
- UINT16 PostCodeOutputPort;
-
-/** Offset 0x05C4 - Enable/Disable SA CRID
- Enable: SA CRID, Disable (Default): SA CRID
- $EN_DIS
-**/
- UINT8 CridEnable;
-
-/** Offset 0x05C5
-**/
- UINT8 UnusedUpdSpace17[3];
-
-/** Offset 0x05C8 - BCLK RFI Frequency
- Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
- RFI Tuning</b>. Range is 98Mhz-100Mhz.
-**/
- UINT32 BclkRfiFreq[4];
-
-/** Offset 0x05D8 - Size of PCIe IMR.
- Size of PCIe IMR in megabytes
-**/
- UINT16 PcieImrSize;
-
-/** Offset 0x05DA - Enable PCIe IMR
- 0: Disable(AUTO), 1: Enable
- $EN_DIS
-**/
- UINT8 PcieImrEnabled;
-
-/** Offset 0x05DB - Enable PCIe IMR
- 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
- the Root port location from PCH PCIe or SA PCIe
- $EN_DIS
-**/
- UINT8 PcieImrRpLocation;
-
-/** Offset 0x05DC - Root port number for IMR.
- Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
- from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
-**/
- UINT8 PcieImrRpSelection;
-
-/** Offset 0x05DD - Mem Boot Mode
- 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
- 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
-**/
- UINT8 MemBootMode;
-
-/** Offset 0x05DE - PCIe ASPM programming will happen in relation to the Oprom
- This option is specifically needed for ASPM configuration in 2LM feature
- 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto
-**/
- UINT8 Peg3Aspm;
-
-/** Offset 0x05DF - MFVC WRR VC Arbitration
- 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES
- 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES
-**/
- UINT8 MfvcWrrArb;
-
-/** Offset 0x05E0 - VcId_7_0 values
- Select VC ID for arbitration
-**/
- UINT8 VcId_7_0[16];
-
-/** Offset 0x05F0 - Set Hw Parameters enable/disable
- 1: enable, 0: disable, Enable/disable setting of HW parameters
- $EN_DIS
-**/
- UINT8 SetHwParameters;
-
-/** Offset 0x05F1
-**/
- UINT8 UnusedUpdSpace18;
-
-/** Offset 0x05F2 - LTR L1.2 Threshold Value
- LTR L1.2 Threshold Value
-**/
- UINT16 Ltr_L1D2_ThVal;
-
-/** Offset 0x05F4 - LTR L1.2 Threshold Scale
- LTR L1.2 Threshold Scale
-**/
- UINT8 Ltr_L1D2_ThScale;
-
-/** Offset 0x05F5 - system power state
- system power state indicates the platform power state
-**/
- UINT8 SysPwrState;
-
-/** Offset 0x05F6 - Media Death Notification Enable/Disable
- 1: enable, 0: disable, Enable/disable for Media Death Notification
- $EN_DIS
-**/
- UINT8 MediaDeathNotification;
-
-/** Offset 0x05F7 - Health Log Notification Enable/Disable
- 1: enable, 0: disable, Enable/disable for Health Log Notification
- $EN_DIS
-**/
- UINT8 HealthLogNotification;
-
-/** Offset 0x05F8 - Temp crosses below TempThrottle Notification Enable/Disable
- 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification
- $EN_DIS
-**/
- UINT8 TempBelowThrottleNotification;
-
-/** Offset 0x05F9 - Temp crosses above TempThrottle Notification Enable/Disable
- 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification
- $EN_DIS
-**/
- UINT8 TempAboveThrottleNotification;
-
-/** Offset 0x05FA - Missing Commit Bit Notification Enable/Disable
- 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification
- $EN_DIS
-**/
- UINT8 MissingCommitBitNotification;
-
-/** Offset 0x05FB - NVMeHoldDisableBit
- 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit
- $EN_DIS
-**/
- UINT8 NVMeHoldDisableBit;
-
-/** Offset 0x05FC - PreMemRsvd
- Reserved for Pre-Mem
- $EN_DIS
-**/
- UINT8 ReservedFspmUpd[18];
-
-/** Offset 0x060E - Skip external display device scanning
- Enable: Do not scan for external display device, Disable (Default): Scan external
- display devices
- $EN_DIS
-**/
- UINT8 SkipExtGfxScan;
-
-/** Offset 0x060F - Generate BIOS Data ACPI Table
- Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
- $EN_DIS
-**/
- UINT8 BdatEnable;
-
-/** Offset 0x0610 - Detect External Graphics device for LegacyOpROM
- Detect and report if external graphics device only support LegacyOpROM or not (to
- support CSM auto-enable). Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 ScanExtGfxForLegacyOpRom;
-
-/** Offset 0x0611 - Lock PCU Thermal Management registers
- Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 LockPTMregs;
-
-/** Offset 0x0612 - Rsvd
- Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
- Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
- peak values unmodified
- $EN_DIS
-**/
- UINT8 PegGen3Rsvd;
-
-/** Offset 0x0613 - Panel Power Enable
- Control for enabling/disabling VDD force bit (Required only for early enabling of
- eDP panel). 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 PanelPowerEnable;
-
-/** Offset 0x0614 - BdatTestType
- Indicates the type of Memory Training data to populate into the BDAT ACPI table.
- 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
-**/
- UINT8 BdatTestType;
-
-/** Offset 0x0615 - SaPreMemTestRsvd
- Reserved for SA Pre-Mem Test
- $EN_DIS
-**/
- UINT8 SaPreMemTestRsvd[98];
-
-/** Offset 0x0677
-**/
- UINT8 UnusedUpdSpace19;
-
-/** Offset 0x0678 - TotalFlashSize
- Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
-**/
- UINT16 TotalFlashSize;
-
-/** Offset 0x067A - BiosSize
- Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
-**/
- UINT16 BiosSize;
-
-/** Offset 0x067C - TxtAcheckRequest
- Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
- $EN_DIS
-**/
- UINT8 TxtAcheckRequest;
-
-/** Offset 0x067D - SecurityTestRsvd
- Reserved for SA Pre-Mem Test
- $EN_DIS
-**/
- UINT8 SecurityTestRsvd[11];
-
-/** Offset 0x0688 - Smbus dynamic power gating
- Disable or Enable Smbus dynamic power gating.
- $EN_DIS
-**/
- UINT8 SmbusDynamicPowerGating;
-
-/** Offset 0x0689 - Disable and Lock Watch Dog Register
- Set 1 to clear WDT status, then disable and lock WDT registers.
- $EN_DIS
-**/
- UINT8 WdtDisableAndLock;
-
-/** Offset 0x068A - SMBUS SPD Write Disable
- Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
- Disable bit. For security recommendations, SPD write disable bit must be set.
- $EN_DIS
-**/
- UINT8 SmbusSpdWriteDisable;
-
-/** Offset 0x068B - VC Type
- Virtual Channel Type Select: 0: VC0, 1: VC1.
- 0: VC0, 1: VC1
-**/
- UINT8 PchHdaVcType;
-
-/** Offset 0x068C - Universal Audio Architecture compliance for DSP enabled system
- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
- driver or SST driver supported).
- $EN_DIS
-**/
- UINT8 PchHdaDspUaaCompliance;
-
-/** Offset 0x068D - Enable HD Audio Link
- Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkHdaEnable;
-
-/** Offset 0x068E - Enable HDA SDI lanes
- Enable/disable HDA SDI lanes.
-**/
- UINT8 PchHdaSdiEnable[2];
-
-/** Offset 0x0690 - HDA Power/Clock Gating (PGD/CGD)
- Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
- FORCE_ENABLE, 2: FORCE_DISABLE.
- 0: POR, 1: Force Enable, 2: Force Disable
-**/
- UINT8 PchHdaTestPowerClockGating;
-
-/** Offset 0x0691 - Enable HD Audio DMIC_N Link
- Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
-**/
- UINT8 PchHdaAudioLinkDmicEnable[2];
-
-/** Offset 0x0693
-**/
- UINT8 UnusedUpdSpace20[1];
-
-/** Offset 0x0694 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
-**/
- UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-
-/** Offset 0x069C - DMIC<N> ClkB Pin Muxing
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
-**/
- UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-
-/** Offset 0x06A4 - Enable HD Audio DSP
- Enable/disable HD Audio DSP feature.
- $EN_DIS
-**/
- UINT8 PchHdaDspEnable;
-
-/** Offset 0x06A5
-**/
- UINT8 UnusedUpdSpace21[3];
-
-/** Offset 0x06A8 - DMIC<N> Data Pin Muxing
- Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
-**/
- UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-
-/** Offset 0x06B0 - Enable HD Audio SSP0 Link
- Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
-**/
- UINT8 PchHdaAudioLinkSspEnable[6];
-
-/** Offset 0x06B6 - Enable HD Audio SoundWire#N Link
- Enable/disable HD Audio SNDW#N link. Muxed with HDA.
-**/
- UINT8 PchHdaAudioLinkSndwEnable[4];
-
-/** Offset 0x06BA - iDisp-Link Frequency
- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
- 4: 96MHz, 3: 48MHz
-**/
- UINT8 PchHdaIDispLinkFrequency;
-
-/** Offset 0x06BB - iDisp-Link T-mode
- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
- 0: 2T, 2: 4T, 3: 8T, 4: 16T
-**/
- UINT8 PchHdaIDispLinkTmode;
-
-/** Offset 0x06BC - iDisplay Audio Codec disconnection
- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
- $EN_DIS
-**/
- UINT8 PchHdaIDispCodecDisconnect;
-
-/** Offset 0x06BD - Tcc Tuning enable/disable
- Tcc (Time Coordinated Computing) Tuning Enabled
- $EN_DIS
-**/
- UINT8 TccTuningEnable;
-
-/** Offset 0x06BE
-**/
- UINT8 UnusedUpdSpace22[2];
-
-/** Offset 0x06C0 - Tcc Register File Base Address
- Tcc (Time Coordinated Computing) Register File Base Address
-**/
- UINT32 TccConfigBase;
-
-/** Offset 0x06C4 - Tcc Register File Size
- Tcc (Time Coordinated Computing) Register File Size
-**/
- UINT32 TccConfigSize;
-
-/** Offset 0x06C8 - Force ME DID Init Status
- Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
- ME DID init stat value
- $EN_DIS
-**/
- UINT8 DidInitStat;
-
-/** Offset 0x06C9 - CPU Replaced Polling Disable
- Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
- $EN_DIS
-**/
- UINT8 DisableCpuReplacedPolling;
-
-/** Offset 0x06CA - ME DID Message
- Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
- the DID message from being sent)
- $EN_DIS
-**/
- UINT8 SendDidMsg;
-
-/** Offset 0x06CB - Check HECI message before send
- Test, 0: disable, 1: enable, Enable/Disable message check.
- $EN_DIS
-**/
- UINT8 DisableMessageCheck;
-
-/** Offset 0x06CC - Skip MBP HOB
- Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
- $EN_DIS
-**/
- UINT8 SkipMbpHob;
-
-/** Offset 0x06CD - HECI2 Interface Communication
- Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
- $EN_DIS
-**/
- UINT8 HeciCommunication2;
-
-/** Offset 0x06CE - Enable KT device
- Test, 0: disable, 1: enable, Enable or Disable KT device.
- $EN_DIS
-**/
- UINT8 KtDeviceEnable;
-
-/** Offset 0x06CF
-**/
- UINT8 UnusedUpdSpace23[5];
-
-/** Offset 0x06D4
-**/
- UINT8 ReservedFspmUpd2[20];
-} FSP_M_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x06E8
-**/
- UINT8 UnusedUpdSpace24[6];
-
-/** Offset 0x06EE
-**/
- UINT16 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x004B - Enable/Disable CrashLog Device 10 + Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogDevice; + +/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x005C - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0068 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x007C - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0084 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x008A - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0094 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, + 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0095 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x0096 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0097 - LPDDR4 Write DQ/DQS Retraining + Enables/Disable LPDDR4 Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 Lp4DqsOscEn; + +/** Offset 0x0098 - Ibecc + Enables/Disable Ibecc + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x0099 - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x009A - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x009B - IbeccErrorInj Note: Modification accepts the disclaimer shown in the Help text + Disclaimer: Warning: This must NOT be enabled for production!!! Enabling Error Injection + allows attackers who have access to the Host Operating System to inject IBECC errors + that can cause unintended memory corruption and enable the leak of security data + in the BIOS stolen memory regions. + $EN_DIS +**/ + UINT8 IbeccErrorInj; + +/** Offset 0x009C - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x00A4 - IbeccProtectedRegionBases + IBECC Protected Region Bases +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x00B4 - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; + +/** Offset 0x00C4 - MrcTaskDebugPrintEnable + Mrc Task Debug Print Enable. 0(Default)=Disable, non-Zero=Enable Task Debug print +**/ + UINT8 MrcTaskDebugEnable; + +/** Offset 0x00C5 - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x00C6 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x00C7 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x00C8 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x00CC - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x00D0 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x00D2 - LowSupplyEnData + Enable: Enable Low Supply for LPDDR4 Data, Disable(Default) + $EN_DIS +**/ + UINT8 LowSupplyEnData; + +/** Offset 0x00D3 - LowSupplyEnCcc + Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default) + $EN_DIS +**/ + UINT8 LowSupplyEnCcc; + +/** Offset 0x00D4 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x00D5 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x00D6 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x00D7 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[4]; + +/** Offset 0x00DB - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), + 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x00DC - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x00DD - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x00DE - Enable DCI ModPHY Pwoer Gate + Enable ModPHY Pwoer Gate when DCI is enabled + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x00DF - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x00E0 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x00E1 - PCH Trace Hub Memory Region 0 buffer Size + Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg0Size; + +/** Offset 0x00E2 - PCH Trace Hub Memory Region 1 buffer Size + Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg1Size; + +/** Offset 0x00E3 - PchPreMemRsvd + Reserved for PCH Pre-Mem Reserved + $EN_DIS +**/ + UINT8 PchPreMemRsvd[7]; + +/** Offset 0x00EA - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x00EB - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x00EC - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x0110 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x0111 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x0112 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x0113 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x0114 - Vtd Programming for ITbt + 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdItbtEnable; + +/** Offset 0x0115 - Disable Te Igd + 0=Enable/FALSE(Te Igd enabled), 1=Disable/TRUE (Te Igd disabled) + $EN_DIS +**/ + UINT8 DisableTeIgd; + +/** Offset 0x0116 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x0117 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x0118 - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x0119 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x011A - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x011C - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x011D - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x011E - Low Frequency + SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, + 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 FreqSaGvLow; + +/** Offset 0x0120 - Mid Frequency + SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, + 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 FreqSaGvMid; + +/** Offset 0x0122 - Channel A DIMM Control + Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmChannel0; + +/** Offset 0x0123 - Channel B DIMM Control + Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmChannel1; + +/** Offset 0x0124 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x0125 - Ddr4OneDpc + DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 Ddr4OneDpc; + +/** Offset 0x0126 +**/ + UINT8 UnusedUpdSpace1[2]; + +/** Offset 0x0128 - MMA Test Content Pointer + Pointer to MMA Test Content in Memory +**/ + UINT32 MmaTestContentPtr; + +/** Offset 0x012C - MMA Test Content Size + Size of MMA Test Content in Memory +**/ + UINT32 MmaTestContentSize; + +/** Offset 0x0130 - MMA Test Config Pointer + Pointer to MMA Test Config in Memory +**/ + UINT32 MmaTestConfigPtr; + +/** Offset 0x0134 - MMA Test Config Size + Size of MMA Test Config in Memory +**/ + UINT32 MmaTestConfigSize; + +/** Offset 0x0138 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x0139 +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x013A - Memory Voltage + Memory Voltage Override (Vddq). Default = no override + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x013C - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x013D - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 Ratio; + +/** Offset 0x013E - tCL + CAS Latency, 0: AUTO, max: 31 +**/ + UINT8 tCL; + +/** Offset 0x013F - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 34 +**/ + UINT8 tCWL; + +/** Offset 0x0140 - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 63 +**/ + UINT16 tFAW; + +/** Offset 0x0142 - tRAS + RAS Active Time, 0: AUTO, max: 64 +**/ + UINT16 tRAS; + +/** Offset 0x0144 - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 +**/ + UINT8 tRCDtRP; + +/** Offset 0x0145 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x0146 - tREFI + Refresh Interval, 0: AUTO, max: 65535 +**/ + UINT16 tREFI; + +/** Offset 0x0148 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 +**/ + UINT16 tRFC; + +/** Offset 0x014A - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 +**/ + UINT8 tRRD; + +/** Offset 0x014B - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal + values: 5, 6, 7, 8, 9, 10, 12 +**/ + UINT8 tRTP; + +/** Offset 0x014C - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40 + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x014D - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 +**/ + UINT8 tWTR; + +/** Offset 0x014E - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x014F - DllBwEn[0] + DllBwEn[0], for 1067 (0..7) +**/ + UINT8 DllBwEn0; + +/** Offset 0x0150 - DllBwEn[1] + DllBwEn[1], for 1333 (0..7) +**/ + UINT8 DllBwEn1; + +/** Offset 0x0151 - DllBwEn[2] + DllBwEn[2], for 1600 (0..7) +**/ + UINT8 DllBwEn2; + +/** Offset 0x0152 - DllBwEn[3] + DllBwEn[3], for 1867 and up (0..7) +**/ + UINT8 DllBwEn3; + +/** Offset 0x0153 - ISVT IO Port Address + ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default +**/ + UINT8 IsvtIoPort; + +/** Offset 0x0154 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x0155 - Enable PSE Controller + 0: Disable; 1: Enable (Default) PSE controller + $EN_DIS +**/ + UINT8 PchPseEnable; + +/** Offset 0x0156 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x0157 - CPU Trace Hub Memory Region 0 + CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg0Size; + +/** Offset 0x0158 - CPU Trace Hub Memory Region 1 + CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg1Size; + +/** Offset 0x0159 - SA GV Low Gear + Gear Selection for SAGV Low point + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvLowGear2; + +/** Offset 0x015A - SA GV Mid Gear + Gear Selection for SAGV Mid point + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvMidGear2; + +/** Offset 0x015B - SA GV High Gear + Gear Selection for SAGV High point, or when SAGV is disabled + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvHighGear2; + +/** Offset 0x015C - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x015D +**/ + UINT8 UnusedUpdSpace4[3]; + +/** Offset 0x0160 - HECI1 BAR address + BAR address of HECI1 +**/ + UINT32 Heci1BarAddress; + +/** Offset 0x0164 - HECI2 BAR address + BAR address of HECI2 +**/ + UINT32 Heci2BarAddress; + +/** Offset 0x0168 - HECI3 BAR address + BAR address of HECI3 +**/ + UINT32 Heci3BarAddress; + +/** Offset 0x016C - HG dGPU Power Delay + HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is + 300=300 microseconds +**/ + UINT16 HgDelayAfterPwrEn; + +/** Offset 0x016E - HG dGPU Reset Delay + HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 + microseconds +**/ + UINT16 HgDelayAfterHoldReset; + +/** Offset 0x0170 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x0172 - PCIe ASPM programming will happen in relation to the Oprom + Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): + Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after + Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume + 0:Before, 1:After +**/ + UINT8 InitPcieAspmAfterOprom; + +/** Offset 0x0173 - Selection of the primary display device + 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0174 - Selection of PSMI Region size + 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 + 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB +**/ + UINT8 PsmiRegionSize; + +/** Offset 0x0175 +**/ + UINT8 UnusedUpdSpace5[3]; + +/** Offset 0x0178 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress + - 0x1) (Where ApertureSize = 256MB) +**/ + UINT32 GmAdr; + +/** Offset 0x017C - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x0180 - Selection of iGFX GTT Memory size + 1=2MB, 2=4MB, 3=8MB, Default is 3 + 1:2MB, 2:4MB, 3:8MB +**/ + UINT16 GttSize; + +/** Offset 0x0182 - Hybrid Graphics GPIO information for PEG 0 + Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + UINT8 CpuPcie0Rtd3Gpio[24]; + +/** Offset 0x019A - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x019B - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x019C - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x019D - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x019E - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x01A0 - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x01A2 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtExtraTurboVoltage; + +/** Offset 0x01A4 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x01A6 - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x01A7 - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x01A8 - This is policy to control iTBT PCIe Multiple Segment setting. + When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the + TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 PcieMultipleSegmentEnabled; + +/** Offset 0x01A9 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x01AA - IPU IMR Configuration + 0:IPU Camera, 1:IPU Gen Default is 0 + 0:IPU Camera, 1:IPU Gen +**/ + UINT8 SaIpuImrConfiguration; + +/** Offset 0x01AB - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. + $EN_DIS +**/ + UINT8 ImguClkOutEn[5]; + +/** Offset 0x01B0 - IPU FUSA Configuration + 0:FUSA Disable, 1:FUSA Enable Default is 0 + 0:FUSA Disable, 1:FUSA Enable +**/ + UINT8 SaIpuFusaConfigEnable; + +/** Offset 0x01B1 +**/ + UINT8 UnusedUpdSpace6[3]; + +/** Offset 0x01B4 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x01B8 - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpLinkDownGpios; + +/** Offset 0x01B9 - Enable ClockReq Messaging + ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): + Enable ClockReq Messaging + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpClockReqMsgEnable; + +/** Offset 0x01BA - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: CPU_PCIE_SPEED). +**/ + UINT8 CpuPcieRpPcieSpeed[4]; + +/** Offset 0x01BE - Selection of PSMI Support On/Off + 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support + $EN_DIS +**/ + UINT8 GtPsmiSupport; + +/** Offset 0x01BF - Selection of DiSM Region Size + DiSM Size to be allocated for 2LM Sku Default is 0 + 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB +**/ + UINT8 DismSize; + +/** Offset 0x01C0 - Pram Size + Persisted Ram Size. Default is Disabled + 0x30:Disable, 0x31:4MB, 0x32:16MB, 0x33:64MB +**/ + UINT8 PramSize; + +/** Offset 0x01C1 - SaPreMemProductionRsvd + Reserved for SA Pre-Mem Production + $EN_DIS +**/ + UINT8 SaPreMemProductionRsvd[138]; + +/** Offset 0x024B - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x024C - DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 DmiGen3EqPh2Enable; + +/** Offset 0x024D - DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 DmiGen3EqPh3Method; + +/** Offset 0x024E - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x024F - DeEmphasis control for DMI + DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB + 0: -6dB, 1: -3.5dB +**/ + UINT8 DmiDeEmphasis; + +/** Offset 0x0250 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x0258 - DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 DmiGen3EndPointPreset[8]; + +/** Offset 0x0260 - DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 DmiGen3EndPointHint[8]; + +/** Offset 0x0268 - DMI Gen3 RxCTLEp per-Bundle control + Range: 0-15, 0 is default for each bundle, must be specified based upon platform design +**/ + UINT8 DmiGen3RxCtlePeaking[4]; + +/** Offset 0x026C - BIST on Reset + Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x026D - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x026E - Over clocking support + Over clocking support; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x026F - Over clocking Lock + Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x0270 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x0271 - Core voltage mode + Core voltage mode; <b>0: Adaptive</b>; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x0272 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x0273 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x0274 - Enable or Disable CPU Ratio Override + Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 CpuRatioOverride; + +/** Offset 0x0275 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0276 - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- + <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo + is selected BIOS will start in max non-turbo mode and switch to Turbo mode. + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x0277 - Number of active cores + Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2: + 2 </b>;<b>3: 3 </b> + 0:All, 1:1, 2:2, 3:3 +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x0278 - Processor Early Power On Configuration FCLK setting + <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x0279 - Set JTAG power in C10 and deeper power states + False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 + and deeper power states for debug purpose. <b>0: False</b>; 1: True. + 0: False, 1: True +**/ + UINT8 JtagC10PowerGateDisable; + +/** Offset 0x027A - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x027B - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x027C - AVX3 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x027D - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: + Disable;<b> 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x027E - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x0280 - Core Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageAdaptive; + +/** Offset 0x0282 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x0284 - Core PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x0285 - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; <b>1: Enable.</b> + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x0286 - Ring voltage mode + Ring voltage mode; <b>0: Adaptive</b>; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x0287 - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x0288 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x028A - Ring Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageAdaptive; + +/** Offset 0x028C - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x028E +**/ + UINT8 UnusedUpdSpace7[2]; + +/** Offset 0x0290 - ElixirSpringsPatchAddr + Address of Elixir Springs Patches +**/ + UINT32 ElixirSpringsPatchAddr; + +/** Offset 0x0294 - ElixirSpringsPatchSize + Size of Elixir Springs Patches +**/ + UINT32 ElixirSpringsPatchSize; + +/** Offset 0x0298 - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: + No Change</b> + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x0299 - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x029A - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x029B +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x029C - EnableSgx + Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control + 0: Disable, 1: Enable, 2: Software Control +**/ + UINT8 EnableSgx; + +/** Offset 0x029D - Txt + Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x029E +**/ + UINT8 UnusedUpdSpace8[2]; + +/** Offset 0x02A0 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x02A4 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x02A8 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x02B0 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x02B4 - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x02B8 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x02BC - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x02C0 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x02C4 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x02C8 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x02D0 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x02D8 - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x02D9 - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS +**/ + UINT8 ReservedSecurityPreMem[6]; + +/** Offset 0x02DF - PCH Master Clock Gating Control + Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default + $EN_DIS +**/ + UINT8 PchMasterClockGating; + +/** Offset 0x02E0 - PCH Master Power Gating Control + Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default + $EN_DIS +**/ + UINT8 PchMasterPowerGating; + +/** Offset 0x02E1 +**/ + UINT8 UnusedUpdSpace9; + +/** Offset 0x02E2 - FIA Lane Reversal Enable/Disable config mask + Enable/Disable. 0: Disable, 1: enable, Enable or disable Lane Reversal. If Enabled, + the x2 FIA Lane will be flipped +**/ + UINT16 FiaLaneReversalEnable; + +/** Offset 0x02E4 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[24]; + +/** Offset 0x02FC - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[24]; + +/** Offset 0x0314 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; + +/** Offset 0x032C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; + +/** Offset 0x0344 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; + +/** Offset 0x035C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; + +/** Offset 0x0374 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; + +/** Offset 0x038C - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; + +/** Offset 0x03A4 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; + +/** Offset 0x03BC - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[24]; + +/** Offset 0x03D4 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; + +/** Offset 0x03EC - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; + +/** Offset 0x0404 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; + +/** Offset 0x041C - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; + +/** Offset 0x0434 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x043C - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x0444 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x044C - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x0454 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x045C - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x0464 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x046C - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x0474 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x047C - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x0484 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x048C - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x0494 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x049C - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x04A4 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x04AC - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x04B4 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x04BC - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x04C4 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x04C5 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x04C6 - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x04C7 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x04C8 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x04CA - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x04CB - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x04DB - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x04EB +**/ + UINT8 UnusedUpdSpace10; + +/** Offset 0x04EC - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; + +/** Offset 0x04F0 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x04F4 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x04F5 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x04F6 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x04F7 +**/ + UINT8 UnusedUpdSpace11; + +/** Offset 0x04F8 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x04FC - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x04FD - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x04FE - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x04FF +**/ + UINT8 UnusedUpdSpace12; + +/** Offset 0x0500 - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0504 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0505 - GT PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 +**/ + UINT8 GtPllVoltageOffset; + +/** Offset 0x0506 - Ring PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0507 - System Agent PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0508 - Memory Controller PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0509 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x050A - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x050B - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x050C - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x050D - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x050E - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x050F - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x0510 - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x0511 - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x0512 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0513 - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0514 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0515 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0516 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0517 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0518 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0519 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x051A - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x051B - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x051C - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x051D - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x051E - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x051F - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x0520 - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x0521 - Write Drive Strength/Equalization 2D + Enables/Disable Write Drive Strength/Equalization 2D + $EN_DIS +**/ + UINT8 WRDSEQT; + +/** Offset 0x0522 - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x0523 - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x0524 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0525 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x0526 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0527 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0528 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0529 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x052A - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x052B - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x052C - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x052D - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x052E - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x052F - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x0530 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0531 +**/ + UINT8 UnusedUpdSpace13; + +/** Offset 0x0532 - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x0534 - Memory Test + Enables/Disable Memory Test + $EN_DIS +**/ + UINT8 MEMTST; + +/** Offset 0x0535 - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x0536 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x0537 - Write Drive Strength Up/Dn independently + Enables/Disable Write Drive Strength Up/Dn independently + $EN_DIS +**/ + UINT8 WRDSUDT; + +/** Offset 0x0538 - Command Slew Rate Training + Enables/Disable Command Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x0539 - Command Drive Strength and Equalization 2D + Enables/Disable Command Drive Strength and Equalization 2D + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x053A - Command Normalization + Enables/Disable Command Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x053B - Early DQ Write Drive Strength and Equalization Training + Enables/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x053C - Read Voltage Centering + Enables/Disable Read Voltage Centering + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x053D - Write TCO Comp Training + Enables/Disable Write TCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x053E - Clock TCO Comp Training + Enables/Disable Clock TCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x053F - Dimm ODT CA Training + Enables/Disable Dimm ODT CA Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x0540 - Write TCO Dqs Training + Enables/Disable Write TCO Dqs Training + $EN_DIS +**/ + UINT8 TXTCODQS; + +/** Offset 0x0541 - Duty Cycle Correction + Enables/Disable Duty Cycle Correction + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0542 - DQ DFE Training + Enable/Disable DQ DFE Training + $EN_DIS +**/ + UINT8 DQDFE; + +/** Offset 0x0543 - Sense Amplifier Correction Training + Enable/Disable Sense Amplifier Correction Training + $EN_DIS +**/ + UINT8 SOTC; + +/** Offset 0x0544 - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0545 - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0546 - MRC Time Measure + Enable/Disable MRC Time Measure + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x0547 - MRC Fast Boot + Enable/Disable MRC Fast flow + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0548 - MRC Force Training on Warm + Enables/Disable the MRC training on warm boot + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x0549 - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x054A - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x054B - Memory Trace + Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of + equal size. This option may change TOLUD and REMAP values as needed. + $EN_DIS +**/ + UINT8 MemoryTrace; + +/** Offset 0x054C - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x054D - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x054E - Closed Loop Therm Manage + Enables/Disable Closed Loop Therm Manage + $EN_DIS +**/ + UINT8 EnableCltm; + +/** Offset 0x054F - Open Loop Therm Manage + Enables/Disable Open Loop Therm Manage + $EN_DIS +**/ + UINT8 EnableOltm; + +/** Offset 0x0550 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x0551 - DDR PowerDown and idle counter - LPDDR + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0552 - Use user provided power weights, scale factor, and channel power floor values + Enables/Disable Use user provided power weights, scale factor, and channel power + floor values + $EN_DIS +**/ + UINT8 UserPowerWeightsEn; + +/** Offset 0x0553 - RAPL PL Lock + Enables/Disable RAPL PL Lock + $EN_DIS +**/ + UINT8 RaplLim2Lock; + +/** Offset 0x0554 - RAPL PL 2 enable + Enables/Disable RAPL PL 2 enable + $EN_DIS +**/ + UINT8 RaplLim2Ena; + +/** Offset 0x0555 - RAPL PL 1 enable + Enables/Disable RAPL PL 1 enable + $EN_DIS +**/ + UINT8 RaplLim1Ena; + +/** Offset 0x0556 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0557 - Throttler CKEMin Defeature - LPDDR + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x0558 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x0559 - Enable RH Prevention + Enables/Disable RH Prevention + $EN_DIS +**/ + UINT8 RhPrevention; + +/** Offset 0x055A - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x055B - LPDDR Thermal Sensor + Enables/Disable LPDDR Thermal Sensor + $EN_DIS +**/ + UINT8 DdrThermalSensor; + +/** Offset 0x055C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedClock; + +/** Offset 0x055D - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x055E +**/ + UINT8 UnusedUpdSpace14[2]; + +/** Offset 0x0560 - Base reference clock value + Base reference clock value, in Hertz(Default is 125Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0564 - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0565 +**/ + UINT8 UnusedUpdSpace15; + +/** Offset 0x0566 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0568 - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x0569 - Energy Scale Factor + Energy Scale Factor, Default is 4 +**/ + UINT8 EnergyScaleFact; + +/** Offset 0x056A - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x056C - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x056E - RH Activation Probability + RH Activation Probability, Probability value is 1/2^(inputvalue) +**/ + UINT8 RhActProbability; + +/** Offset 0x056F - RAPL PL 2 WindowX + Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim2WindX; + +/** Offset 0x0570 - RAPL PL 2 WindowY + Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim2WindY; + +/** Offset 0x0571 - RAPL PL 1 WindowX + Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindX; + +/** Offset 0x0572 - RAPL PL 1 WindowY + Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindY; + +/** Offset 0x0573 +**/ + UINT8 UnusedUpdSpace16; + +/** Offset 0x0574 - RAPL PL 2 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim2Pwr; + +/** Offset 0x0576 - RAPL PL 1 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim1Pwr; + +/** Offset 0x0578 - Warm Threshold Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh0Dimm0; + +/** Offset 0x0579 - Warm Threshold Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh0Dimm1; + +/** Offset 0x057A - Warm Threshold Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh1Dimm0; + +/** Offset 0x057B - Warm Threshold Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh1Dimm1; + +/** Offset 0x057C - Hot Threshold Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh0Dimm0; + +/** Offset 0x057D - Hot Threshold Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh0Dimm1; + +/** Offset 0x057E - Hot Threshold Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh1Dimm0; + +/** Offset 0x057F - Hot Threshold Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh1Dimm1; + +/** Offset 0x0580 - Warm Budget Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh0Dimm0; + +/** Offset 0x0581 - Warm Budget Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh0Dimm1; + +/** Offset 0x0582 - Warm Budget Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh1Dimm0; + +/** Offset 0x0583 - Warm Budget Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh1Dimm1; + +/** Offset 0x0584 - Hot Budget Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh0Dimm0; + +/** Offset 0x0585 - Hot Budget Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh0Dimm1; + +/** Offset 0x0586 - Hot Budget Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh1Dimm0; + +/** Offset 0x0587 - Hot Budget Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh1Dimm1; + +/** Offset 0x0588 - Idle Energy Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh0Dimm0; + +/** Offset 0x0589 - Idle Energy Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh0Dimm1; + +/** Offset 0x058A - Idle Energy Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh1Dimm0; + +/** Offset 0x058B - Idle Energy Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh1Dimm1; + +/** Offset 0x058C - PowerDown Energy Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh0Dimm0; + +/** Offset 0x058D - PowerDown Energy Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh0Dimm1; + +/** Offset 0x058E - PowerDown Energy Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh1Dimm0; + +/** Offset 0x058F - PowerDown Energy Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh1Dimm1; + +/** Offset 0x0590 - Activate Energy Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh0Dimm0; + +/** Offset 0x0591 - Activate Energy Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh0Dimm1; + +/** Offset 0x0592 - Activate Energy Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh1Dimm0; + +/** Offset 0x0593 - Activate Energy Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh1Dimm1; + +/** Offset 0x0594 - Read Energy Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh0Dimm0; + +/** Offset 0x0595 - Read Energy Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh0Dimm1; + +/** Offset 0x0596 - Read Energy Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh1Dimm0; + +/** Offset 0x0597 - Read Energy Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh1Dimm1; + +/** Offset 0x0598 - Write Energy Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh0Dimm0; + +/** Offset 0x0599 - Write Energy Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh0Dimm1; + +/** Offset 0x059A - Write Energy Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh1Dimm0; + +/** Offset 0x059B - Write Energy Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh1Dimm1; + +/** Offset 0x059C - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x30 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x059D - Cke Rank Mapping + Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies + which rank CKE[i] goes to. +**/ + UINT8 CkeRankMapping; + +/** Offset 0x059E - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x059F - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x05A0 - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x05A1 - REFRESH_2X_MODE + 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot + 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only +**/ + UINT8 Refresh2X; + +/** Offset 0x05A2 - Energy Performance Gain + Enable/disable(default) Energy Performance Gain. + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x05A3 - Row Hammer Solution + Type of method used to prevent Row Hammer. Default is 2x Refresh + 0:Hardware RHP, 1:2x Refresh +**/ + UINT8 RhSolution; + +/** Offset 0x05A4 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x05A5 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x05A6 - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x05A7 - TcritMax + Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax + has to be greater than THIGHMax .\n + Critical temperature will be TcritMax +**/ + UINT8 TsodTcritMax; + +/** Offset 0x05A8 - Event mode + Disable:Comparator mode.\n + Enable:Interrupt mode + $EN_DIS +**/ + UINT8 TsodEventMode; + +/** Offset 0x05A9 - EVENT polarity + Disable:Active LOW.\n + Enable:Active HIGH + $EN_DIS +**/ + UINT8 TsodEventPolarity; + +/** Offset 0x05AA - Critical event only + Disable:Trips on alarm or critical.\n + Enable:Trips only if criticaal temperature is reached + $EN_DIS +**/ + UINT8 TsodCriticalEventOnly; + +/** Offset 0x05AB - Event output control + Disable:Event output disable.\n + Enable:Event output enabled + $EN_DIS +**/ + UINT8 TsodEventOutputControl; + +/** Offset 0x05AC - Alarm window lock bit + Disable:Alarm trips are not locked and can be changed.\n + Enable:Alarm trips are locked and cannot be changed + $EN_DIS +**/ + UINT8 TsodAlarmwindowLockBit; + +/** Offset 0x05AD - Critical trip lock bit + Disable:Critical trip is not locked and can be changed.\n + Enable:Critical trip is locked and cannot be changed + $EN_DIS +**/ + UINT8 TsodCriticaltripLockBit; + +/** Offset 0x05AE - Shutdown mode + Disable:Temperature sensor enable.\n + Enable:Temperature sensor disable + $EN_DIS +**/ + UINT8 TsodShutdownMode; + +/** Offset 0x05AF - ThighMax + Thigh = ThighMax (Default is 93) +**/ + UINT8 TsodThigMax; + +/** Offset 0x05B0 - User Manual Thig and Tcrit + Disabled(Default): Temperature will be given by the configuration of memories and + 1x or 2xrefresh rate.\n + Enabled: User Input will define for Thigh and Tcrit. + $EN_DIS +**/ + UINT8 TsodManualEnable; + +/** Offset 0x05B1 - Force OLTM or 2X Refresh when needed + Disabled(Default): = Force OLTM.\n + Enabled: = Force 2x Refresh. + $EN_DIS +**/ + UINT8 ForceOltmOrRefresh2x; + +/** Offset 0x05B2 - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x05B3 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x05B4 - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, + Rank0 is terminating and Rank1 is non-terminating</b> +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x05B5 - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x05B6 - Throttler CKEMin Timer for LPDDR + LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH + (4). Dfault is 0x40 +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x05B7 - Retrain on Fast Fail + Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled + $EN_DIS +**/ + UINT8 RetrainOnFastFail; + +/** Offset 0x05B8 - Rank Margin Tool Per Bit + Enable/disable Rank Margin Tool Per Bit. + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x05B9 - Read Timing Optimization + Enables/Disable Read Timing Optimization + $EN_DIS +**/ + UINT8 RDTOPT; + +/** Offset 0x05BA - REFRESH_PANIC_WM + Refresh Panic Watermark, range 1-9, Default is 9 +**/ + UINT8 RefreshPanicWm; + +/** Offset 0x05BB - REFRESH_HP_WM + Refresh High Priority Watermark, range 1-9, Default is 8 +**/ + UINT8 RefreshHpWm; + +/** Offset 0x05BC - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x05BD - Fivr Faults + Fivr Faults; 0: Disabled; <b>1: Enabled.</b> + $EN_DIS +**/ + UINT8 FivrFaults; + +/** Offset 0x05BE - Fivr Efficiency + Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b> + $EN_DIS +**/ + UINT8 FivrEfficiency; + +/** Offset 0x05BF - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x05C0 - Ask MRC to clear memory content + Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x05C1 - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x05C2 - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x05C4 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x05C5 +**/ + UINT8 UnusedUpdSpace17[3]; + +/** Offset 0x05C8 - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No + RFI Tuning</b>. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; + +/** Offset 0x05D8 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x05DA - Enable PCIe IMR + 0: Disable(AUTO), 1: Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x05DB - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS +**/ + UINT8 PcieImrRpLocation; + +/** Offset 0x05DC - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; + +/** Offset 0x05DD - Mem Boot Mode + 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION + 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION +**/ + UINT8 MemBootMode; + +/** Offset 0x05DE - PCIe ASPM programming will happen in relation to the Oprom + This option is specifically needed for ASPM configuration in 2LM feature + 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto +**/ + UINT8 Peg3Aspm; + +/** Offset 0x05DF - MFVC WRR VC Arbitration + 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES + 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES +**/ + UINT8 MfvcWrrArb; + +/** Offset 0x05E0 - VcId_7_0 values + Select VC ID for arbitration +**/ + UINT8 VcId_7_0[16]; + +/** Offset 0x05F0 - Set Hw Parameters enable/disable + 1: enable, 0: disable, Enable/disable setting of HW parameters + $EN_DIS +**/ + UINT8 SetHwParameters; + +/** Offset 0x05F1 +**/ + UINT8 UnusedUpdSpace18; + +/** Offset 0x05F2 - LTR L1.2 Threshold Value + LTR L1.2 Threshold Value +**/ + UINT16 Ltr_L1D2_ThVal; + +/** Offset 0x05F4 - LTR L1.2 Threshold Scale + LTR L1.2 Threshold Scale +**/ + UINT8 Ltr_L1D2_ThScale; + +/** Offset 0x05F5 - system power state + system power state indicates the platform power state +**/ + UINT8 SysPwrState; + +/** Offset 0x05F6 - Media Death Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Media Death Notification + $EN_DIS +**/ + UINT8 MediaDeathNotification; + +/** Offset 0x05F7 - Health Log Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Health Log Notification + $EN_DIS +**/ + UINT8 HealthLogNotification; + +/** Offset 0x05F8 - Temp crosses below TempThrottle Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification + $EN_DIS +**/ + UINT8 TempBelowThrottleNotification; + +/** Offset 0x05F9 - Temp crosses above TempThrottle Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification + $EN_DIS +**/ + UINT8 TempAboveThrottleNotification; + +/** Offset 0x05FA - Missing Commit Bit Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification + $EN_DIS +**/ + UINT8 MissingCommitBitNotification; + +/** Offset 0x05FB - NVMeHoldDisableBit + 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit + $EN_DIS +**/ + UINT8 NVMeHoldDisableBit; + +/** Offset 0x05FC - PreMemRsvd + Reserved for Pre-Mem + $EN_DIS +**/ + UINT8 ReservedFspmUpd[18]; + +/** Offset 0x060E - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x060F - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0610 - Detect External Graphics device for LegacyOpROM + Detect and report if external graphics device only support LegacyOpROM or not (to + support CSM auto-enable). Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 ScanExtGfxForLegacyOpRom; + +/** Offset 0x0611 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0612 - Rsvd + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS +**/ + UINT8 PegGen3Rsvd; + +/** Offset 0x0613 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0614 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0615 - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SaPreMemTestRsvd[98]; + +/** Offset 0x0677 +**/ + UINT8 UnusedUpdSpace19; + +/** Offset 0x0678 - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + UINT16 TotalFlashSize; + +/** Offset 0x067A - BiosSize + Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable +**/ + UINT16 BiosSize; + +/** Offset 0x067C - TxtAcheckRequest + Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. + $EN_DIS +**/ + UINT8 TxtAcheckRequest; + +/** Offset 0x067D - SecurityTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SecurityTestRsvd[11]; + +/** Offset 0x0688 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0689 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x068A - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x068B - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x068C - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x068D - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x068E - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x0690 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x0691 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0693 +**/ + UINT8 UnusedUpdSpace20[1]; + +/** Offset 0x0694 - DMIC<N> ClkA Pin Muxing (N - DMIC number) + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x069C - DMIC<N> ClkB Pin Muxing + Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x06A4 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x06A5 +**/ + UINT8 UnusedUpdSpace21[3]; + +/** Offset 0x06A8 - DMIC<N> Data Pin Muxing + Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x06B0 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x06B6 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x06BA - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x06BB - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x06BC - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x06BD - Tcc Tuning enable/disable + Tcc (Time Coordinated Computing) Tuning Enabled + $EN_DIS +**/ + UINT8 TccTuningEnable; + +/** Offset 0x06BE +**/ + UINT8 UnusedUpdSpace22[2]; + +/** Offset 0x06C0 - Tcc Register File Base Address + Tcc (Time Coordinated Computing) Register File Base Address +**/ + UINT32 TccConfigBase; + +/** Offset 0x06C4 - Tcc Register File Size + Tcc (Time Coordinated Computing) Register File Size +**/ + UINT32 TccConfigSize; + +/** Offset 0x06C8 - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x06C9 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x06CA - ME DID Message + Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent + the DID message from being sent) + $EN_DIS +**/ + UINT8 SendDidMsg; + +/** Offset 0x06CB - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x06CC - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x06CD - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x06CE - Enable KT device + Test, 0: disable, 1: enable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x06CF +**/ + UINT8 UnusedUpdSpace23[5]; + +/** Offset 0x06D4 +**/ + UINT8 ReservedFspmUpd2[20]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x06E8 +**/ + UINT8 UnusedUpdSpace24[6]; + +/** Offset 0x06EE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h index 641081fe03..4c3b9458f1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h @@ -1,4837 +1,4837 @@ -/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0020 - Logo Pointer
- Points to PEI Display Logo Image
-**/
- UINT32 LogoPtr;
-
-/** Offset 0x0024 - Logo Size
- Size of PEI Display Logo Image
-**/
- UINT32 LogoSize;
-
-/** Offset 0x0028 - Blt Buffer Address
- Address of Blt buffer
-**/
- UINT32 BltBufferAddress;
-
-/** Offset 0x002C - Blt Buffer Size
- Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
-**/
- UINT32 BltBufferSize;
-
-/** Offset 0x0030 - Graphics Configuration Ptr
- Points to VBT
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x0034 - Enable Device 4
- Enable/disable Device 4
- $EN_DIS
-**/
- UINT8 Device4Enable;
-
-/** Offset 0x0035 - Enable eMMC Controller
- Enable/disable eMMC Controller.
- $EN_DIS
-**/
- UINT8 ScsEmmcEnabled;
-
-/** Offset 0x0036 - Enable eMMC HS400 Mode
- Enable eMMC HS400 Mode.
- $EN_DIS
-**/
- UINT8 ScsEmmcHs400Enabled;
-
-/** Offset 0x0037 - Enable eMMC DDR50 Mode
- Enable eMMC DDR50 Mode.
- $EN_DIS
-**/
- UINT8 ScsEmmcDdr50Enabled;
-
-/** Offset 0x0038 - Use DLL values from policy
- Set if FSP should use HS400 DLL values from policy
- $EN_DIS
-**/
- UINT8 EmmcUseCustomDlls;
-
-/** Offset 0x0039
-**/
- UINT8 UnusedUpdSpace0[3];
-
-/** Offset 0x003C - Emmc Tx CMD Delay control register value
- Please see Tx CMD Delay Control register definition for help
-**/
- UINT32 EmmcTxCmdDelayRegValue;
-
-/** Offset 0x0040 - Emmc Tx DATA Delay control 1 register value
- Please see Tx DATA Delay control 1 register definition for help
-**/
- UINT32 EmmcTxDataDelay1RegValue;
-
-/** Offset 0x0044 - Emmc Tx DATA Delay control 2 register value
- Please see Tx DATA Delay control 2 register definition for help
-**/
- UINT32 EmmcTxDataDelay2RegValue;
-
-/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 1 register value
- Please see Rx CMD + DATA Delay control 1 register definition for help
-**/
- UINT32 EmmcRxCmdDataDelay1RegValue;
-
-/** Offset 0x004C - Emmc Rx CMD + DATA Delay control 2 register value
- Please see Rx CMD + DATA Delay control 2 register definition for help
-**/
- UINT32 EmmcRxCmdDataDelay2RegValue;
-
-/** Offset 0x0050 - Emmc Rx Strobe Delay control register value
- Please see Rx Strobe Delay control register definition for help
-**/
- UINT32 EmmcRxStrobeDelayRegValue;
-
-/** Offset 0x0054 - Enable SdCard Controller
- Enable/disable SD Card Controller.
- $EN_DIS
-**/
- UINT8 ScsSdCardEnabled;
-
-/** Offset 0x0055 - SdCard power enable polarity
- Choose SD_PWREN# polarity
- 0: Active low, 1: Active high
-**/
- UINT8 SdCardPowerEnableActiveHigh;
-
-/** Offset 0x0056 - Use tuned DLL values from policy
- Set if FSP should use HS400 DLL values from policy
- $EN_DIS
-**/
- UINT8 SdCardUseCustomDlls;
-
-/** Offset 0x0057
-**/
- UINT8 UnusedUpdSpace1;
-
-/** Offset 0x0058 - SdCard Tx CMD Delay control register value
- Please see Tx CMD Delay Control register definition for help
-**/
- UINT32 SdCardTxCmdDelayRegValue;
-
-/** Offset 0x005C - SdCard Tx DATA Delay control 1 register value
- Please see Tx DATA Delay control 1 register definition for help
-**/
- UINT32 SdCardTxDataDelay1RegValue;
-
-/** Offset 0x0060 - SdCard Tx DATA Delay control 2 register value
- Please see Tx DATA Delay control 2 register definition for help
-**/
- UINT32 SdCardTxDataDelay2RegValue;
-
-/** Offset 0x0064 - SdCard Rx CMD + DATA Delay control 1 register value
- Please see Rx CMD + DATA Delay control 1 register definition for help
-**/
- UINT32 SdCardRxCmdDataDelay1RegValue;
-
-/** Offset 0x0068 - SdCard Rx CMD + DATA Delay control 2 register value
- Please see Rx CMD + DATA Delay control 2 register definition for help
-**/
- UINT32 SdCardRxCmdDataDelay2RegValue;
-
-/** Offset 0x006C - SdCard Power Enable Pin Mux
- Select Power Enable pin muxing. Refer to GPIO_*_MUXING_SDCARD_PWR_EN* for possible values.
-**/
- UINT32 SdCardGpioPrwEnBPinMux;
-
-/** Offset 0x0070 - SdCard Power Enable Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioPrwEnBPadTermination;
-
-/** Offset 0x0071
-**/
- UINT8 UnusedUpdSpace2[3];
-
-/** Offset 0x0074 - SdCard Command Pin Mux
- Select Command pin muxing. Refer to GPIO_*_MUXING_SDCARD_CMD* for possible values.
-**/
- UINT32 SdCardGpioCmdPinMux;
-
-/** Offset 0x0078 - SdCard Command Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioCmdPadTermination;
-
-/** Offset 0x0079
-**/
- UINT8 UnusedUpdSpace3[3];
-
-/** Offset 0x007C - SdCard Data Pin Mux
- Select Data pin muxing. Refer to GPIO_*_MUXING_SDCARD_DATAx_* for possible values.
- One UINT32 for each data pin [0-4]
-**/
- UINT32 SdCardGpioDataPinMux[4];
-
-/** Offset 0x008C - SdCard Data Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up. One byte for each data pin [0-4]
-**/
- UINT8 SdCardGpioDataPadTermination[4];
-
-/** Offset 0x0090 - SdCard Cdb Pin Mux
- Select Cdb pin muxing. Refer to GPIO_*_MUXING_SDCARD_CDB* for possible values.
-**/
- UINT32 SdCardGpioCdbPinMux;
-
-/** Offset 0x0094 - SdCard Cdb Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioCdbPadTermination;
-
-/** Offset 0x0095
-**/
- UINT8 UnusedUpdSpace4[3];
-
-/** Offset 0x0098 - SdCard Clock Pin Mux
- Select Clock pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK* for possible values.
-**/
- UINT32 SdCardGpioClkPinMux;
-
-/** Offset 0x009C - SdCard Clock Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioClkPadTermination;
-
-/** Offset 0x009D
-**/
- UINT8 UnusedUpdSpace5[3];
-
-/** Offset 0x00A0 - SdCard Wp PinMux
- Select Wp pin muxing. Refer to GPIO_*_MUXING_SDCARD_WP* for possible values.
-**/
- UINT32 SdCardGpioWpPinMux;
-
-/** Offset 0x00A4 - SdCard Wp Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioWpPadTermination;
-
-/** Offset 0x00A5
-**/
- UINT8 UnusedUpdSpace6[3];
-
-/** Offset 0x00A8 - SdCard Clock Feedback Pin Mux
- Select pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK_FB* for possible values.
-**/
- UINT32 SdCardGpioClkFbPinMux;
-
-/** Offset 0x00AC - SdCard Clock Feedback Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 SdCardGpioClkFbPadTermination;
-
-/** Offset 0x00AD
-**/
- UINT8 UnusedUpdSpace7[3];
-
-/** Offset 0x00B0 - Emmc Command Pin Mux
- Select pin muxing. Refer to GPIO_*_MUXING_EMMC_CMD* for possible values.
-**/
- UINT32 EmmcGpioCmdPinMux;
-
-/** Offset 0x00B4 - Emmc Command Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 EmmcGpioCmdPadTermination;
-
-/** Offset 0x00B5 - Emmc Data Pin Mux
- Select pin muxing. Refer to GPIO_*_MUXING_EMMC_DATA_x* for possible values. One
- UINT32 for each data pin [0-8]
-**/
- UINT8 EmmcGpioDataPinMux[32];
-
-/** Offset 0x00D5 - Emmc Data Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up. One byte for each data pin [0-8]
-**/
- UINT8 EmmcGpioDataPadTermination[8];
-
-/** Offset 0x00DD
-**/
- UINT8 UnusedUpdSpace8[3];
-
-/** Offset 0x00E0 - Emmc Rclk PinMux
- Select Rclk pin muxing. Refer to GPIO_*_MUXING_EMMC_RCLK* for possible values.
-**/
- UINT32 EmmcGpioRclkPinMux;
-
-/** Offset 0x00E4 - Emmc Rclk Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 EmmcGpioRclkPadTermination;
-
-/** Offset 0x00E5
-**/
- UINT8 UnusedUpdSpace9[3];
-
-/** Offset 0x00E8 - Emmc Clock Pin Mux
- Select Clock pin muxing. Refer to GPIO_*_MUXING_EMMC_CLK* for possible values.
-**/
- UINT32 EmmcGpioClkPinMux;
-
-/** Offset 0x00EC - Emmc Clock Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 EmmcGpioClkPadTermination;
-
-/** Offset 0x00ED
-**/
- UINT8 UnusedUpdSpace10[3];
-
-/** Offset 0x00F0 - Emmc Resetb PinMux
- Select Resetb pin muxing. Refer to GPIO_*_MUXING_EMMC_RESETB* for possible values.
-**/
- UINT32 EmmcGpioResetbPinMux;
-
-/** Offset 0x00F4 - Emmc Resetb Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 EmmcGpioResetbPadTermination;
-
-/** Offset 0x00F5
-**/
- UINT8 UnusedUpdSpace11[3];
-
-/** Offset 0x00F8 - Emmc HipMon PinMux
- Select HipMon pin muxing. Refer to GPIO_*_MUXING_EMMC_HIP_MON* for possible values.
-**/
- UINT32 EmmcGpioHipMonPinMux;
-
-/** Offset 0x00FC - Emmc HipMon Pad Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up
-**/
- UINT8 EmmcGpioHipMonPadTermination;
-
-/** Offset 0x00FD - Show SPI controller
- Enable/disable to show SPI controller.
- $EN_DIS
-**/
- UINT8 ShowSpiController;
-
-/** Offset 0x00FE
-**/
- UINT8 UnusedUpdSpace12[2];
-
-/** Offset 0x0100 - MicrocodeRegionBase
- Memory Base of Microcode Updates
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0104 - MicrocodeRegionSize
- Size of Microcode Updates
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0108 - SiipRegionBase
- Memory Base of Siip Firmware
-**/
- UINT32 SiipRegionBase;
-
-/** Offset 0x010C - SiipRegionSize
- Size of Siip Firmware
-**/
- UINT32 SiipRegionSize;
-
-/** Offset 0x0110 - Turbo Mode
- Enable/Disable Turbo mode. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 TurboMode;
-
-/** Offset 0x0111 - Enable SATA SALP Support
- Enable/disable SATA Aggressive Link Power Management.
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0112 - PCH Sata Port Multiplier
- Enable / Disable SATA Port Multiplier
- $EN_DIS
-**/
- UINT8 SataPortMultiplier;
-
-/** Offset 0x0113 - Enable SATA ports
- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
- and so on.
-**/
- UINT8 SataPortsEnable[8];
-
-/** Offset 0x011B - Enable SATA DEVSLP Feature
- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
- port, byte0 for port0, byte1 for port1, and so on.
-**/
- UINT8 SataPortsDevSlp[8];
-
-/** Offset 0x0123 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb20Enable[16];
-
-/** Offset 0x0133 - Enable USB2 ports OTG
- Selectively Enable/Disable USB2 OTG Mode. One byte for each port, byte0 for port0,
- byte1 for port1, and so on.
-**/
- UINT8 USB20Otg[16];
-
-/** Offset 0x0143 - Enable USB3 ports OTG
- Selectively Enable/Disable USB3 OTG Mode. One byte for each port, byte0 for port0,
- byte1 for port1, and so on.
-**/
- UINT8 USB30Otg[10];
-
-/** Offset 0x014D - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb30Enable[10];
-
-/** Offset 0x0157 - Enable xDCI controller
- Enable/disable to xDCI controller.
- $EN_DIS
-**/
- UINT8 XdciEnable;
-
-/** Offset 0x0158 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
- The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
-**/
- UINT32 DevIntConfigPtr;
-
-/** Offset 0x015C - Number of DevIntConfig Entry
- Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
- must not be NULL.
-**/
- UINT8 NumOfDevIntConfig;
-
-/** Offset 0x015D - PIRQx to IRQx Map Config
- PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
- PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
- 8259 PCI mode.
-**/
- UINT8 PxRcConfig[8];
-
-/** Offset 0x0165 - Select GPIO IRQ Route
- GPIO IRQ Select. The valid value is 14 or 15.
-**/
- UINT8 GpioIrqRoute;
-
-/** Offset 0x0166 - Select SciIrqSelect
- SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
-**/
- UINT8 SciIrqSelect;
-
-/** Offset 0x0167 - Select TcoIrqSelect
- TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
-**/
- UINT8 TcoIrqSelect;
-
-/** Offset 0x0168 - Enable/Disable Tco IRQ
- Enable/disable TCO IRQ
- $EN_DIS
-**/
- UINT8 TcoIrqEnable;
-
-/** Offset 0x0169 - PCH HDA Verb Table Entry Number
- Number of Entries in Verb Table.
-**/
- UINT8 PchHdaVerbTableEntryNum;
-
-/** Offset 0x016A
-**/
- UINT8 UnusedUpdSpace13[2];
-
-/** Offset 0x016C - PCH HDA Verb Table Pointer
- Pointer to Array of pointers to Verb Table.
-**/
- UINT32 PchHdaVerbTablePtr;
-
-/** Offset 0x0170 - PCH HDA Codec Sx Wake Capability
- Capability to detect wake initiated by a codec in Sx
-**/
- UINT8 PchHdaCodecSxWakeCapability;
-
-/** Offset 0x0171 - Enable SATA
- Enable/disable SATA controller.
- $EN_DIS
-**/
- UINT8 SataEnable;
-
-/** Offset 0x0172 - SATA Mode
- Select SATA controller working mode.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x0173 - SPIn Device Mode
- Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
- modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
-**/
- UINT8 SerialIoSpiMode[7];
-
-/** Offset 0x017A - SPI<N> Chip Select Polarity
- Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
- 1:SerialIoSpiCsActiveHigh
-**/
- UINT8 SerialIoSpiCsPolarity[14];
-
-/** Offset 0x0188 - SPI<N> Chip Select Enable
- 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
-**/
- UINT8 SerialIoSpiCsEnable[14];
-
-/** Offset 0x0196 - SPIn Default Chip Select Output
- Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
- options: 0:CS0, 1:CS1
-**/
- UINT8 SerialIoSpiDefaultCsOutput[7];
-
-/** Offset 0x019D - SPIn Default Chip Select Mode HW/SW
- Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
- SPI1, ... Available options: 0:HW, 1:SW
-**/
- UINT8 SerialIoSpiCsMode[7];
-
-/** Offset 0x01A4 - SPIn Default Chip Select State Low/High
- Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
- Available options: 0:Low, 1:High
-**/
- UINT8 SerialIoSpiCsState[7];
-
-/** Offset 0x01AB - SPIn Master Input Slave Output Enable/Disable
- 0:Disabled, 1:Enabled. Sets Native Mode for SPIx MISO GPIO if it is Enabled
-**/
- UINT8 SerialIoSpiMisoEnable[3];
-
-/** Offset 0x01AE - SPIn Delayed Rx Clock setting
- 00:As-is, 01:Internal, 10:NegEdge Tx Clock, 11:NegEdge Delayed Rx Clk. Configure
- Delayed Rx Clock
-**/
- UINT8 SerialIoSpiDelayRxClk[3];
-
-/** Offset 0x01B1 - UARTn Device Mode
- Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
- modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 SerialIoUartMode[7];
-
-/** Offset 0x01B8 - Default BaudRate for each Serial IO UART
- Set default BaudRate Supported from 0 - default to 6000000
-**/
- UINT32 SerialIoUartBaudRate[7];
-
-/** Offset 0x01D4 - Default ParityType for each Serial IO UART
- Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
- UINT8 SerialIoUartParity[7];
-
-/** Offset 0x01DB - Default DataBits for each Serial IO UART
- Set default word length. 0: Default, 5,6,7,8
-**/
- UINT8 SerialIoUartDataBits[7];
-
-/** Offset 0x01E2 - Default StopBits for each Serial IO UART
- Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
- TwoStopBits
-**/
- UINT8 SerialIoUartStopBits[7];
-
-/** Offset 0x01E9 - Power Gating mode for each Serial IO UART that works in COM mode
- Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
-**/
- UINT8 SerialIoUartPowerGating[7];
-
-/** Offset 0x01F0 - Enable Dma for each Serial IO UART that supports it
- Set DMA/PIO mode. 0: Disabled, 1: Enabled
-**/
- UINT8 SerialIoUartDmaEnable[7];
-
-/** Offset 0x01F7 - Enables UART hardware flow control, CTS and RTS lines
- Enables UART hardware flow control, CTS and RTS lines.
-**/
- UINT8 SerialIoUartAutoFlow[7];
-
-/** Offset 0x01FE
-**/
- UINT8 UnusedUpdSpace14[2];
-
-/** Offset 0x0200 - SerialIoUartRtsPinMuxPolicy
- Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
- for possible values.
-**/
- UINT32 SerialIoUartRtsPinMuxPolicy[7];
-
-/** Offset 0x021C - SerialIoUartCtsPinMuxPolicy
- Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
- for possible values.
-**/
- UINT32 SerialIoUartCtsPinMuxPolicy[7];
-
-/** Offset 0x0238 - SerialIoUartRxPinMuxPolicy
- Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
- possible values.
-**/
- UINT32 SerialIoUartRxPinMuxPolicy[7];
-
-/** Offset 0x0254 - SerialIoUartTxPinMuxPolicy
- Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
- possible values.
-**/
- UINT32 SerialIoUartTxPinMuxPolicy[7];
-
-/** Offset 0x0270 - UART Number For Debug Purpose
- UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
- 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
- for debug purpose.
- 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
-**/
- UINT8 SerialIoDebugUartNumber;
-
-/** Offset 0x0271 - Serial IO UART DBG2 table
- Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
- 1: Enable.
-**/
- UINT8 SerialIoUartDbg2[7];
-
-/** Offset 0x0278 - I2Cn Device Mode
- Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
- modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
-**/
- UINT8 SerialIoI2cMode[8];
-
-/** Offset 0x0280 - Serial IO I2C SDA Pin Muxing
- Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSdaPinMux[8];
-
-/** Offset 0x02A0 - Serial IO I2C SCL Pin Muxing
- Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSclPinMux[8];
-
-/** Offset 0x02C0 - PCH SerialIo I2C Pads Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
- respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
- 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU
-**/
- UINT8 PchSerialIoI2cPadsTermination[8];
-
-/** Offset 0x02C8 - USB Per Port HS Preemphasis Bias
- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
-**/
- UINT8 Usb2PhyPetxiset[16];
-
-/** Offset 0x02D8 - USB Per Port HS Transmitter Bias
- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
-**/
- UINT8 Usb2PhyTxiset[16];
-
-/** Offset 0x02E8 - USB Per Port HS Transmitter Emphasis
- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
-**/
- UINT8 Usb2PhyPredeemp[16];
-
-/** Offset 0x02F8 - USB Per Port Half Bit Pre-emphasis
- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
- One byte for each port.
-**/
- UINT8 Usb2PhyPehalfbit[16];
-
-/** Offset 0x0308 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmphEnable[10];
-
-/** Offset 0x0312 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmph[10];
-
-/** Offset 0x031C - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-
-/** Offset 0x0326 - USB 3.0 TX Output Downscale Amplitude Adjustment
- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
- = 00h</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmp[10];
-
-/** Offset 0x0330
-**/
- UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
-
-/** Offset 0x033A
-**/
- UINT8 PchUsb3HsioFilterSelNEnable[10];
-
-/** Offset 0x0344
-**/
- UINT8 PchUsb3HsioFilterSelPEnable[10];
-
-/** Offset 0x034E
-**/
- UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
-
-/** Offset 0x0358
-**/
- UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
-
-/** Offset 0x0362
-**/
- UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
-
-/** Offset 0x036C
-**/
- UINT8 PchUsb3HsioFilterSelN[10];
-
-/** Offset 0x0376
-**/
- UINT8 PchUsb3HsioFilterSelP[10];
-
-/** Offset 0x0380 - Enable LAN
- Enable/disable LAN controller.
- $EN_DIS
-**/
- UINT8 PchLanEnable;
-
-/** Offset 0x0381 - Enable PCH TSN
- Enable/disable TSN on the PCH.
- $EN_DIS
-**/
- UINT8 PchTsnEnable;
-
-/** Offset 0x0382 - PCH TSN Multi VC Enable
- Enable/Disable PCH TSN GBE Multiple Virtual Channel
- $EN_DIS
-**/
- UINT8 PchTsnGbeMultiVcEnable;
-
-/** Offset 0x0383 - PCH TSN Link Speed
- Set PCH TSN Link Speed.
- 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
-**/
- UINT8 PchTsnGbeLinkSpeed;
-
-/** Offset 0x0384 - PCH TSN SGMII Support
- Enable/disable SGMII support
- $EN_DIS
-**/
- UINT8 PchTsnGbeSgmiiEnable;
-
-/** Offset 0x0385 - PSE TSN Multi VC Enable
- Enable/Disable PSE TSN GBE Multiple Virtual Channel
- $EN_DIS
-**/
- UINT8 PseTsnGbeMultiVcEnable[2];
-
-/** Offset 0x0387 - PSE TSN Link Speed
- Set TSN Link Speed.
- 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
-**/
- UINT8 PseTsnGbeLinkSpeed[2];
-
-/** Offset 0x0389 - PSE TSN SGMII Support
- Enable/disable SGMII support
- $EN_DIS
-**/
- UINT8 PseTsnGbeSgmiiEnable[2];
-
-/** Offset 0x038B - PSE TSN Phy Interface Type
- Set PSE TSN Phy Interface Type
- 0: Not Connected, 1: RGMII, 2: SGMII, 3:SGMII+
-**/
- UINT8 PseTsnGbePhyInterfaceType[2];
-
-/** Offset 0x038D
-**/
- UINT8 UnusedUpdSpace15[3];
-
-/** Offset 0x0390 - Tsn Mac Address Sub Region Base
- Base address of TSN MAC Address Sub Region
-**/
- UINT32 TsnMacAddrBase;
-
-/** Offset 0x0394 - Tsn Mac Address Sub Region Size
- Size of TSN MAC Address Sub Region
-**/
- UINT32 TsnMacAddrSize;
-
-/** Offset 0x0398 - PSE Tsn Ip Config Sub Region Base
- Base address of PSE TSN IP Config Sub Region
-**/
- UINT32 PseTsnIpConfigBase;
-
-/** Offset 0x039C - PSE Tsn Ip Config Sub Region Size
- Size of PSE TSN IP Config Sub Region
-**/
- UINT32 PseTsnIpConfigSize;
-
-/** Offset 0x03A0 - Tsn Config Sub Region Base
- Base address of TSN Config Sub Region
-**/
- UINT32 TsnConfigBase;
-
-/** Offset 0x03A4 - Tsn Config Sub Region Size
- Size of TSN Config Sub Region
-**/
- UINT32 TsnConfigSize;
-
-/** Offset 0x03A8 - PSE GBE0 DLL OVERRIDE
- Enable/Disable PSE GBE DLL OVERRIDE
- $EN_DIS
-**/
- UINT8 PseGbeDllOverride[2];
-
-/** Offset 0x03AA - PSE GBE TX_Delay
- PSE GBE TX_Delay configuration.
-**/
- UINT8 PseGbeTxDelay[2];
-
-/** Offset 0x03AC - PCIe PTM enable/disable
- Enable/disable Precision Time Measurement for PCIE Root Ports.
-**/
- UINT8 PciePtm[24];
-
-/** Offset 0x03C4 - PCIe DPC enable/disable
- Enable/disable Downstream Port Containment for PCIE Root Ports.
-**/
- UINT8 PcieDpc[24];
-
-/** Offset 0x03DC - PCIe DPC extensions enable/disable
- Enable/disable Downstream Port Containment Extensions for PCIE Root Ports.
-**/
- UINT8 PcieEdpc[24];
-
-/** Offset 0x03F4 - USB PDO Programming
- Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
- during later phase. 1: enable, 0: disable
- $EN_DIS
-**/
- UINT8 UsbPdoProgramming;
-
-/** Offset 0x03F5
-**/
- UINT8 UnusedUpdSpace16[3];
-
-/** Offset 0x03F8 - Power button debounce configuration
- Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
- be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
-**/
- UINT32 PmcPowerButtonDebounce;
-
-/** Offset 0x03FC - PCH eSPI Master and Slave BME enabled
- PCH eSPI Master and Slave BME enabled
- $EN_DIS
-**/
- UINT8 PchEspiBmeMasterSlaveEnabled;
-
-/** Offset 0x03FD - PCH SATA use RST Legacy OROM
- Use PCH SATA RST Legacy OROM when CSM is Enabled
- $EN_DIS
-**/
- UINT8 SataRstLegacyOrom;
-
-/** Offset 0x03FE - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
- Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
-**/
- UINT8 PchFivrExtV1p05RailEnabledStates;
-
-/** Offset 0x03FF - Mask to enable the platform configuration of external V1p05 VR rail
- External V1P05 Rail Supported Configuration
-**/
- UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
-
-/** Offset 0x0400 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
- Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
-**/
- UINT16 PchFivrExtV1p05RailVoltage;
-
-/** Offset 0x0402 - External V1P05 Icc Max Value
- Granularity of this setting is 1mA and maximal possible value is 200mA
-**/
- UINT8 PchFivrExtV1p05RailIccMax;
-
-/** Offset 0x0403 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
- Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
-**/
- UINT8 PchFivrExtVnnRailEnabledStates;
-
-/** Offset 0x0404 - Mask to enable the platform configuration of external Vnn VR rail
- External Vnn Rail Supported Configuration
-**/
- UINT8 PchFivrExtVnnRailSupportedVoltageStates;
-
-/** Offset 0x0405
-**/
- UINT8 UnusedUpdSpace17;
-
-/** Offset 0x0406 - External Vnn Voltage Value that will be used in S0ix/Sx states
- Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
-**/
- UINT16 PchFivrExtVnnRailVoltage;
-
-/** Offset 0x0408 - External Vnn Icc Max Value that will be used in S0ix/Sx states
- Granularity of this setting is 1mA and maximal possible value is 200mA
-**/
- UINT8 PchFivrExtVnnRailIccMax;
-
-/** Offset 0x0409 - Mask to enable the usage of external Vnn VR rail in Sx states
- Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
- Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
-**/
- UINT8 PchFivrExtVnnRailSxEnabledStates;
-
-/** Offset 0x040A - External Vnn Voltage Value that will be used in Sx states
- Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
- (0=0mV, 1=2.5mV, 2=5mV...)
-**/
- UINT16 PchFivrExtVnnRailSxVoltage;
-
-/** Offset 0x040C - External Vnn Icc Max Value that will be used in Sx states
- Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
- is 1mA and maximal possible value is 200mA
-**/
- UINT8 PchFivrExtVnnRailSxIccMax;
-
-/** Offset 0x040D - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to low current mode voltage.
-**/
- UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
-
-/** Offset 0x040E - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to retention mode voltage.
-**/
- UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-
-/** Offset 0x040F - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to retention mode voltage.
-**/
- UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
-
-/** Offset 0x0410 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
- This field has 1us resolution. When value is 0 Transition to 0V is disabled.
-**/
- UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
-
-/** Offset 0x0412
-**/
- UINT8 UnusedUpdSpace18[2];
-
-/** Offset 0x0414 - Trace Hub Memory Base
- If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
- trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
- memory is configured properly.
-**/
- UINT32 TraceHubMemBase;
-
-/** Offset 0x0418 - PMC Debug Message Enable
- When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
- will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
- $EN_DIS
-**/
- UINT8 PmcDbgMsgEn;
-
-/** Offset 0x0419
-**/
- UINT8 UnusedUpdSpace19[3];
-
-/** Offset 0x041C - Pointer of ChipsetInit Binary
- ChipsetInit Binary Pointer.
-**/
- UINT32 ChipsetInitBinPtr;
-
-/** Offset 0x0420 - Length of ChipsetInit Binary
- ChipsetInit Binary Length.
-**/
- UINT32 ChipsetInitBinLen;
-
-/** Offset 0x0424 - ChipsetInit Sync Enable
- Enable/Disable. 0: Disable, 1: Enable
-**/
- UINT8 ChipsetInitSyncEnable;
-
-/** Offset 0x0425 - FIVR Dynamic Power Management
- Enable/Disable FIVR Dynamic Power Management.
- $EN_DIS
-**/
- UINT8 PchFivrDynPm;
-
-/** Offset 0x0426 - External V1P05 Icc Max Value
- Granularity of this setting is 1mA and maximal possible value is 500mA
-**/
- UINT16 PchFivrExtV1p05RailIccMaximum;
-
-/** Offset 0x0428 - External Vnn Icc Max Value that will be used in S0ix/Sx states
- Granularity of this setting is 1mA and maximal possible value is 500mA
-**/
- UINT16 PchFivrExtVnnRailIccMaximum;
-
-/** Offset 0x042A - External Vnn Icc Max Value that will be used in Sx states
- Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
- is 1mA and maximal possible value is 500mA
-**/
- UINT16 PchFivrExtVnnRailSxIccMaximum;
-
-/** Offset 0x042C - PCH eSPI Link Configuration Lock (SBLCL)
- Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves
- addresseses from range 0x0 - 0x7FF
- $EN_DIS
-**/
- UINT8 PchEspiLockLinkConfiguration;
-
-/** Offset 0x042D - Extented BIOS Direct Read Decode enable
- Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads.
- 0: disabled (default), 1: enabled
- $EN_DIS
-**/
- UINT8 PchSpiExtendedBiosDecodeRangeEnable;
-
-/** Offset 0x042E - PchPostMemRsvd
- Reserved for PCH Post-Mem
- $EN_DIS
-**/
- UINT8 PchPostMemRsvd[11];
-
-/** Offset 0x0439
-**/
- UINT8 UnusedUpdSpace20[3];
-
-/** Offset 0x043C - Extended BIOS Direct Read Decode Range base
- Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
-**/
- UINT32 PchSpiExtendedBiosDecodeRangeBase;
-
-/** Offset 0x0440 - Extended BIOS Direct Read Decode Range limit
- Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode.
-**/
- UINT32 PchSpiExtendedBiosDecodeRangeLimit;
-
-/** Offset 0x0444 - CNVi Configuration
- This option allows for automatic detection of Connectivity Solution. [Auto Detection]
- assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
- 0:Disable, 1:Auto
-**/
- UINT8 CnviMode;
-
-/** Offset 0x0445 - CNVi BT Core
- Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtCore;
-
-/** Offset 0x0446 - CNVi BT Audio Offload
- Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtAudioOffload;
-
-/** Offset 0x0447
-**/
- UINT8 UnusedUpdSpace21;
-
-/** Offset 0x0448 - CNVi RF_RESET pin muxing
- Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default)
- or GPP_F4 = 0x194BE404. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*
- in GpioPins*.h.
-**/
- UINT32 CnviRfResetPinMux;
-
-/** Offset 0x044C - CNVi CLKREQ pin muxing
- Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default)
- or GPP_F5 = 0x394BE605. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_*
- in GpioPins*.h.
-**/
- UINT32 CnviClkreqPinMux;
-
-/** Offset 0x0450 - Enable Host C10 reporting through eSPI
- Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire.
- $EN_DIS
-**/
- UINT8 PchEspiHostC10ReportEnable;
-
-/** Offset 0x0451 - PCH USB2 PHY Power Gating enable
- 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
- Sus Well PG
- $EN_DIS
-**/
- UINT8 PmcUsb2PhySusPgEnable;
-
-/** Offset 0x0452 - PCH USB OverCurrent mapping enable
- 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
- mapping allow for NOA usage of OC pins
- $EN_DIS
-**/
- UINT8 PchUsbOverCurrentEnable;
-
-/** Offset 0x0453 - Espi Lgmr Memory Range decode
- This option enables or disables espi lgmr
- $EN_DIS
-**/
- UINT8 PchEspiLgmrEnable;
-
-/** Offset 0x0454 - External V1P05 Control Ramp Timer value
- Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
-**/
- UINT8 PchFivrExtV1p05RailCtrlRampTmr;
-
-/** Offset 0x0455 - External VNN Control Ramp Timer value
- Hold off time to be used when changing the vnn_ctrl for external bypass value in us
-**/
- UINT8 PchFivrExtVnnRailCtrlRampTmr;
-
-/** Offset 0x0456 - HECI3 state
- The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
- 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 Heci3Enabled;
-
-/** Offset 0x0457 - PCHHOT# pin
- Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchHotEnable;
-
-/** Offset 0x0458 - SATA LED
- SATA LED indicating SATA controller activity. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 SataLedEnable;
-
-/** Offset 0x0459 - VRAlert# Pin
- When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
- to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchPmVrAlert;
-
-/** Offset 0x045A - AMT Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
- $EN_DIS
-**/
- UINT8 AmtEnabled;
-
-/** Offset 0x045B - WatchDog Timer Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
- is invalid if AmtEnabled is 0.
- $EN_DIS
-**/
- UINT8 WatchDogEnabled;
-
-/** Offset 0x045C - Manageability Mode set by Mebx
- Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
- $EN_DIS
-**/
- UINT8 ManageabilityMode;
-
-/** Offset 0x045D - PET Progress
- Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
- PET Events. Setting is invalid if AmtEnabled is 0.
- $EN_DIS
-**/
- UINT8 FwProgress;
-
-/** Offset 0x045E - SOL Switch
- Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
- Setting is invalid if AmtEnabled is 0.
- $EN_DIS
-**/
- UINT8 AmtSolEnabled;
-
-/** Offset 0x045F
-**/
- UINT8 UnusedUpdSpace22;
-
-/** Offset 0x0460 - OS Timer
- 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
-**/
- UINT16 WatchDogTimerOs;
-
-/** Offset 0x0462 - BIOS Timer
- 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
-**/
- UINT16 WatchDogTimerBios;
-
-/** Offset 0x0464 - Remote Assistance Trigger Availablilty
- Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
- $EN_DIS
-**/
- UINT8 RemoteAssistance;
-
-/** Offset 0x0465 - KVM Switch
- Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
- is invalid if AmtEnabled is 0.
- $EN_DIS
-**/
- UINT8 AmtKvmEnabled;
-
-/** Offset 0x0466 - KVM Switch
- Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx.
- $EN_DIS
-**/
- UINT8 ForcMebxSyncUp;
-
-/** Offset 0x0467 - PCH PCIe root port connection type
- 0: built-in device, 1:slot
-**/
- UINT8 PcieRpSlotImplemented[24];
-
-/** Offset 0x047F - PCIE RP Access Control Services Extended Capability
- Enable/Disable PCIE RP Access Control Services Extended Capability
-**/
- UINT8 PcieRpAcsEnabled[24];
-
-/** Offset 0x0497 - PCIE RP Clock Power Management
- Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
- can still be controlled by L1 PM substates mechanism
-**/
- UINT8 PcieRpEnableCpm[24];
-
-/** Offset 0x04AF - PCIE RP Multi VC Enabled
- Enable/Disable PCIE RP Multiple Virtual Channels
-**/
- UINT8 PcieRpMultiVcEnabled[24];
-
-/** Offset 0x04C7 - PCIE RP VC1 to TC Mapping
- PCIE RP Virtual Channel 1 to Traffic Class mapping
-**/
- UINT8 PcieRpVc1TcMap[24];
-
-/** Offset 0x04DF
-**/
- UINT8 UnusedUpdSpace23[1];
-
-/** Offset 0x04E0 - PCIE RP Detect Timeout Ms
- The number of milliseconds within 0~65535 in reference code will wait for link to
- exit Detect state for enabled ports before assuming there is no device and potentially
- disabling the port.
-**/
- UINT16 PcieRpDetectTimeoutMs[24];
-
-/** Offset 0x0510 - ModPHY SUS Power Domain Dynamic Gating
- Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
- PCH-H. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PmcModPhySusPgEnable;
-
-/** Offset 0x0511 - V1p05-PHY supply external FET control
- Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
- supply. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PmcV1p05PhyExtFetControlEn;
-
-/** Offset 0x0512 - V1p05-IS supply external FET control
- Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
- supply. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PmcV1p05IsExtFetControlEn;
-
-/** Offset 0x0513 - Enable/Disable PavpEnable
- Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
- $EN_DIS
-**/
- UINT8 PavpEnable;
-
-/** Offset 0x0514 - CdClock Frequency selection
- 0 (Default) Auto (Max based on reference clock frequency), 0: 307.2, 1: 312 Mhz,
- 2: 552 Mhz, 3: 556.8 Mhz, 4: 648 Mhz, 5: 652.8 Mhz
- 0xFF: Auto (Max based on reference clock frequency), 0: 307.2, 1: 312 Mhz, 2: 552
- Mhz, 3: 556.8 Mhz, 4: 648 Mhz, 5: 652.8 Mhz
-**/
- UINT8 CdClock;
-
-/** Offset 0x0515 - Enable/Disable PeiGraphicsPeimInit
- Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x0516 - Enable D3 Hot in TCSS
- This policy will enable/disable D3 hot support in IOM
- $EN_DIS
-**/
- UINT8 D3HotEnable;
-
-/** Offset 0x0517 - Enable or disable GNA device
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 GnaEnable;
-
-/** Offset 0x0518 - Enable or disable HPD of DDI port-A device
- 0=Disabled,1(Default)=eDP, 2=MIPI DSI,
- 0:Disabled, 1:eDP, 2:MIPI DSI
-**/
- UINT8 DdiPortAConfig;
-
-/** Offset 0x0519 - Enable or disable HPD of DDI port-B device
- 1(Default)=DP, 2=MIPI DSI, 3=HDMI
- 1:DP, 2:MIPI DSI, 3:HDMI
-**/
- UINT8 DdiPortBConfig;
-
-/** Offset 0x051A - Enable or disable HPD of DDI port-C device
- 1(Default)= HDMI, 2=DP
- 1:HDMI, 2:DP
-**/
- UINT8 DdiPortCConfig;
-
-/** Offset 0x051B - Enable or disable HPD of DDI port A
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortAHpd;
-
-/** Offset 0x051C - Enable or disable HPD of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBHpd;
-
-/** Offset 0x051D - Enable or disable HPD of DDI port C
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCHpd;
-
-/** Offset 0x051E - Enable or disable HPD of DDI port 1
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort1Hpd;
-
-/** Offset 0x051F - Enable or disable HPD of DDI port 2
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort2Hpd;
-
-/** Offset 0x0520 - Enable or disable HPD of DDI port 3
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort3Hpd;
-
-/** Offset 0x0521 - Enable or disable HPD of DDI port 4
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort4Hpd;
-
-/** Offset 0x0522 - Enable or disable DDC of DDI port A
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortADdc;
-
-/** Offset 0x0523 - Enable or disable DDC of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBDdc;
-
-/** Offset 0x0524 - Enable or disable DDC of DDI port C
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCDdc;
-
-/** Offset 0x0525 - Enable DDC setting of DDI Port 1
- 0=Disable, 1=DDC(Default)
- 0: Disable, 1: DDC
-**/
- UINT8 DdiPort1Ddc;
-
-/** Offset 0x0526 - Enable DDC setting of DDI Port 2
- 0=Disable, 1=DDC(Default)
- 0: Disable, 1: DDC
-**/
- UINT8 DdiPort2Ddc;
-
-/** Offset 0x0527 - Enable DDC setting of DDI Port 3
- 0=Disable, 1=DDC(Default)
- 0: Disable, 1: DDC
-**/
- UINT8 DdiPort3Ddc;
-
-/** Offset 0x0528 - Enable DDC setting of DDI Port 4
- 0=Disable, 1=DDC(Default)
- 0: Disable, 1: DDC
-**/
- UINT8 DdiPort4Ddc;
-
-/** Offset 0x0529
-**/
- UINT8 UnusedUpdSpace24[3];
-
-/** Offset 0x052C - TypeC port GPIO setting
- GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
- in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Ehl
- = ElkhartLake)
-**/
- UINT32 IomTypeCPortPadCfg[8];
-
-/** Offset 0x054C - CPU USB3 Port Over Current Pin
- Describe the specific over current pin number of USBC Port N.
-**/
- UINT8 CpuUsb3OverCurrentPin[8];
-
-/** Offset 0x0554 - Enable D3 Cold in TCSS
- This policy will enable/disable D3 cold support in IOM
- $EN_DIS
-**/
- UINT8 D3ColdEnable;
-
-/** Offset 0x0555 - PchPostMemRsvd
- Reserved for PCH Post-Mem
- $EN_DIS
-**/
- UINT8 SaPostMemRsvd[8];
-
-/** Offset 0x055D - Enable VMD controller
- Enable/disable to VMD controller.0: Disable(Default); 1: Enable
- $EN_DIS
-**/
- UINT8 VmdEnable;
-
-/** Offset 0x055E - Enable VMD portA Support
- Enable/disable to VMD portA Support.
- $EN_DIS
-**/
- UINT8 VmdPortA;
-
-/** Offset 0x055F - Enable VMD portB Support
- Enable/disable to VMD portB Support.
- $EN_DIS
-**/
- UINT8 VmdPortB;
-
-/** Offset 0x0560 - Enable VMD portC Support
- Enable/disable to VMD portC Support.
- $EN_DIS
-**/
- UINT8 VmdPortC;
-
-/** Offset 0x0561 - Enable VMD portD Support
- Enable/disable to VMD portD Support.
- $EN_DIS
-**/
- UINT8 VmdPortD;
-
-/** Offset 0x0562 - VMD Config Bar size
- Set The VMD Config Bar Size.
-**/
- UINT8 VmdCfgBarSz;
-
-/** Offset 0x0563 - VMD Config Bar Attributes
- 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default)
- 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
-**/
- UINT8 VmdCfgBarAttr;
-
-/** Offset 0x0564 - VMD Mem Bar1 size
- Set The VMD Mem Bar1 Size.
-**/
- UINT8 VmdMemBarSz1;
-
-/** Offset 0x0565 - VMD Mem Bar1 Attributes
- 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
- 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
-**/
- UINT8 VmdMemBar1Attr;
-
-/** Offset 0x0566 - VMD Mem Bar2 size
- Set The VMD Mem Bar2 Size.
-**/
- UINT8 VmdMemBarSz2;
-
-/** Offset 0x0567 - VMD Mem Bar2 Attributes
- 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
- 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
-**/
- UINT8 VmdMemBar2Attr;
-
-/** Offset 0x0568 - Enable/Disable PMC-PD Solution
- This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
- $EN_DIS
-**/
- UINT8 PmcPdEnable;
-
-/** Offset 0x0569
-**/
- UINT8 UnusedUpdSpace25;
-
-/** Offset 0x056A - TCSS Aux Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssAuxOri;
-
-/** Offset 0x056C - TCSS HSL Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssHslOri;
-
-/** Offset 0x056E - USB override in IOM
- This policy will enable/disable USB Connect override in IOM
- $EN_DIS
-**/
- UINT8 UsbOverride;
-
-/** Offset 0x056F - TCSS USB Port Enable
- Bits 0, 1, ... max Type C port control enables
-**/
- UINT8 UsbTcPortEn;
-
-/** Offset 0x0570 - ITBT Root Port Enable
- ITBT Root Port Enable, 0:Disable, 1:Enable
- 0:Disable, 1:Enable
-**/
- UINT8 ITbtPcieRootPortEn[4];
-
-/** Offset 0x0574 - ITBTForcePowerOn Timeout value
- ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
- 100 = 100 ms.
-**/
- UINT16 ITbtForcePowerOnTimeoutInMs;
-
-/** Offset 0x0576 - ITbtConnectTopology Timeout value
- ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
- is 0-10000. 100 = 100 ms.
-**/
- UINT16 ITbtConnectTopologyTimeoutInMs;
-
-/** Offset 0x0578 - VCCST request for IOM
- This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
- $EN_DIS
-**/
- UINT8 VccSt;
-
-/** Offset 0x0579
-**/
- UINT8 UnusedUpdSpace26[1];
-
-/** Offset 0x057A - ITBT DMA LTR
- TCSS DMA1, DMA2 LTR value
-**/
- UINT16 ITbtDmaLtr[2];
-
-/** Offset 0x057E - Enable/Disable CrashLog
- Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
- $EN_DIS
-**/
- UINT8 CpuCrashLogEnable;
-
-/** Offset 0x057F - Enable/Disable PTM
- This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
- $EN_DIS
-**/
- UINT8 PtmEnabled[4];
-
-/** Offset 0x0583 - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 SaPcieItbtRpLtrEnable[4];
-
-/** Offset 0x0587 - PCIE RP Snoop Latency Override Mode
- Latency Tolerance Reporting, Snoop Latency Override Mode.
-**/
- UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
-
-/** Offset 0x058B - PCIE RP Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Snoop Latency Override Multiplier.
-**/
- UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
-
-/** Offset 0x058F
-**/
- UINT8 UnusedUpdSpace27[1];
-
-/** Offset 0x0590 - PCIE RP Snoop Latency Override Value
- Latency Tolerance Reporting, Snoop Latency Override Value.
-**/
- UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
-
-/** Offset 0x0598 - PCIE RP Non Snoop Latency Override Mode
- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
-**/
- UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
-
-/** Offset 0x059C - PCIE RP Non Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
-**/
- UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
-
-/** Offset 0x05A0 - PCIE RP Non Snoop Latency Override Value
- Latency Tolerance Reporting, Non-Snoop Latency Override Value.
-**/
- UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
-
-/** Offset 0x05A8 - Force LTR Override
- Force LTR Override.
-**/
- UINT8 SaPcieItbtRpForceLtrOverride[4];
-
-/** Offset 0x05AC - PCIE RP Ltr Config Lock
- 0: Disable; 1: Enable.
-**/
- UINT8 SaPcieItbtRpLtrConfigLock[4];
-
-/** Offset 0x05B0 - Advanced Encryption Standard (AES) feature
- Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
- $EN_DIS
-**/
- UINT8 AesEnable;
-
-/** Offset 0x05B1 - Power State 3 enable/disable
- PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
- For all VR Indexes
-**/
- UINT8 Psi3Enable[5];
-
-/** Offset 0x05B6 - Power State 4 enable/disable
- PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
- all VR Indexes
-**/
- UINT8 Psi4Enable[5];
-
-/** Offset 0x05BB
-**/
- UINT8 UnusedUpdSpace28[1];
-
-/** Offset 0x05BC - Imon slope correction
- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
-**/
- UINT16 ImonSlope[5];
-
-/** Offset 0x05C6 - Imon offset correction
- PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
- Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
-**/
- UINT16 ImonOffset[5];
-
-/** Offset 0x05D0 - Enable/Disable BIOS configuration of VR
- Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
-**/
- UINT8 VrConfigEnable[5];
-
-/** Offset 0x05D5 - Thermal Design Current enable/disable
- PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
- Enable.For all VR Indexes
-**/
- UINT8 TdcEnable[5];
-
-/** Offset 0x05DA
-**/
- UINT8 UnusedUpdSpace29[2];
-
-/** Offset 0x05DC - Thermal Design Current time window
- PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
- Range 1ms to 448s
-**/
- UINT32 TdcTimeWindow[5];
-
-/** Offset 0x05F0 - Thermal Design Current Lock
- PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
- all VR Indexes
-**/
- UINT8 TdcLock[5];
-
-/** Offset 0x05F5 - Platform Psys slope correction
- PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
- 1/100 increment values. Range is 0-200. 125 = 1.25
-**/
- UINT8 PsysSlope;
-
-/** Offset 0x05F6 - Platform Psys offset correction
- PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/1000,
- Range 0-63999. For an offset of 25.348, enter 25348.
-**/
- UINT16 PsysOffset;
-
-/** Offset 0x05F8 - Acoustic Noise Mitigation feature
- Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
- $EN_DIS
-**/
- UINT8 AcousticNoiseMitigation;
-
-/** Offset 0x05F9 - Disable Fast Slew Rate for Deep Package C States for VR domains
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisable[5];
-
-/** Offset 0x05FE - Slew Rate configuration for Deep Package C States for VR domains
- Slew Rate configuration for Deep Package C States for VR domains based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRate[5];
-
-/** Offset 0x0603
-**/
- UINT8 UnusedUpdSpace30[1];
-
-/** Offset 0x0604 - Thermal Design Current current limit
- PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
- Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
-**/
- UINT16 TdcCurrentLimit[5];
-
-/** Offset 0x060E - AcLoadline
- PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
-**/
- UINT16 AcLoadline[5];
-
-/** Offset 0x0618 - DcLoadline
- PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
-**/
- UINT16 DcLoadline[5];
-
-/** Offset 0x0622 - Power State 1 Threshold current
- PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi1Threshold[5];
-
-/** Offset 0x062C - Power State 2 Threshold current
- PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi2Threshold[5];
-
-/** Offset 0x0636 - Power State 3 Threshold current
- PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi3Threshold[5];
-
-/** Offset 0x0640 - Icc Max limit
- PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
-**/
- UINT16 IccMax[5];
-
-/** Offset 0x064A - Enable VR specific mailbox command
- VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
- VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
- command sent for PS4 exit issue. 11b - Reserved.
- $EN_DIS
-**/
- UINT8 SendVrMbxCmd;
-
-/** Offset 0x064B - Enable or Disable TXT
- Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 TxtEnable;
-
-/** Offset 0x064C - Skip Multi-Processor Initialization
- When this is skipped, boot loader must initialize processors before SilicionInit
- API. </b>0: Initialize; <b>1: Skip
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x064D
-**/
- UINT8 UnusedUpdSpace31;
-
-/** Offset 0x064E - FIVR RFI Frequency
- PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
- Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
- 0-1535 (Up to 153.5MHz) for 19MHz clock.
-**/
- UINT16 FivrRfiFrequency;
-
-/** Offset 0x0650 - FIVR RFI Spread Spectrum
- PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
- Range: 0.0% to 10.0% (0-100).
-**/
- UINT8 FivrSpreadSpectrum;
-
-/** Offset 0x0651
-**/
- UINT8 UnusedUpdSpace32[3];
-
-/** Offset 0x0654 - UFS Soft Strap Start Address
- UFS Soft Strap Start Address, Value will be based on the CSE IFWI Layout
-**/
- UINT32 UfsStrapAddress;
-
-/** Offset 0x0658 - CpuBistData
- Pointer CPU BIST Data
-**/
- UINT32 CpuBistData;
-
-/** Offset 0x065C - CpuMpPpi
- <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
- If not NULL, FSP will use the boot loader's implementation of multiprocessing.
- See section 5.1.4 of the FSP Integration Guide for more details.
-**/
- UINT32 CpuMpPpi;
-
-/** Offset 0x0660 - CpuMpHob
- <b>Optional</b> pointer for CpuMpHob. If the boot loader is a UEFI boot loader using
- API mode instead of dispatch mode, and FspsUpd->FspsConfig.CpuMpPpi != NULL, then
- FspsUpd->FspsConfig.CpuMpHob must be != NULL. See section 5.1.4 of the FSP Integration
- Guide for more details.
-**/
- UINT32 CpuMpHob;
-
-/** Offset 0x0664
-**/
- UINT8 CpuPostMemRsvd[16];
-
-/** Offset 0x0674 - PpinSupport to view Protected Processor Inventory Number
- Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
- flag is set) for PPIN Support
- 0: Disable, 1: Enable, 2: Auto
-**/
- UINT8 PpinSupport;
-
-/** Offset 0x0675 - Enable or Disable Minimum Voltage Override
- Enable or disable Minimum Voltage overrides ; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 EnableMinVoltageOverride;
-
-/** Offset 0x0676 - Min Voltage for Runtime
- PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride
- = 1. Range 0 to 1999mV. <b> 0: 0mV </b>
-**/
- UINT16 MinVoltageRuntime;
-
-/** Offset 0x0678 - Base of memory region allocated for Processor Trace
- Base address of memory region allocated for Processor Trace. Processor Trace requires
- 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
-**/
- UINT64 ProcessorTraceMemBase;
-
-/** Offset 0x0680 - Memory region allocation for Processor Trace
- Length in bytes of memory region allocated for Processor Trace. Processor Trace
- requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
-**/
- UINT32 ProcessorTraceMemLength;
-
-/** Offset 0x0684 - Min Voltage for C8
- PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
- 1. Range 0 to 1999mV. <b> 0: 0mV </b>
-**/
- UINT16 MinVoltageC8;
-
-/** Offset 0x0686 - Smbios Type4 Max Speed Override
- Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
- If this value is not zero, it dominates the field.
-**/
- UINT16 SmbiosType4MaxSpeedOverride;
-
-/** Offset 0x0688 - ReservedCpuPostMemProduction
- Reserved for CPU Post-Mem Production
- $EN_DIS
-**/
- UINT8 ReservedCpuPostMemProduction[6];
-
-/** Offset 0x068E - AC Split Lock
- Enable/Disable #AC check on split lock. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 AcSplitLock;
-
-/** Offset 0x068F - PCH Master Clock Gating Control
- Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default
- $EN_DIS
-**/
- UINT8 PchMasterClockGating;
-
-/** Offset 0x0690 - PCH Master Power Gating Control
- Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default
- $EN_DIS
-**/
- UINT8 PchMasterPowerGating;
-
-/** Offset 0x0691 - Sci Pin Mux Enable
- Enable/Disable Sci Gpio Pin Mux. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 SciPinMuxEnable;
-
-/** Offset 0x0692 - Enable Power Optimizer
- Enable DMI Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 PchPwrOptEnable;
-
-/** Offset 0x0693 - PCH Flash Protection Ranges Write Enble
- Write or erase is blocked by hardware.
-**/
- UINT8 PchWriteProtectionEnable[5];
-
-/** Offset 0x0698 - PCH Flash Protection Ranges Read Enble
- Read is blocked by hardware.
-**/
- UINT8 PchReadProtectionEnable[5];
-
-/** Offset 0x069D
-**/
- UINT8 UnusedUpdSpace33[1];
-
-/** Offset 0x069E - PCH Protect Range Limit
- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
- limit comparison.
-**/
- UINT16 PchProtectedRangeLimit[5];
-
-/** Offset 0x06A8 - PCH Protect Range Base
- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
- UINT16 PchProtectedRangeBase[5];
-
-/** Offset 0x06B2 - Enable Pme
- Enable Azalia wake-on-ring.
- $EN_DIS
-**/
- UINT8 PchHdaPme;
-
-/** Offset 0x06B3 - HD Audio Link Frequency
- HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
- 0: 6MHz, 1: 12MHz, 2: 24MHz
-**/
- UINT8 PchHdaLinkFrequency;
-
-/** Offset 0x06B4 - PchPostMemRsvd
- Reserved for PCH Post-Mem
- $EN_DIS
-**/
- UINT8 PchPostMemRsvd4[3];
-
-/** Offset 0x06B7 - Enable PCH Io Apic Entry 24-119
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIoApicEntry24_119;
-
-/** Offset 0x06B8 - PCH Io Apic ID
- This member determines IOAPIC ID. Default is 0x02.
-**/
- UINT8 PchIoApicId;
-
-/** Offset 0x06B9
-**/
- UINT8 UnusedUpdSpace34[3];
-
-/** Offset 0x06BC - PCH PSE Log Output Channel
- Set PSE Log Output Channel. 0: internal memory; 1-6: UART channels; Other: shut down
-**/
- UINT32 PchPseLogOutputChannel;
-
-/** Offset 0x06C0 - PCH PSE Log Output Size
- Set PSE Log Output Size
-**/
- UINT16 PchPseLogOutputSize;
-
-/** Offset 0x06C2 - PCH PSE Log Output Offset
- Set PSE Log Output Offset
-**/
- UINT16 PchPseLogOutputOffset;
-
-/** Offset 0x06C4 - PCH PSE OOB Prov State Offset
- Set PSE OOB Prov State Offset
-**/
- UINT16 PchPseOobProvDone;
-
-/** Offset 0x06C6 - Enable PCH PSE I2S pins assigned
- Set if PSE I2S native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseI2sEnable[2];
-
-/** Offset 0x06C8 - PchPseI2sTxPinMux
- Select PSE I2S Tx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_TXD* for possible values.
-**/
- UINT32 PchPseI2sTxPinMux[2];
-
-/** Offset 0x06D0 - PchPseI2sRxPinMux
- Select PSE I2S Rx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_RXD* for possible values.
-**/
- UINT32 PchPseI2sRxPinMux[2];
-
-/** Offset 0x06D8 - PchPseI2sSfrmPinMux
- Select PSE I2S Sfrm pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SFRM* for possible values.
-**/
- UINT32 PchPseI2sSfrmPinMux[2];
-
-/** Offset 0x06E0 - PchPseI2sSclkPinMux
- Select PSE I2S Sclk pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SCLK* for possible values.
-**/
- UINT32 PchPseI2sSclkPinMux[2];
-
-/** Offset 0x06E8 - Enable PCH PSE PWM pins assigned
- Set if PSE PWM native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPsePwmEnable;
-
-/** Offset 0x06E9 - PchPsePwmPinEnable
- Set PWM pin to PSE PWM native function. 0: Disable; 1: Enable.
-**/
- UINT8 PchPsePwmPinEnable[16];
-
-/** Offset 0x06F9
-**/
- UINT8 UnusedUpdSpace35[3];
-
-/** Offset 0x06FC - PchPsePwmPinMux
- Select PSE Pwm pin muxing start from PWM0 to PWM15. Refer to GPIO_*_MUXING_PSE_PWM*
- for possible values.
-**/
- UINT32 PchPsePwmPinMux[16];
-
-/** Offset 0x073C - Enable PCH PSE UART pins assigned
- Set if PSE UART native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseUartEnable[6];
-
-/** Offset 0x0742 - Enable PCH PSE HSUART pins assigned
- Set if PSE HSUART native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseHsuartEnable[4];
-
-/** Offset 0x0746 - Enable PCH PSE QEP pins assigned
- Set if PSE QEP native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseQepEnable[4];
-
-/** Offset 0x074A - Enable PCH PSE DMA pins assigned
- Set if PSE DMA native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseDmaEnable[3];
-
-/** Offset 0x074D - Enable PCH PSE GBE pins assigned
- Set if PSE GBE native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseGbeEnable[2];
-
-/** Offset 0x074F - Enable PCH PSE I2C pins assigned
- Set if PSE I2C native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseI2cEnable[8];
-
-/** Offset 0x0757 - Enable PCH PSE SPI pins assigned
- Set if PSE SPI native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseSpiEnable[4];
-
-/** Offset 0x075B - Enable PCH PSE SPI CS0 pins assigned
- Set if PSE SPI CS0 pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseSpiCs0Enable[4];
-
-/** Offset 0x075F - Enable PCH PSE SPI CS1 pins assigned
- Set if PSE SPI CS1 pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseSpiCs1Enable[4];
-
-/** Offset 0x0763
-**/
- UINT8 UnusedUpdSpace36[1];
-
-/** Offset 0x0764 - PchPseSpiMosiPinMux
- Select PSE Spi Mosi pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MOSI* for possible values.
-**/
- UINT32 PchPseSpiMosiPinMux[4];
-
-/** Offset 0x0774 - PchPseSpiMisoPinMux
- Select PSE Spi Miso pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MISO* for possible values.
-**/
- UINT32 PchPseSpiMisoPinMux[4];
-
-/** Offset 0x0784 - PchPseSpiClkPinMux
- Select PSE Spi Clk pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_SCLK* for possible values.
-**/
- UINT32 PchPseSpiClkPinMux[4];
-
-/** Offset 0x0794 - PchPseSpiCs0PinMux
- Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values.
-**/
- UINT32 PchPseSpiCs0PinMux[4];
-
-/** Offset 0x07A4 - PchPseSpiCs1PinMux
- Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values.
-**/
- UINT32 PchPseSpiCs1PinMux[4];
-
-/** Offset 0x07B4 - Enable PCH PSE ADC pins assigned
- Set if PSE ADC native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseAdcEnable;
-
-/** Offset 0x07B5 - Enable PCH PSE CAN pins assigned
- Set if PSE CAN native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseCanEnable[2];
-
-/** Offset 0x07B7 - Enable PCH PSE I2S sideband interrupt
- Set if PSE I2S are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseI2sSbInterruptEnable[2];
-
-/** Offset 0x07B9 - Enable PCH PSE PWM sideband interrupt
- Set if PSE PWM are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPsePwmSbInterruptEnable;
-
-/** Offset 0x07BA - Enable PCH PSE UART sideband interrupt
- Set if PSE UART are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseUartSbInterruptEnable[6];
-
-/** Offset 0x07C0 - Enable PCH PSE QEP sideband interrupt
- Set if PSE QEP are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseQepSbInterruptEnable[4];
-
-/** Offset 0x07C4 - Enable PCH PSE DMA sideband interrupt
- Set if PSE DMA are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseDmaSbInterruptEnable[3];
-
-/** Offset 0x07C7 - Enable PCH PSE I2C sideband interrupt
- Set if PSE I2C are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseI2cSbInterruptEnable[8];
-
-/** Offset 0x07CF - Enable PCH PSE SPI sideband interrupt
- Set if PSE SPI are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseSpiSbInterruptEnable[4];
-
-/** Offset 0x07D3 - Enable PCH PSE ADC sideband interrupt
- Set if PSE ADC are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseAdcSbInterruptEnable;
-
-/** Offset 0x07D4 - Enable PCH PSE LH2OSE sideband interrupt
- Set if PSE LH2OSE are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseLh2PseSbInterruptEnable;
-
-/** Offset 0x07D5 - Enable PCH PSE CAN sideband interrupt
- Set if PSE CAN are to be set to sideband interrupt. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseCanSbInterruptEnable[2];
-
-/** Offset 0x07D7 - Enable PCH PSE Timed GPIO pins assigned
- Set if PSE Timed GPIO native pins and ownership are to be enabled by BIOS. 0: Disable/pins
- are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE;
- 2: Pins are muxed to PSE IP, the IO is owned by host;
-**/
- UINT8 PchPseTimedGpioEnable[2];
-
-/** Offset 0x07D9 - Enable PCH PSE Timed GPIO 20 pins allocation
- Allocate 20 pins for PCH PSE Timed GPIO. 0: Top 20 pins; 1: Mid 20 pins; 2: Lower 20 pins.
-**/
- UINT8 PchPseTimedGpioPinAllocation[2];
-
-/** Offset 0x07DB - Enable PCH PSE Timed GPIO Pin to PSE TGPIO native function
- Set TGPIO pin to PSE TGPIO native function. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseTimedGpioPinEnable[60];
-
-/** Offset 0x0817
-**/
- UINT8 UnusedUpdSpace37;
-
-/** Offset 0x0818 - Pch Pse Tgpio6 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio6PinMux;
-
-/** Offset 0x081C - Pch Pse Tgpio7 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio7PinMux;
-
-/** Offset 0x0820 - Pch Pse Tgpio8 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio8PinMux;
-
-/** Offset 0x0824 - Pch Pse Tgpio9 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio9PinMux;
-
-/** Offset 0x0828 - Pch Pse Tgpio10 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio10PinMux;
-
-/** Offset 0x082C - Pch Pse Tgpio11 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio11PinMux;
-
-/** Offset 0x0830 - Pch Pse Tgpio12 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio12PinMux;
-
-/** Offset 0x0834 - Pch Pse Tgpio13 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio13PinMux;
-
-/** Offset 0x0838 - Pch Pse Tgpio14 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio14PinMux;
-
-/** Offset 0x083C - Pch Pse Tgpio15 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio15PinMux;
-
-/** Offset 0x0840 - Pch Pse Tgpio16 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio16PinMux;
-
-/** Offset 0x0844 - Pch Pse Tgpio17 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio17PinMux;
-
-/** Offset 0x0848 - Pch Pse Tgpio18 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio18PinMux;
-
-/** Offset 0x084C - Pch Pse Tgpio19 Pin Mux
- Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values.
-**/
- UINT32 PchPseTgpio19PinMux;
-
-/** Offset 0x0850 - Enable PCH Lan LTR capabilty of PCH internal LAN
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchLanLtrEnable;
-
-/** Offset 0x0851 - Enable LOCKDOWN BIOS LOCK
- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
- protection.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosLock;
-
-/** Offset 0x0852 - PCH Compatibility Revision ID
- This member describes whether or not the CRID feature of PCH should be enabled.
- $EN_DIS
-**/
- UINT8 PchCrid;
-
-/** Offset 0x0853 - RTC BIOS Interface Lock
- Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
- $EN_DIS
-**/
- UINT8 RtcBiosInterfaceLock;
-
-/** Offset 0x0854 - RTC Cmos Memory Lock
- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
- and and lower 128-byte bank of RTC RAM.
- $EN_DIS
-**/
- UINT8 RtcMemoryLock;
-
-/** Offset 0x0855 - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 PcieRpHotPlug[24];
-
-/** Offset 0x086D - Enable PCIE RP Pm Sci
- Indicate whether the root port power manager SCI is enabled.
-**/
- UINT8 PcieRpPmSci[24];
-
-/** Offset 0x0885 - Enable PCIE RP Transmitter Half Swing
- Indicate whether the Transmitter Half Swing is enabled.
-**/
- UINT8 PcieRpTransmitterHalfSwing[24];
-
-/** Offset 0x089D - Enable PCIE RP Clk Req Detect
- Probe CLKREQ# signal before enabling CLKREQ# based power management.
-**/
- UINT8 PcieRpClkReqDetect[24];
-
-/** Offset 0x08B5 - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 PcieRpAdvancedErrorReporting[24];
-
-/** Offset 0x08CD - PCIE RP Unsupported Request Report
- Indicate whether the Unsupported Request Report is enabled.
-**/
- UINT8 PcieRpUnsupportedRequestReport[24];
-
-/** Offset 0x08E5 - PCIE RP Fatal Error Report
- Indicate whether the Fatal Error Report is enabled.
-**/
- UINT8 PcieRpFatalErrorReport[24];
-
-/** Offset 0x08FD - PCIE RP No Fatal Error Report
- Indicate whether the No Fatal Error Report is enabled.
-**/
- UINT8 PcieRpNoFatalErrorReport[24];
-
-/** Offset 0x0915 - PCIE RP Correctable Error Report
- Indicate whether the Correctable Error Report is enabled.
-**/
- UINT8 PcieRpCorrectableErrorReport[24];
-
-/** Offset 0x092D - PCIE RP System Error On Fatal Error
- Indicate whether the System Error on Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnFatalError[24];
-
-/** Offset 0x0945 - PCIE RP System Error On Non Fatal Error
- Indicate whether the System Error on Non Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnNonFatalError[24];
-
-/** Offset 0x095D - PCIE RP System Error On Correctable Error
- Indicate whether the System Error on Correctable Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnCorrectableError[24];
-
-/** Offset 0x0975 - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 PcieRpMaxPayload[24];
-
-/** Offset 0x098D - Touch Host Controller Port 0 Assignment
- Assign THC Port 0
- 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
-**/
- UINT8 ThcPort0Assignment;
-
-/** Offset 0x098E
-**/
- UINT8 UnusedUpdSpace38[2];
-
-/** Offset 0x0990 - THC Port 0 Interrupt Pin Mux
- Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer
- to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
-**/
- UINT32 ThcPort0InterruptPinMuxing;
-
-/** Offset 0x0994 - Touch Host Controller Port 1 Assignment
- Assign THC Port 1
- 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
-**/
- UINT8 ThcPort1Assignment;
-
-/** Offset 0x0995 - Touch Host Controller Port 1 ReadFrequency
- Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
- 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
-**/
- UINT8 ThcPort1ReadFrequency;
-
-/** Offset 0x0996 - Touch Host Controller Port 1 WriteFrequency
- Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
- 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz
-**/
- UINT8 ThcPort1WriteFrequency;
-
-/** Offset 0x0997
-**/
- UINT8 UnusedUpdSpace39;
-
-/** Offset 0x0998 - THC Port 1 Interrupt Pin Mux
- Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
- to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values.
-**/
- UINT32 ThcPort1InterruptPinMuxing;
-
-/** Offset 0x099C - PCIE RP Pcie Speed
- Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
- PCH_PCIE_SPEED).
-**/
- UINT8 PcieRpPcieSpeed[24];
-
-/** Offset 0x09B4 - PCIE RP Physical Slot Number
- Indicates the slot number for the root port. Default is the value as root port index.
-**/
- UINT8 PcieRpPhysicalSlotNumber[24];
-
-/** Offset 0x09CC - PCIE RP Completion Timeout
- The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
-**/
- UINT8 PcieRpCompletionTimeout[24];
-
-/** Offset 0x09E4 - PCIE RP Aspm
- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
- PchPcieAspmAutoConfig.
-**/
- UINT8 PcieRpAspm[24];
-
-/** Offset 0x09FC - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
- Default is PchPcieL1SubstatesL1_1_2.
-**/
- UINT8 PcieRpL1Substates[24];
-
-/** Offset 0x0A14 - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 PcieRpLtrEnable[24];
-
-/** Offset 0x0A2C - PCIE RP Ltr Config Lock
- 0: Disable; 1: Enable.
-**/
- UINT8 PcieRpLtrConfigLock[24];
-
-/** Offset 0x0A44 - PCIe override default settings for EQ
- Choose PCIe EQ method
- $EN_DIS
-**/
- UINT8 PcieEqOverrideDefault;
-
-/** Offset 0x0A45 - PCIe choose EQ method
- Choose PCIe EQ method
- 0: HardwareEq, 1: FixedEq
-**/
- UINT8 PcieEqMethod;
-
-/** Offset 0x0A46 - PCIe choose EQ mode
- Choose PCIe EQ mode
- 0: PresetEq, 1: CoefficientEq
-**/
- UINT8 PcieEqMode;
-
-/** Offset 0x0A47 - PCIe EQ local transmitter override
- Enable/Disable local transmitter override
- $EN_DIS
-**/
- UINT8 PcieEqLocalTransmitterOverrideEnable;
-
-/** Offset 0x0A48 - PCIe number of valid list entries
- Select number of presets or coefficients depending on the mode
-**/
- UINT8 PcieEqPh3NumberOfPresetsOrCoefficients;
-
-/** Offset 0x0A49 - PCIe pre-cursor coefficient list
- Provide a list of pre-cursor coefficients to be used during phase 3 EQ
-**/
- UINT8 PcieEqPh3PreCursorList[10];
-
-/** Offset 0x0A53 - PCIe post-cursor coefficient list
- Provide a list of post-cursor coefficients to be used during phase 3 EQ
-**/
- UINT8 PcieEqPh3PostCursorList[10];
-
-/** Offset 0x0A5D - PCIe preset list
- Provide a list of presets to be used during phase 3 EQ
-**/
- UINT8 PcieEqPh3PresetList[11];
-
-/** Offset 0x0A68 - PCIe EQ phase 1 downstream transmitter port preset
- Allows to select the downstream port preset value that will be used during phase
- 1 of equalization
-**/
- UINT32 PcieEqPh1DownstreamPortTransmitterPreset;
-
-/** Offset 0x0A6C - PCIe EQ phase 1 upstream tranmitter port preset
- Allows to select the upstream port preset value that will be used during phase 1
- of equalization
-**/
- UINT32 PcieEqPh1UpstreamPortTransmitterPreset;
-
-/** Offset 0x0A70 - PCIe EQ phase 2 local transmitter override preset
- Allows to select the value of the preset used during phase 2 local transmitter override
-**/
- UINT8 PcieEqPh2LocalTransmitterOverridePreset;
-
-/** Offset 0x0A71 - PCIE Enable Peer Memory Write
- This member describes whether Peer Memory Writes are enabled on the platform.
- $EN_DIS
-**/
- UINT8 PcieEnablePeerMemoryWrite;
-
-/** Offset 0x0A72 - PCIE Compliance Test Mode
- Compliance Test Mode shall be enabled when using Compliance Load Board.
- $EN_DIS
-**/
- UINT8 PcieComplianceTestMode;
-
-/** Offset 0x0A73 - PCI Express Clock Gating
- Enable/Disable Clock Gating, 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
- 0: POR, 1: Force Enable, 2: Force Disable
-**/
- UINT8 TestPcieClockGating;
-
-/** Offset 0x0A74 - PCIE Rp Function Swap
- Allows BIOS to use root port function number swapping when root port of function
- 0 is disabled.
- $EN_DIS
-**/
- UINT8 PcieRpFunctionSwap;
-
-/** Offset 0x0A75 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
- Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
- Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 CpuPcieGen3ProgramStaticEq;
-
-/** Offset 0x0A76 - Enable/Disable GEN4 Static EQ Phase1 programming
- Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets
- Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 CpuPcieGen4ProgramStaticEq;
-
-/** Offset 0x0A77 - PCH Pm PME_B0_S5_DIS
- When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
- $EN_DIS
-**/
- UINT8 PchPmPmeB0S5Dis;
-
-/** Offset 0x0A78 - PCIE IMR
- Enables Isolated Memory Region for PCIe.
- $EN_DIS
-**/
- UINT8 PcieRpImrEnabled;
-
-/** Offset 0x0A79 - PCIE IMR port number
- Selects PCIE root port number for IMR feature.
-**/
- UINT8 PcieRpImrSelection;
-
-/** Offset 0x0A7A - PCH Pm Wol Enable Override
- Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
- $EN_DIS
-**/
- UINT8 PchPmWolEnableOverride;
-
-/** Offset 0x0A7B - PCH Pm Pcie Wake From DeepSx
- Determine if enable PCIe to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmPcieWakeFromDeepSx;
-
-/** Offset 0x0A7C - PCH Pm WoW lan Enable
- Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanEnable;
-
-/** Offset 0x0A7D - PCH Pm WoW lan DeepSx Enable
- Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
- PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanDeepSxEnable;
-
-/** Offset 0x0A7E - PCH Pm Lan Wake From DeepSx
- Determine if enable LAN to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmLanWakeFromDeepSx;
-
-/** Offset 0x0A7F - PCH Pm Deep Sx Pol
- Deep Sx Policy.
- $EN_DIS
-**/
- UINT8 PchPmDeepSxPol;
-
-/** Offset 0x0A80 - PCH Pm Slp S3 Min Assert
- SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
-**/
- UINT8 PchPmSlpS3MinAssert;
-
-/** Offset 0x0A81 - PCH Pm Slp S4 Min Assert
- SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
-**/
- UINT8 PchPmSlpS4MinAssert;
-
-/** Offset 0x0A82 - PCH Pm Slp Sus Min Assert
- SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
-**/
- UINT8 PchPmSlpSusMinAssert;
-
-/** Offset 0x0A83 - PCH Pm Slp A Min Assert
- SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
-**/
- UINT8 PchPmSlpAMinAssert;
-
-/** Offset 0x0A84 - USB Overcurrent Override for DbC
- This option overrides USB Over Current enablement state that USB OC will be disabled
- after enabling this option. Enable when DbC is used to avoid signaling conflicts.
- $EN_DIS
-**/
- UINT8 PchEnableDbcObs;
-
-/** Offset 0x0A85 - PCH Pm Slp Strch Sus Up
- Enable SLP_X Stretching After SUS Well Power Up.
- $EN_DIS
-**/
- UINT8 PchPmSlpStrchSusUp;
-
-/** Offset 0x0A86 - PCH Pm Slp Lan Low Dc
- Enable/Disable SLP_LAN# Low on DC Power.
- $EN_DIS
-**/
- UINT8 PchPmSlpLanLowDc;
-
-/** Offset 0x0A87 - PCH Pm Pwr Btn Override Period
- PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
-**/
- UINT8 PchPmPwrBtnOverridePeriod;
-
-/** Offset 0x0A88 - PCH Pm Disable Dsx Ac Present Pulldown
- When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
- $EN_DIS
-**/
- UINT8 PchPmDisableDsxAcPresentPulldown;
-
-/** Offset 0x0A89 - PCH Pm Disable Native Power Button
- Power button native mode disable.
- $EN_DIS
-**/
- UINT8 PchPmDisableNativePowerButton;
-
-/** Offset 0x0A8A - PCH Pm ME_WAKE_STS
- Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmMeWakeSts;
-
-/** Offset 0x0A8B - PCH Pm WOL_OVR_WK_STS
- Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmWolOvrWkSts;
-
-/** Offset 0x0A8C - PCH Pm Reset Power Cycle Duration
- Could be customized in the unit of second. Please refer to EDS for all support settings.
- 0 is default, 1 is 1 second, 2 is 2 seconds, ...
-**/
- UINT8 PchPmPwrCycDur;
-
-/** Offset 0x0A8D - PCH Pm Pcie Pll Ssc
- Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
- BIOS override.
-**/
- UINT8 PchPmPciePllSsc;
-
-/** Offset 0x0A8E - PCH Legacy IO Low Latency Enable
- Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
- $EN_DIS
-**/
- UINT8 PchLegacyIoLowLatency;
-
-/** Offset 0x0A8F - PCH Sata Pwr Opt Enable
- SATA Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x0A90 - PCH Sata eSATA Speed Limit
- When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
- $EN_DIS
-**/
- UINT8 EsataSpeedLimit;
-
-/** Offset 0x0A91 - PCH Sata Speed Limit
- Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
-**/
- UINT8 SataSpeedLimit;
-
-/** Offset 0x0A92 - Enable SATA Port HotPlug
- Enable SATA Port HotPlug.
-**/
- UINT8 SataPortsHotPlug[8];
-
-/** Offset 0x0A9A - Enable SATA Port Interlock Sw
- Enable SATA Port Interlock Sw.
-**/
- UINT8 SataPortsInterlockSw[8];
-
-/** Offset 0x0AA2 - Enable SATA Port External
- Enable SATA Port External.
-**/
- UINT8 SataPortsExternal[8];
-
-/** Offset 0x0AAA - Enable SATA Port SpinUp
- Enable the COMRESET initialization Sequence to the device.
-**/
- UINT8 SataPortsSpinUp[8];
-
-/** Offset 0x0AB2 - Enable SATA Port Solid State Drive
- 0: HDD; 1: SSD.
-**/
- UINT8 SataPortsSolidStateDrive[8];
-
-/** Offset 0x0ABA - Enable SATA Port Enable Dito Config
- Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
-**/
- UINT8 SataPortsEnableDitoConfig[8];
-
-/** Offset 0x0AC2 - Enable SATA Port DmVal
- DITO multiplier. Default is 15.
-**/
- UINT8 SataPortsDmVal[8];
-
-/** Offset 0x0ACA - Enable SATA Port DmVal
- DEVSLP Idle Timeout (DITO), Default is 625.
-**/
- UINT16 SataPortsDitoVal[8];
-
-/** Offset 0x0ADA - Enable SATA Port ZpOdd
- Support zero power ODD.
-**/
- UINT8 SataPortsZpOdd[8];
-
-/** Offset 0x0AE2 - Enable SATA Port RxPolarity
- Reverse RxPolarity.
-**/
- UINT8 SataPortsRxPolarity[8];
-
-/** Offset 0x0AEA - PCH Sata Rst Raid Alternate Id
- Enable RAID Alternate ID.
- $EN_DIS
-**/
- UINT8 SataRstRaidDeviceId;
-
-/** Offset 0x0AEB - PCH Sata Rst Raid0
- RAID0.
- $EN_DIS
-**/
- UINT8 SataRstRaid0;
-
-/** Offset 0x0AEC - PCH Sata Rst Raid1
- RAID1.
- $EN_DIS
-**/
- UINT8 SataRstRaid1;
-
-/** Offset 0x0AED - PCH Sata Rst Raid10
- RAID10.
- $EN_DIS
-**/
- UINT8 SataRstRaid10;
-
-/** Offset 0x0AEE - PCH Sata Rst Raid5
- RAID5.
- $EN_DIS
-**/
- UINT8 SataRstRaid5;
-
-/** Offset 0x0AEF - PCH Sata Rst Irrt
- Intel Rapid Recovery Technology.
- $EN_DIS
-**/
- UINT8 SataRstIrrt;
-
-/** Offset 0x0AF0 - PCH Sata Rst Orom Ui Banner
- OROM UI and BANNER.
- $EN_DIS
-**/
- UINT8 SataRstOromUiBanner;
-
-/** Offset 0x0AF1 - PCH Sata Rst Orom Ui Delay
- 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
-**/
- UINT8 SataRstOromUiDelay;
-
-/** Offset 0x0AF2 - PCH Sata Rst Hdd Unlock
- Indicates that the HDD password unlock in the OS is enabled.
- $EN_DIS
-**/
- UINT8 SataRstHddUnlock;
-
-/** Offset 0x0AF3 - PCH Sata Rst Led Locate
- Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
- enabled on the OS.
- $EN_DIS
-**/
- UINT8 SataRstLedLocate;
-
-/** Offset 0x0AF4 - PCH Sata Rst Irrt Only
- Allow only IRRT drives to span internal and external ports.
- $EN_DIS
-**/
- UINT8 SataRstIrrtOnly;
-
-/** Offset 0x0AF5 - PCH Sata Rst Smart Storage
- RST Smart Storage caching Bit.
- $EN_DIS
-**/
- UINT8 SataRstSmartStorage;
-
-/** Offset 0x0AF6 - PCH Sata Rst Pcie Storage Remap enable
- Enable Intel RST for PCIe Storage remapping.
-**/
- UINT8 SataRstPcieEnable[3];
-
-/** Offset 0x0AF9 - PCH Sata Rst Pcie Storage Port
- Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
-**/
- UINT8 SataRstPcieStoragePort[3];
-
-/** Offset 0x0AFC - PCH Sata Rst Pcie Device Reset Delay
- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
-**/
- UINT8 SataRstPcieDeviceResetDelay[3];
-
-/** Offset 0x0AFF - UFS enable/disable
- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
- $EN_DIS
-**/
- UINT8 UfsEnable[2];
-
-/** Offset 0x0B01 - IEH Mode
- Integrated Error Handler Mode, 0: Bypass, 1: Enable
- 0: Bypass, 1:Enable
-**/
- UINT8 IehMode;
-
-/** Offset 0x0B02 - PSF Tcc
- Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency
- by disable some psf power management features, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 PsfTccEnable;
-
-/** Offset 0x0B03 - TCC Mode Default Flag
- Variable to determine TCC mode default value, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 TccModeInitFlag;
-
-/** Offset 0x0B04 - Tcc Tuning enable/disable
- Tcc (Time Coordinated Computing) Tuning Enabled
- $EN_DIS
-**/
- UINT8 TccTuningEnable;
-
-/** Offset 0x0B05
-**/
- UINT8 UnusedUpdSpace40[3];
-
-/** Offset 0x0B08 - Tcc Register File Base Address
- Tcc (Time Coordinated Computing) Register File Base Address
-**/
- UINT32 TccConfigBase;
-
-/** Offset 0x0B0C - Tcc Register File Size
- Tcc (Time Coordinated Computing) Register File Size
-**/
- UINT32 TccConfigSize;
-
-/** Offset 0x0B10 - Fusa Display Configuration
- Fusa (Functional Safety) Enable Fusa Feature on Display, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 DisplayFusaConfigEnable;
-
-/** Offset 0x0B11 - Fusa Graphics Configuration
- Fusa (Functional Safety) Enable Fusa Feature on Graphics, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 GraphicFusaConfigEnable;
-
-/** Offset 0x0B12 - Fusa Opio Configuration
- Fusa (Functional Safety) Enable Fusa Feature on Opio, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 OpioFusaConfigEnable;
-
-/** Offset 0x0B13 - Fusa Psf Configuration
- Fusa (Functional Safety) Enable Fusa Feature on Psf, 0: Disable, 1: Enable
- $EN_DIS
-**/
- UINT8 PsfFusaConfigEnable;
-
-/** Offset 0x0B14 - Thermal Throttling Custimized T0Level Value
- Custimized T0Level value.
-**/
- UINT16 PchT0Level;
-
-/** Offset 0x0B16 - Thermal Throttling Custimized T1Level Value
- Custimized T1Level value.
-**/
- UINT16 PchT1Level;
-
-/** Offset 0x0B18 - Thermal Throttling Custimized T2Level Value
- Custimized T2Level value.
-**/
- UINT16 PchT2Level;
-
-/** Offset 0x0B1A - Enable The Thermal Throttle
- Enable the thermal throttle function.
- $EN_DIS
-**/
- UINT8 PchTTEnable;
-
-/** Offset 0x0B1B - PMSync State 13
- When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
- at least T2 state.
- $EN_DIS
-**/
- UINT8 PchTTState13Enable;
-
-/** Offset 0x0B1C - Thermal Throttle Lock
- Thermal Throttle Lock.
- $EN_DIS
-**/
- UINT8 PchTTLock;
-
-/** Offset 0x0B1D - Thermal Throttling Suggested Setting
- Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 TTSuggestedSetting;
-
-/** Offset 0x0B1E - Enable PCH Cross Throttling
- Enable/Disable PCH Cross Throttling
- $EN_DIS
-**/
- UINT8 TTCrossThrottling;
-
-/** Offset 0x0B1F - DMI Thermal Sensor Autonomous Width Enable
- DMI Thermal Sensor Autonomous Width Enable.
- $EN_DIS
-**/
- UINT8 PchDmiTsawEn;
-
-/** Offset 0x0B20 - DMI Thermal Sensor Suggested Setting
- DMT thermal sensor suggested representative values.
- $EN_DIS
-**/
- UINT8 DmiSuggestedSetting;
-
-/** Offset 0x0B21 - Thermal Sensor 0 Target Width
- Thermal Sensor 0 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS0TW;
-
-/** Offset 0x0B22 - Thermal Sensor 1 Target Width
- Thermal Sensor 1 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS1TW;
-
-/** Offset 0x0B23 - Thermal Sensor 2 Target Width
- Thermal Sensor 2 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS2TW;
-
-/** Offset 0x0B24 - Thermal Sensor 3 Target Width
- Thermal Sensor 3 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS3TW;
-
-/** Offset 0x0B25 - Port 0 T1 Multipler
- Port 0 T1 Multipler.
-**/
- UINT8 SataP0T1M;
-
-/** Offset 0x0B26 - Port 0 T2 Multipler
- Port 0 T2 Multipler.
-**/
- UINT8 SataP0T2M;
-
-/** Offset 0x0B27 - Port 0 T3 Multipler
- Port 0 T3 Multipler.
-**/
- UINT8 SataP0T3M;
-
-/** Offset 0x0B28 - Port 0 Tdispatch
- Port 0 Tdispatch.
-**/
- UINT8 SataP0TDisp;
-
-/** Offset 0x0B29 - Port 1 T1 Multipler
- Port 1 T1 Multipler.
-**/
- UINT8 SataP1T1M;
-
-/** Offset 0x0B2A - Port 1 T2 Multipler
- Port 1 T2 Multipler.
-**/
- UINT8 SataP1T2M;
-
-/** Offset 0x0B2B - Port 1 T3 Multipler
- Port 1 T3 Multipler.
-**/
- UINT8 SataP1T3M;
-
-/** Offset 0x0B2C - Port 1 Tdispatch
- Port 1 Tdispatch.
-**/
- UINT8 SataP1TDisp;
-
-/** Offset 0x0B2D - Port 0 Tinactive
- Port 0 Tinactive.
-**/
- UINT8 SataP0Tinact;
-
-/** Offset 0x0B2E - Port 0 Alternate Fast Init Tdispatch
- Port 0 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP0TDispFinit;
-
-/** Offset 0x0B2F - Port 1 Tinactive
- Port 1 Tinactive.
-**/
- UINT8 SataP1Tinact;
-
-/** Offset 0x0B30 - Port 1 Alternate Fast Init Tdispatch
- Port 1 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP1TDispFinit;
-
-/** Offset 0x0B31 - Sata Thermal Throttling Suggested Setting
- Sata Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 SataThermalSuggestedSetting;
-
-/** Offset 0x0B32 - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
- $EN_DIS
-**/
- UINT8 PchMemoryThrottlingEnable;
-
-/** Offset 0x0B33 - Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPmsyncEnable[2];
-
-/** Offset 0x0B35 - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryC0TransmitEnable[2];
-
-/** Offset 0x0B37 - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPinSelection[2];
-
-/** Offset 0x0B39
-**/
- UINT8 UnusedUpdSpace41;
-
-/** Offset 0x0B3A - Thermal Device Temperature
- Decides the temperature.
-**/
- UINT16 PchTemperatureHotLevel;
-
-/** Offset 0x0B3C - Enable xHCI Compliance Mode
- Compliance Mode can be enabled for testing through this option but this is disabled
- by default.
- $EN_DIS
-**/
- UINT8 PchEnableComplianceMode;
-
-/** Offset 0x0B3D - USB2 Port Over Current Pin
- Describe the specific over current pin number of USB 2.0 Port N.
-**/
- UINT8 Usb2OverCurrentPin[16];
-
-/** Offset 0x0B4D - USB3 Port Over Current Pin
- Describe the specific over current pin number of USB 3.0 Port N.
-**/
- UINT8 Usb3OverCurrentPin[10];
-
-/** Offset 0x0B57 - Enable xHCI LTR override
- Enables override of recommended LTR values for xHCI
- $EN_DIS
-**/
- UINT8 PchUsbLtrOverrideEnable;
-
-/** Offset 0x0B58 - USB Clock Gating Enable
- Enable or disable USB clock gating
- $EN_DIS
-**/
- UINT8 UsbClockGatingEnable;
-
-/** Offset 0x0B59 - USB Power Gating Enable
- Enable or disable USB power gating
- $EN_DIS
-**/
- UINT8 UsbPowerGatingEnable;
-
-/** Offset 0x0B5A - USB3 LINK SPEED
- Set USB3 LINK SPEED=0 for GEN2, Set USB3 LINK SPEED=1 for GEN1
-**/
- UINT8 USB3LinkSpeed;
-
-/** Offset 0x0B5B
-**/
- UINT8 UnusedUpdSpace42;
-
-/** Offset 0x0B5C - xHCI High Idle Time LTR override
- Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
-**/
- UINT32 PchUsbLtrHighIdleTimeOverride;
-
-/** Offset 0x0B60 - xHCI Medium Idle Time LTR override
- Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
-**/
- UINT32 PchUsbLtrMediumIdleTimeOverride;
-
-/** Offset 0x0B64 - xHCI Low Idle Time LTR override
- Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
-**/
- UINT32 PchUsbLtrLowIdleTimeOverride;
-
-/** Offset 0x0B68 - Enable 8254 Static Clock Gating
- Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
- might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
- legacy OS using 8254 timer. Also enable this while S0ix is enabled.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGating;
-
-/** Offset 0x0B69 - Enable 8254 Static Clock Gating On S3
- This is only applicable when Enable8254ClockGating is disabled. FSP will do the
- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
- avoids the SMI requirement for the programming.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGatingOnS3;
-
-/** Offset 0x0B6A - PCH Sata Rst Optane Memory
- Optane Memory
- $EN_DIS
-**/
- UINT8 SataRstOptaneMemory;
-
-/** Offset 0x0B6B - PCH Sata Rst CPU Attached Storage
- CPU Attached Storage
- $EN_DIS
-**/
- UINT8 SataRstCpuAttachedStorage;
-
-/** Offset 0x0B6C - Enable TCO timer.
- When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
- huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
- emulation must be enabled, and WDAT table must not be exposed to the OS.
- $EN_DIS
-**/
- UINT8 EnableTcoTimer;
-
-/** Offset 0x0B6D - Enable Timed GPIO 0.
- When FALSE, it disables Timed GPIO 0.
- $EN_DIS
-**/
- UINT8 EnableTimedGpio0;
-
-/** Offset 0x0B6E - Enable Timed GPIO 1.
- When FALSE, it disables Timed GPIO 1.
- $EN_DIS
-**/
- UINT8 EnableTimedGpio1;
-
-/** Offset 0x0B6F - Enable VNN Voltage Raise.
- When TRUE, it enable VNN Voltage Raise.
- $EN_DIS
-**/
- UINT8 EnableVnnVoltageRaise;
-
-/** Offset 0x0B70 - BgpdtHash[4]
- BgpdtHash values
-**/
- UINT64 BgpdtHash[4];
-
-/** Offset 0x0B90 - BiosGuardAttr
- BiosGuardAttr default values
-**/
- UINT32 BiosGuardAttr;
-
-/** Offset 0x0B94
-**/
- UINT8 UnusedUpdSpace43[4];
-
-/** Offset 0x0B98 - BiosGuardModulePtr
- BiosGuardModulePtr default values
-**/
- UINT64 BiosGuardModulePtr;
-
-/** Offset 0x0BA0 - SendEcCmd
- SendEcCmd function pointer. \n
- @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
- EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
-**/
- UINT64 SendEcCmd;
-
-/** Offset 0x0BA8 - EcCmdProvisionEav
- Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
-**/
- UINT8 EcCmdProvisionEav;
-
-/** Offset 0x0BA9 - EcCmdLock
- EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
-**/
- UINT8 EcCmdLock;
-
-/** Offset 0x0BAA - Si Config CSM Flag.
- Platform specific common policies that used by several silicon components. CSM status flag.
- $EN_DIS
-**/
- UINT8 SiCsmFlag;
-
-/** Offset 0x0BAB - Skip Ssid Programming.
- When set to TRUE, silicon code will not do any SSID programming and platform code
- needs to handle that by itself properly.
- $EN_DIS
-**/
- UINT8 SiSkipSsidProgramming;
-
-/** Offset 0x0BAC - Change Default SVID
- Change the default SVID used in FSP to programming internal devices. This is only
- valid when SkipSsidProgramming is FALSE.
-**/
- UINT16 SiCustomizedSvid;
-
-/** Offset 0x0BAE - Change Default SSID
- Change the default SSID used in FSP to programming internal devices. This is only
- valid when SkipSsidProgramming is FALSE.
-**/
- UINT16 SiCustomizedSsid;
-
-/** Offset 0x0BB0 - SVID SDID table Poniter.
- The address of the table of SVID SDID to customize each SVID SDID entry. This is
- only valid when SkipSsidProgramming is FALSE.
-**/
- UINT32 SiSsidTablePtr;
-
-/** Offset 0x0BB4 - Number of ssid table.
- SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
- This is only valid when SkipSsidProgramming is FALSE.
-**/
- UINT16 SiNumberOfSsidTableEntry;
-
-/** Offset 0x0BB6
-**/
- UINT8 SiPostMemRsvd[16];
-
-/** Offset 0x0BC6 - SATA RST Interrupt Mode
- Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
- 0:Msix, 1:Msi, 2:Legacy
-**/
- UINT8 SataRstInterrupt;
-
-/** Offset 0x0BC7 - ME Unconfig on RTC clear
- 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
- 2: Cmos is clear, status unkonwn. 3: Reserved
- 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
- is clear, 3: Reserved
-**/
- UINT8 MeUnconfigOnRtcClear;
-
-/** Offset 0x0BC8 - Enable PS_ON.
- PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
- target that will be required by the California Energy Commission (CEC). When FALSE,
- PS_ON is to be disabled.
- $EN_DIS
-**/
- UINT8 PsOnEnable;
-
-/** Offset 0x0BC9 - Pmc Cpu C10 Gate Pin Enable
- Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
- and VccSTG rails instead of SLP_S0# pin.
- $EN_DIS
-**/
- UINT8 PmcCpuC10GatePinEnable;
-
-/** Offset 0x0BCA - Pch Dmi Aspm Ctrl
- ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
- 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
-**/
- UINT8 PchDmiAspmCtrl;
-
-/** Offset 0x0BCB - PchDmiCwbEnable
- Central Write Buffer feature configurable and disabled by default
- $EN_DIS
-**/
- UINT8 PchDmiCwbEnable;
-
-/** Offset 0x0BCC - OS IDLE Mode Enable
- Enable/Disable OS Idle Mode
- $EN_DIS
-**/
- UINT8 PmcOsIdleEnable;
-
-/** Offset 0x0BCD - S0ix Auto-Demotion
- Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
- $EN_DIS
-**/
- UINT8 PchS0ixAutoDemotion;
-
-/** Offset 0x0BCE - Global Reset TSC Enable
- Enable/Disable PMC Global Reset Three Strike Counter feature. If enabled, PMC will
- keep the platform in S5 after the third consecutive type 7 global reset occurs
- during boot flow
- $EN_DIS
-**/
- UINT8 PmcGrTscEnable;
-
-/** Offset 0x0BCF - Latch Events C10 Exit
- When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
- captured on C10 exit (instead of C10 entry which is default)
- $EN_DIS
-**/
- UINT8 PchPmLatchEventsC10Exit;
-
-/** Offset 0x0BD0 - PCIE Eq Ph3 Lane Param Cm
- CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
-**/
- UINT8 CpuPcieEqPh3LaneParamCm[32];
-
-/** Offset 0x0BF0 - PCIE Eq Ph3 Lane Param Cp
- CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1.
-**/
- UINT8 CpuPcieEqPh3LaneParamCp[32];
-
-/** Offset 0x0C10 - PCIE Hw Eq Gen3 CoeffList Cm
- CPU_PCIE_EQ_PARAM. Coefficient C-1.
-**/
- UINT8 CpuPcieHwEqGen3CoeffListCm[5];
-
-/** Offset 0x0C15 - PCIE Hw Eq Gen3 CoeffList Cp
- CPU_PCIE_EQ_PARAM. Coefficient C+1.
-**/
- UINT8 CpuPcieHwEqGen3CoeffListCp[5];
-
-/** Offset 0x0C1A - PCIE Hw Eq Gen4 CoeffList Cm
- CPU_PCIE_EQ_PARAM. Coefficient C-1.
-**/
- UINT8 CpuPcieHwEqGen4CoeffListCm[5];
-
-/** Offset 0x0C1F - PCIE Hw Eq Gen4 CoeffList Cp
- CPU_PCIE_EQ_PARAM. Coefficient C+1.
-**/
- UINT8 CpuPcieHwEqGen4CoeffListCp[5];
-
-/** Offset 0x0C24 - Gen3 Root port preset values per lane
- Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default
- for each lane
-**/
- UINT8 CpuPcieGen3RootPortPreset[20];
-
-/** Offset 0x0C38 - Pcie Gen4 Root port preset values per lane
- Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default
- for each lane
-**/
- UINT8 CpuPcieGen4RootPortPreset[20];
-
-/** Offset 0x0C4C - Pcie Gen3 End port preset values per lane
- Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default
- for each lane
-**/
- UINT8 CpuPcieGen3EndPointPreset[20];
-
-/** Offset 0x0C60 - Pcie Gen4 End port preset values per lane
- Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default
- for each lane
-**/
- UINT8 CpuPcieGen4EndPointPreset[20];
-
-/** Offset 0x0C74 - Pcie Gen3 End port Hint values per lane
- Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 CpuPcieGen3EndPointHint[20];
-
-/** Offset 0x0C88 - Pcie Gen4 End port Hint values per lane
- Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 CpuPcieGen4EndPointHint[20];
-
-/** Offset 0x0C9C - Skip Cpu Fia Programming
- Skip Fia configuration and lock if enable. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 CpuPcieSkipCpuFiaProgramming;
-
-/** Offset 0x0C9D - PCIE Disable RootPort Clock Gating
- Describes whether the PCI Express Clock Gating for each root port is enabled by
- platform modules. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 CpuPcieDisableRootPortClockGating;
-
-/** Offset 0x0C9E - PCIE Disable RootPort Power Gating
- Describes whether the PCI Express Power Gating for each root port is enabled by
- platform modules. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 CpuPcieDisableRootPortPowerGating;
-
-/** Offset 0x0C9F - PCIE Compliance Test Mode
- Compliance Test Mode shall be enabled when using Compliance Load Board.
- $EN_DIS
-**/
- UINT8 CpuPcieComplianceTestMode;
-
-/** Offset 0x0CA0 - PCIE Secure Register Lock
- Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
- load CpuPcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
- $EN_DIS
-**/
- UINT8 CpuPcieSetSecuredRegisterLock;
-
-/** Offset 0x0CA1 - PCIE Enable Peer Memory Write
- This member describes whether Peer Memory Writes are enabled on the platform.
- $EN_DIS
-**/
- UINT8 CpuPcieEnablePeerMemoryWrite;
-
-/** Offset 0x0CA2 - PCIE Rp Function Swap
- Allows BIOS to use root port function number swapping when root port of function
- 0 is disabled.
- $EN_DIS
-**/
- UINT8 CpuPcieRpFunctionSwap;
-
-/** Offset 0x0CA3
-**/
- UINT8 UnusedUpdSpace44;
-
-/** Offset 0x0CA4 - Pch PCIE device override table pointer
- The PCIe device table is being used to override PCIe device ASPM settings. This
- is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
- refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
- must be 0.
-**/
- UINT32 CpuPcieDeviceOverrideTablePtr;
-
-/** Offset 0x0CA8 - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 CpuPcieRpHotPlug[4];
-
-/** Offset 0x0CAC - Enable PCIE RP Pm Sci
- Indicate whether the root port power manager SCI is enabled.
-**/
- UINT8 CpuPcieRpPmSci[4];
-
-/** Offset 0x0CB0 - Enable PCIE RP Transmitter Half Swing
- Indicate whether the Transmitter Half Swing is enabled.
-**/
- UINT8 CpuPcieRpTransmitterHalfSwing[4];
-
-/** Offset 0x0CB4 - PCIE RP Access Control Services Extended Capability
- Enable/Disable PCIE RP Access Control Services Extended Capability
-**/
- UINT8 CpuPcieRpAcsEnabled[4];
-
-/** Offset 0x0CB8 - PCIE RP Clock Power Management
- Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
- can still be controlled by L1 PM substates mechanism
-**/
- UINT8 CpuPcieRpEnableCpm[4];
-
-/** Offset 0x0CBC - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 CpuPcieRpAdvancedErrorReporting[4];
-
-/** Offset 0x0CC0 - PCIE RP Unsupported Request Report
- Indicate whether the Unsupported Request Report is enabled.
-**/
- UINT8 CpuPcieRpUnsupportedRequestReport[4];
-
-/** Offset 0x0CC4 - PCIE RP Fatal Error Report
- Indicate whether the Fatal Error Report is enabled.
-**/
- UINT8 CpuPcieRpFatalErrorReport[4];
-
-/** Offset 0x0CC8 - PCIE RP No Fatal Error Report
- Indicate whether the No Fatal Error Report is enabled.
-**/
- UINT8 CpuPcieRpNoFatalErrorReport[4];
-
-/** Offset 0x0CCC - PCIE RP Correctable Error Report
- Indicate whether the Correctable Error Report is enabled.
-**/
- UINT8 CpuPcieRpCorrectableErrorReport[4];
-
-/** Offset 0x0CD0 - PCIE RP System Error On Fatal Error
- Indicate whether the System Error on Fatal Error is enabled.
-**/
- UINT8 CpuPcieRpSystemErrorOnFatalError[4];
-
-/** Offset 0x0CD4 - PCIE RP System Error On Non Fatal Error
- Indicate whether the System Error on Non Fatal Error is enabled.
-**/
- UINT8 CpuPcieRpSystemErrorOnNonFatalError[4];
-
-/** Offset 0x0CD8 - PCIE RP System Error On Correctable Error
- Indicate whether the System Error on Correctable Error is enabled.
-**/
- UINT8 CpuPcieRpSystemErrorOnCorrectableError[4];
-
-/** Offset 0x0CDC - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 CpuPcieRpMaxPayload[4];
-
-/** Offset 0x0CE0 - DPC for PCIE RP Mask
- Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
- One bit for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT8 CpuPcieRpDpcEnabled[4];
-
-/** Offset 0x0CE4 - DPC Extensions PCIE RP Mask
- Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
- for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT8 CpuPcieRpDpcExtensionsEnabled[4];
-
-/** Offset 0x0CE8 - PCH PCIe root port connection type
- 0: built-in device, 1:slot
-**/
- UINT8 CpuPcieRpSlotImplemented[4];
-
-/** Offset 0x0CEC - PCIE RP Gen3 Equalization Phase Method
- PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
- 1: hardware equalization; 4: Fixed Coeficients.
-**/
- UINT8 CpuPcieRpGen3EqPh3Method[4];
-
-/** Offset 0x0CF0 - PCIE RP Gen4 Equalization Phase Method
- PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
- 1: hardware equalization; 4: Fixed Coeficients.
-**/
- UINT8 CpuPcieRpGen4EqPh3Method[4];
-
-/** Offset 0x0CF4 - Phase3 RP Gen3 EQ enable
- Phase3 Gen3 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase
- 3, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 CpuPcieRpGen3EqPh3Enable[4];
-
-/** Offset 0x0CF8 - Phase3 RP Gen4 EQ enable
- Phase3 Gen4 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase
- 3, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 CpuPcieRpGen4EqPh3Enable[4];
-
-/** Offset 0x0CFC - Phase2-3 RP Gen3 EQ enable
- Phase2-3 Gen3 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3,
- Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 CpuPcieRpGen3EqPh23Enable[4];
-
-/** Offset 0x0D00 - Phase2-3 RP Gen4 EQ enable
- Phase2-3 Gen4 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3,
- Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 CpuPcieRpGen4EqPh23Enable[4];
-
-/** Offset 0x0D04 - PCET Timer
- Preset/Coefficient Evaluation Timeout. See CPU_PCIE_PCET. Default is 0x4
-**/
- UINT8 CpuPciePcetTimer[4];
-
-/** Offset 0x0D08 - Gen3 Preset/Coeffiecient List Count
- Select Gen3 Hardware Autonomous Preset/Coefficient Count. See Gen3 CPU_PCIE_PRESETCOEFF_LIST.
- Default is 0x3
-**/
- UINT8 Gen3CpuPciePresetCoeffList[4];
-
-/** Offset 0x0D0C - Gen4 Preset/Coeffiecient List Count
- Select Gen4 Hardware Autonomous Preset/Coefficient Count. See CPU_PCIE_PRESETCOEFF_LIST.
- Default is 0x3
-**/
- UINT8 Gen4CpuPciePresetCoeffList[4];
-
-/** Offset 0x0D10 - Presets/Coefficients Evaluation for Gen3
- 8.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See
- CPU_PCIE_PX8GTSWLPCE. Default is 0x3
-**/
- UINT8 CpuPciePx8gtswlpce[4];
-
-/** Offset 0x0D14 - Presets/Coefficients Evaluation for Gen4
- 16.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See
- CPU_PCIE_PX16GTSWLPCE. Default is 0x4
-**/
- UINT8 CpuPciePx16gtswlpce[4];
-
-/** Offset 0x0D18 - PCIE RP Physical Slot Number
- Indicates the slot number for the root port. Default is the value as root port index.
-**/
- UINT8 CpuPcieRpPhysicalSlotNumber[4];
-
-/** Offset 0x0D1C - PCIE RP Aspm
- The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is
- CpuPcieAspmAutoConfig.
-**/
- UINT8 CpuPcieRpAspm[4];
-
-/** Offset 0x0D20 - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL).
- Default is CpuPcieL1SubstatesDisabled.
-**/
- UINT8 CpuPcieRpL1Substates[4];
-
-/** Offset 0x0D24 - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 CpuPcieRpLtrEnable[4];
-
-/** Offset 0x0D28 - PCIE RP Ltr Config Lock
- 0: Disable; 1: Enable.
-**/
- UINT8 CpuPcieRpLtrConfigLock[4];
-
-/** Offset 0x0D2C - PTM for PCIE RP Mask
- Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
- One bit for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT8 CpuPcieRpPtmEnabled[4];
-
-/** Offset 0x0D30 - PCIE RP Detect Timeout Ms
- The number of milliseconds within 0~65535 in reference code will wait for link to
- exit Detect state for enabled ports before assuming there is no device and potentially
- disabling the port.
-**/
- UINT16 CpuPcieRpDetectTimeoutMs[4];
-
-/** Offset 0x0D38 - VC for PCIE RP Mask
- Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit
- for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT8 CpuPcieRpVcEnabled[4];
-
-/** Offset 0x0D3C - Force GT CLOS on LLC for Real Time Performance
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 GtClosEnable;
-
-/** Offset 0x0D3D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
- Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
- value in array can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-
-/** Offset 0x0D47 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
- USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
- = 4Ch</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate3UniqTran[10];
-
-/** Offset 0x0D51 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
- Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
- value in array can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-
-/** Offset 0x0D5B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
- USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
- <b>Default = 4Ch</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate2UniqTran[10];
-
-/** Offset 0x0D65 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
- Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
- value in array can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-
-/** Offset 0x0D6F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
- USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
- <b>Default = 4Ch</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate1UniqTran[10];
-
-/** Offset 0x0D79 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
- Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
- value in array can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-
-/** Offset 0x0D83 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
- USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
- <b>Default = 4Ch</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxRate0UniqTran[10];
-
-/** Offset 0x0D8D - Skip PAM regsiter lock
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- $EN_DIS
-**/
- UINT8 SkipPamLock;
-
-/** Offset 0x0D8E - EDRAM Test Mode
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
-**/
- UINT8 EdramTestMode;
-
-/** Offset 0x0D8F - Enable/Disable IGFX RenderStandby
- Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
- $EN_DIS
-**/
- UINT8 RenderStandby;
-
-/** Offset 0x0D90 - Enable/Disable IGFX PmSupport
- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x0D91 - Enable/Disable CdynmaxClamp
- Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
- $EN_DIS
-**/
- UINT8 CdynmaxClampEnable;
-
-/** Offset 0x0D92 - GT Frequency Limit
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
-**/
- UINT8 GtFreqMax;
-
-/** Offset 0x0D93 - Disable Turbo GT
- 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
- $EN_DIS
-**/
- UINT8 DisableTurboGt;
-
-/** Offset 0x0D94 - Enable/Disable CdClock Init
- Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
- CD clock if not initialized by Gfx PEIM
- $EN_DIS
-**/
- UINT8 SkipCdClockInit;
-
-/** Offset 0x0D95
-**/
- UINT8 UnusedUpdSpace45[3];
-
-/** Offset 0x0D98 - LogoPixelHeight Address
- Address of LogoPixelHeight
-**/
- UINT32 LogoPixelHeight;
-
-/** Offset 0x0D9C - LogoPixelWidth Address
- Address of LogoPixelWidth
-**/
- UINT32 LogoPixelWidth;
-
-/** Offset 0x0DA0 - SaPostMemTestRsvd
- Reserved for SA Post-Mem Test
- $EN_DIS
-**/
- UINT8 SaPostMemTestRsvd[6];
-
-/** Offset 0x0DA6 - RSR feature
- Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
- $EN_DIS
-**/
- UINT8 EnableRsr;
-
-/** Offset 0x0DA7 - 1-Core Ratio Limit
- 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
- to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
-**/
- UINT8 OneCoreRatioLimit;
-
-/** Offset 0x0DA8 - 2-Core Ratio Limit
- 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 TwoCoreRatioLimit;
-
-/** Offset 0x0DA9 - 3-Core Ratio Limit
- 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 ThreeCoreRatioLimit;
-
-/** Offset 0x0DAA - 4-Core Ratio Limit
- 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 FourCoreRatioLimit;
-
-/** Offset 0x0DAB - Enable or Disable HWP
- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
- 2-3:Reserved
- $EN_DIS
-**/
- UINT8 Hwp;
-
-/** Offset 0x0DAC - Hardware Duty Cycle Control
- Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
- $EN_DIS
-**/
- UINT8 HdcControl;
-
-/** Offset 0x0DAD - Package Long duration turbo mode time
- Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
- 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PowerLimit1Time;
-
-/** Offset 0x0DAE - Short Duration Turbo Mode
- Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 PowerLimit2;
-
-/** Offset 0x0DAF - Turbo settings Lock
- Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
- $EN_DIS
-**/
- UINT8 TurboPowerLimitLock;
-
-/** Offset 0x0DB0 - Package PL3 time window
- Package PL3 time window range for this policy from 0 to 64ms
-**/
- UINT8 PowerLimit3Time;
-
-/** Offset 0x0DB1 - Package PL3 Duty Cycle
- Package PL3 Duty Cycle; Valid Range is 0 to 100
-**/
- UINT8 PowerLimit3DutyCycle;
-
-/** Offset 0x0DB2 - Package PL3 Lock
- Package PL3 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
- $EN_DIS
-**/
- UINT8 PowerLimit3Lock;
-
-/** Offset 0x0DB3 - Package PL4 Lock
- Package PL4 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
- $EN_DIS
-**/
- UINT8 PowerLimit4Lock;
-
-/** Offset 0x0DB4 - TCC Activation Offset
- TCC Activation Offset. Offset from factory set TCC activation temperature at which
- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
- Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
- <b>10</b>, For all other SKUs the recommended default are <b>0</b>
-**/
- UINT8 TccActivationOffset;
-
-/** Offset 0x0DB5 - Tcc Offset Clamp Enable/Disable
- Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
- below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
- For all other SKUs the recommended default are <b>0: Disabled</b>.
- $EN_DIS
-**/
- UINT8 TccOffsetClamp;
-
-/** Offset 0x0DB6 - Tcc Offset Lock
- Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
- target; <b>0: Disabled</b>; 1: Enabled.
- $EN_DIS
-**/
- UINT8 TccOffsetLock;
-
-/** Offset 0x0DB7 - Custom Ratio State Entries
- The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
- ratio table.Sets the number of custom P-states. At least 2 states must be present
-**/
- UINT8 NumberOfEntries;
-
-/** Offset 0x0DB8 - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
-**/
- UINT8 Custom1PowerLimit1Time;
-
-/** Offset 0x0DB9 - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
-**/
- UINT8 Custom1TurboActivationRatio;
-
-/** Offset 0x0DBA - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom1ConfigTdpControl;
-
-/** Offset 0x0DBB - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
-**/
- UINT8 Custom2PowerLimit1Time;
-
-/** Offset 0x0DBC - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
-**/
- UINT8 Custom2TurboActivationRatio;
-
-/** Offset 0x0DBD - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom2ConfigTdpControl;
-
-/** Offset 0x0DBE - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
-**/
- UINT8 Custom3PowerLimit1Time;
-
-/** Offset 0x0DBF - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
-**/
- UINT8 Custom3TurboActivationRatio;
-
-/** Offset 0x0DC0 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom3ConfigTdpControl;
-
-/** Offset 0x0DC1 - ConfigTdp mode settings Lock
- Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ConfigTdpLock;
-
-/** Offset 0x0DC2 - Load Configurable TDP SSDT
- Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ConfigTdpBios;
-
-/** Offset 0x0DC3 - PL1 Enable value
- PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit1;
-
-/** Offset 0x0DC4 - PL1 timewindow
- PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
- , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PsysPowerLimit1Time;
-
-/** Offset 0x0DC5 - PL2 Enable Value
- PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit2;
-
-/** Offset 0x0DC6 - Enable or Disable MLC Streamer Prefetcher
- Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MlcStreamerPrefetcher;
-
-/** Offset 0x0DC7 - Enable or Disable MLC Spatial Prefetcher
- Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 MlcSpatialPrefetcher;
-
-/** Offset 0x0DC8 - Enable or Disable Monitor /MWAIT instructions
- Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MonitorMwaitEnable;
-
-/** Offset 0x0DC9 - Enable or Disable initialization of machine check registers
- Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MachineCheckEnable;
-
-/** Offset 0x0DCA - Check if FUSA is supported
- Check if FUSA is supported; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 IsFusaSupported;
-
-/** Offset 0x0DCB - AP Idle Manner of waiting for SIPI
- AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
- 1: HALT loop, 2: MWAIT loop, 3: RUN loop
-**/
- UINT8 ApIdleManner;
-
-/** Offset 0x0DCC - Control on Processor Trace output scheme
- Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
- 0: Single Range Output, 1: ToPA Output
-**/
- UINT8 ProcessorTraceOutputScheme;
-
-/** Offset 0x0DCD - Enable or Disable Processor Trace feature
- Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcessorTraceEnable;
-
-/** Offset 0x0DCE - Enable or Disable Intel SpeedStep Technology
- Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Eist;
-
-/** Offset 0x0DCF - Enable or Disable Energy Efficient P-state
- Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientPState;
-
-/** Offset 0x0DD0 - Enable or Disable Energy Efficient Turbo
- Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientTurbo;
-
-/** Offset 0x0DD1 - Enable or Disable T states
- Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 TStates;
-
-/** Offset 0x0DD2 - Enable or Disable Bi-Directional PROCHOT#
- Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 BiProcHot;
-
-/** Offset 0x0DD3 - Enable or Disable PROCHOT# signal being driven externally
- Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DisableProcHotOut;
-
-/** Offset 0x0DD4 - Enable or Disable PROCHOT# Response
- Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcHotResponse;
-
-/** Offset 0x0DD5 - Enable or Disable VR Thermal Alert
- Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DisableVrThermalAlert;
-
-/** Offset 0x0DD6 - Enable or Disable Thermal Reporting
- Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 EnableAllThermalFunctions;
-
-/** Offset 0x0DD7 - Enable or Disable Thermal Monitor
- Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 ThermalMonitor;
-
-/** Offset 0x0DD8 - Enable or Disable CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Cx;
-
-/** Offset 0x0DD9 - Configure C-State Configuration Lock
- Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 PmgCstCfgCtrlLock;
-
-/** Offset 0x0DDA - Enable or Disable Enhanced C-states
- Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1e;
-
-/** Offset 0x0DDB - Enable or Disable Package Cstate Demotion
- Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 PkgCStateDemotion;
-
-/** Offset 0x0DDC - Enable or Disable Package Cstate UnDemotion
- Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 PkgCStateUnDemotion;
-
-/** Offset 0x0DDD - Enable or Disable CState-Pre wake
- Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 CStatePreWake;
-
-/** Offset 0x0DDE - Enable or Disable TimedMwait Support.
- Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 TimedMwait;
-
-/** Offset 0x0DDF - Enable or Disable IO to MWAIT redirection
- Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 CstCfgCtrIoMwaitRedirection;
-
-/** Offset 0x0DE0 - Set the Max Pkg Cstate
- Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
- C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
- 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
-**/
- UINT8 PkgCStateLimit;
-
-/** Offset 0x0DE1 - TimeUnit for C-State Latency Control0
- TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl0TimeUnit;
-
-/** Offset 0x0DE2 - TimeUnit for C-State Latency Control1
- TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl1TimeUnit;
-
-/** Offset 0x0DE3 - TimeUnit for C-State Latency Control2
- TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl2TimeUnit;
-
-/** Offset 0x0DE4 - TimeUnit for C-State Latency Control3
- TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl3TimeUnit;
-
-/** Offset 0x0DE5 - TimeUnit for C-State Latency Control4
- Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl4TimeUnit;
-
-/** Offset 0x0DE6 - TimeUnit for C-State Latency Control5
- TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl5TimeUnit;
-
-/** Offset 0x0DE7 - Interrupt Redirection Mode Select
- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
- No change.
-**/
- UINT8 PpmIrmSetting;
-
-/** Offset 0x0DE8 - Lock prochot configuration
- Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ProcHotLock;
-
-/** Offset 0x0DE9 - Configuration for boot TDP selection
- Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
- Up;0xFF : Deactivate
-**/
- UINT8 ConfigTdpLevel;
-
-/** Offset 0x0DEA - Max P-State Ratio
- Max P-State Ratio, Valid Range 0 to 0x7F
-**/
- UINT8 MaxRatio;
-
-/** Offset 0x0DEB - P-state ratios for custom P-state table
- P-state ratios for custom P-state table. NumberOfEntries has valid range between
- 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
- are configurable. Valid Range of each entry is 0 to 0x7F
-**/
- UINT8 StateRatio[40];
-
-/** Offset 0x0E13 - P-state ratios for max 16 version of custom P-state table
- P-state ratios for max 16 version of custom P-state table. This table is used for
- OS versions limited to a max of 16 P-States. If the first entry of this table is
- 0, or if Number of Entries is 16 or less, then this table will be ignored, and
- up to the top 16 values of the StateRatio table will be used instead. Valid Range
- of each entry is 0 to 0x7F
-**/
- UINT8 StateRatioMax16[16];
-
-/** Offset 0x0E23
-**/
- UINT8 UnusedUpdSpace46;
-
-/** Offset 0x0E24 - Platform Power Pmax
- PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
- Range 0-1024 Watts. Value of 800 = 100W
-**/
- UINT16 PsysPmax;
-
-/** Offset 0x0E26 - Interrupt Response Time Limit of C-State LatencyContol1
- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
- 0 is Auto.
-**/
- UINT16 CstateLatencyControl1Irtl;
-
-/** Offset 0x0E28 - Interrupt Response Time Limit of C-State LatencyContol2
- Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
- 0 is Auto.
-**/
- UINT16 CstateLatencyControl2Irtl;
-
-/** Offset 0x0E2A - Interrupt Response Time Limit of C-State LatencyContol3
- Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
- 0 is Auto.
-**/
- UINT16 CstateLatencyControl3Irtl;
-
-/** Offset 0x0E2C - Interrupt Response Time Limit of C-State LatencyContol4
- Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
- 0 is Auto.
-**/
- UINT16 CstateLatencyControl4Irtl;
-
-/** Offset 0x0E2E - Interrupt Response Time Limit of C-State LatencyContol5
- Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
- 0 is Auto.
-**/
- UINT16 CstateLatencyControl5Irtl;
-
-/** Offset 0x0E30 - Package Long duration turbo mode power limit
- Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
- Valid Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit1;
-
-/** Offset 0x0E34 - Package Short duration turbo mode power limit
- Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit2Power;
-
-/** Offset 0x0E38 - Package PL3 power limit
- Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit3;
-
-/** Offset 0x0E3C - Package PL4 power limit
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit4;
-
-/** Offset 0x0E40 - Tcc Offset Time Window for RATL
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 TccOffsetTimeWindowForRatl;
-
-/** Offset 0x0E44 - Short term Power Limit value for custom cTDP level 1
- Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit1;
-
-/** Offset 0x0E48 - Long term Power Limit value for custom cTDP level 1
- Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit2;
-
-/** Offset 0x0E4C - Short term Power Limit value for custom cTDP level 2
- Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit1;
-
-/** Offset 0x0E50 - Long term Power Limit value for custom cTDP level 2
- Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit2;
-
-/** Offset 0x0E54 - Short term Power Limit value for custom cTDP level 3
- Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit1;
-
-/** Offset 0x0E58 - Long term Power Limit value for custom cTDP level 3
- Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit2;
-
-/** Offset 0x0E5C - Platform PL1 power
- Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit1Power;
-
-/** Offset 0x0E60 - Platform PL2 power
- Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit2Power;
-
-/** Offset 0x0E64 - Race To Halt
- Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
- in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
- through MSR 1FC bit 20)Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 RaceToHalt;
-
-/** Offset 0x0E65 - Set Three Strike Counter Disable
- False (default): Three Strike counter will be incremented and True: Prevents Three
- Strike counter from incrementing; <b>0: False</b>; 1: True.
- 0: False, 1: True
-**/
- UINT8 ThreeStrikeCounterDisable;
-
-/** Offset 0x0E66 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
- Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 HwpInterruptControl;
-
-/** Offset 0x0E67 - 5-Core Ratio Limit
- 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
- 0x0:0xFF
-**/
- UINT8 FiveCoreRatioLimit;
-
-/** Offset 0x0E68 - 6-Core Ratio Limit
- 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
- 0x0:0xFF
-**/
- UINT8 SixCoreRatioLimit;
-
-/** Offset 0x0E69 - 7-Core Ratio Limit
- 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
- 0x0:0xFF
-**/
- UINT8 SevenCoreRatioLimit;
-
-/** Offset 0x0E6A - 8-Core Ratio Limit
- 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
- 0x0:0xFF
-**/
- UINT8 EightCoreRatioLimit;
-
-/** Offset 0x0E6B - Intel Turbo Boost Max Technology 3.0
- Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
- $EN_DIS
-**/
- UINT8 EnableItbm;
-
-/** Offset 0x0E6C - Intel Turbo Boost Max Technology 3.0 Driver
- Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
- $EN_DIS
-**/
- UINT8 EnableItbmDriver;
-
-/** Offset 0x0E6D - Enable or Disable C1 Cstate Demotion
- Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1StateAutoDemotion;
-
-/** Offset 0x0E6E - Enable or Disable C1 Cstate UnDemotion
- Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1StateUnDemotion;
-
-/** Offset 0x0E6F - Minimum Ring ratio limit override
- Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
- ratio limit
-**/
- UINT8 MinRingRatioLimit;
-
-/** Offset 0x0E70 - Maximum Ring ratio limit override
- Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
- ratio limit
-**/
- UINT8 MaxRingRatioLimit;
-
-/** Offset 0x0E71 - Enable or Disable Per Core P State OS control
- Enable or Disable Per Core P State OS control. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnablePerCorePState;
-
-/** Offset 0x0E72 - Enable or Disable HwP Autonomous Per Core P State OS control
- Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; <b>1:
- Enable</b>
- $EN_DIS
-**/
- UINT8 EnableHwpAutoPerCorePstate;
-
-/** Offset 0x0E73 - Enable or Disable HwP Autonomous EPP Grouping
- Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnableHwpAutoEppGrouping;
-
-/** Offset 0x0E74 - Enable or Disable EPB override over PECI
- Enable or Disable EPB override over PECI. <b>0: Disable;</b> 1: Enable
- $EN_DIS
-**/
- UINT8 EnableEpbPeciOverride;
-
-/** Offset 0x0E75 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
- Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnableFastMsrHwpReq;
-
-/** Offset 0x0E76 - Enable Configurable TDP
- Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP;
- <b>1: Applies to cTDP</b>
- $EN_DIS
-**/
- UINT8 ApplyConfigTdp;
-
-/** Offset 0x0E77 - ReservedCpuPostMemTest
- Reserved for CPU Post-Mem Test
- $EN_DIS
-**/
- UINT8 ReservedCpuPostMemTest[16];
-
-/** Offset 0x0E87
-**/
- UINT8 SecurityPostMemRsvd[16];
-
-/** Offset 0x0E97 - D0I3 Setting for HECI Disable
- Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
- HECI devices
- $EN_DIS
-**/
- UINT8 DisableD0I3SettingForHeci;
-
-/** Offset 0x0E98 - Enable LOCKDOWN SMI
- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
- $EN_DIS
-**/
- UINT8 PchLockDownGlobalSmi;
-
-/** Offset 0x0E99 - Enable LOCKDOWN BIOS Interface
- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosInterface;
-
-/** Offset 0x0E9A - Unlock all GPIO pads
- Force all GPIO pads to be unlocked for debug purpose.
- $EN_DIS
-**/
- UINT8 PchUnlockGpioPads;
-
-/** Offset 0x0E9B - PCH Unlock SideBand access
- The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
- 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
- $EN_DIS
-**/
- UINT8 PchSbAccessUnlock;
-
-/** Offset 0x0E9C - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[24];
-
-/** Offset 0x0ECC - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-
-/** Offset 0x0EFC - PCIE RP Snoop Latency Override Mode
- Latency Tolerance Reporting, Snoop Latency Override Mode.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMode[24];
-
-/** Offset 0x0F14 - PCIE RP Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x0F2C - PCIE RP Snoop Latency Override Value
- Latency Tolerance Reporting, Snoop Latency Override Value.
-**/
- UINT16 PcieRpSnoopLatencyOverrideValue[24];
-
-/** Offset 0x0F5C - PCIE RP Non Snoop Latency Override Mode
- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
-
-/** Offset 0x0F74 - PCIE RP Non Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x0F8C - PCIE RP Non Snoop Latency Override Value
- Latency Tolerance Reporting, Non-Snoop Latency Override Value.
-**/
- UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
-
-/** Offset 0x0FBC - PCIE RP Slot Power Limit Scale
- Specifies scale used for slot power limit value. Leave as 0 to set to default.
-**/
- UINT8 PcieRpSlotPowerLimitScale[24];
-
-/** Offset 0x0FD4 - PCIE RP Slot Power Limit Value
- Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
-**/
- UINT16 PcieRpSlotPowerLimitValue[24];
-
-/** Offset 0x1004 - PCIE RP Enable Port8xh Decode
- This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieEnablePort8xhDecode;
-
-/** Offset 0x1005 - PCIE Port8xh Decode Port Index
- The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
-**/
- UINT8 PchPciePort8xhDecodePortIndex;
-
-/** Offset 0x1006 - PCH Energy Reporting
- Disable/Enable PCH to CPU energy report feature.
- $EN_DIS
-**/
- UINT8 PchPmDisableEnergyReport;
-
-/** Offset 0x1007 - PCH Sata Test Mode
- Allow entrance to the PCH SATA test modes.
- $EN_DIS
-**/
- UINT8 SataTestMode;
-
-/** Offset 0x1008 - PCH USB OverCurrent mapping lock enable
- If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
- that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
- $EN_DIS
-**/
- UINT8 PchXhciOcLock;
-
-/** Offset 0x1009 - Low Power Mode Enable/Disable config mask
- Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
- to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
- LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
-**/
- UINT8 PmcLpmS0ixSubStateEnableMask;
-
-/** Offset 0x100A - Mctp Broadcast Cycle
- Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 MctpBroadcastCycle;
-
-/** Offset 0x100B
-**/
- UINT8 UnusedUpdSpace47[1];
-
-/** Offset 0x100C - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 CpuPcieRpLtrMaxSnoopLatency[4];
-
-/** Offset 0x1014 - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4];
-
-/** Offset 0x101C - PCIE RP Snoop Latency Override Mode
- Latency Tolerance Reporting, Snoop Latency Override Mode.
-**/
- UINT8 CpuPcieRpSnoopLatencyOverrideMode[4];
-
-/** Offset 0x1020 - PCIE RP Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Snoop Latency Override Multiplier.
-**/
- UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4];
-
-/** Offset 0x1024 - PCIE RP Snoop Latency Override Value
- Latency Tolerance Reporting, Snoop Latency Override Value.
-**/
- UINT16 CpuPcieRpSnoopLatencyOverrideValue[4];
-
-/** Offset 0x102C - PCIE RP Non Snoop Latency Override Mode
- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
-**/
- UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4];
-
-/** Offset 0x1030 - PCIE RP Non Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
-**/
- UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4];
-
-/** Offset 0x1034 - PCIE RP Non Snoop Latency Override Value
- Latency Tolerance Reporting, Non-Snoop Latency Override Value.
-**/
- UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4];
-
-/** Offset 0x103C - PCIE RP Upstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 CpuPcieRpGen3Uptp[4];
-
-/** Offset 0x1040 - PCIE RP Downstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 CpuPcieRpGen3Dptp[4];
-
-/** Offset 0x1044 - PCIE RP Upstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 CpuPcieRpGen4Uptp[4];
-
-/** Offset 0x1048 - PCIE RP Downstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 CpuPcieRpGen4Dptp[4];
-
-/** Offset 0x104C - Enable PSE JTAG debug option
- Set if to enable JTAG debug feature for PSE. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseJtagEnabled;
-
-/** Offset 0x104D - Enable PSE JTAG pin option
- This option is used to enable or disable PSE JTAG pin pad mode. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseJtagPinMux;
-
-/** Offset 0x104E - Enable PSE SHELL option
- Set if to enable PSE Shell feature. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseShellEnabled;
-
-/** Offset 0x104F - Enable PSE ECLITE option
- Set if to enable PSE Eclite feature. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseEcliteEnabled;
-
-/** Offset 0x1050 - Enable PSE OOB option
- Set if to enable PSE OOB feature. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseOobEnabled;
-
-/** Offset 0x1051 - Enable CPU Temperature Read
- Set to enable CPU Temperature Read feature. 0: Disable; 1: Enable.
-**/
- UINT8 PchCpuTempSensorEnable;
-
-/** Offset 0x1052 - Enable PSE WoL option
- Set if to enable PSE WoL feature. 0: Disable; 1: Enable.
-**/
- UINT8 PchPseWoLEnabled;
-
-/** Offset 0x1053
-**/
- UINT8 ReservedFspsUpd[13];
-} FSP_S_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x1060
-**/
- UINT8 UnusedUpdSpace48[6];
-
-/** Offset 0x1066
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - Logo Pointer + Points to PEI Display Logo Image +**/ + UINT32 LogoPtr; + +/** Offset 0x0024 - Logo Size + Size of PEI Display Logo Image +**/ + UINT32 LogoSize; + +/** Offset 0x0028 - Blt Buffer Address + Address of Blt buffer +**/ + UINT32 BltBufferAddress; + +/** Offset 0x002C - Blt Buffer Size + Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of + EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +**/ + UINT32 BltBufferSize; + +/** Offset 0x0030 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x0034 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x0035 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0036 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0037 - Enable eMMC DDR50 Mode + Enable eMMC DDR50 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcDdr50Enabled; + +/** Offset 0x0038 - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 EmmcUseCustomDlls; + +/** Offset 0x0039 +**/ + UINT8 UnusedUpdSpace0[3]; + +/** Offset 0x003C - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x0040 - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x0044 - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x004C - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x0050 - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x0054 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0055 - SdCard power enable polarity + Choose SD_PWREN# polarity + 0: Active low, 1: Active high +**/ + UINT8 SdCardPowerEnableActiveHigh; + +/** Offset 0x0056 - Use tuned DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 SdCardUseCustomDlls; + +/** Offset 0x0057 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0058 - SdCard Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 SdCardTxCmdDelayRegValue; + +/** Offset 0x005C - SdCard Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 SdCardTxDataDelay1RegValue; + +/** Offset 0x0060 - SdCard Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 SdCardTxDataDelay2RegValue; + +/** Offset 0x0064 - SdCard Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay1RegValue; + +/** Offset 0x0068 - SdCard Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay2RegValue; + +/** Offset 0x006C - SdCard Power Enable Pin Mux + Select Power Enable pin muxing. Refer to GPIO_*_MUXING_SDCARD_PWR_EN* for possible values. +**/ + UINT32 SdCardGpioPrwEnBPinMux; + +/** Offset 0x0070 - SdCard Power Enable Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioPrwEnBPadTermination; + +/** Offset 0x0071 +**/ + UINT8 UnusedUpdSpace2[3]; + +/** Offset 0x0074 - SdCard Command Pin Mux + Select Command pin muxing. Refer to GPIO_*_MUXING_SDCARD_CMD* for possible values. +**/ + UINT32 SdCardGpioCmdPinMux; + +/** Offset 0x0078 - SdCard Command Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioCmdPadTermination; + +/** Offset 0x0079 +**/ + UINT8 UnusedUpdSpace3[3]; + +/** Offset 0x007C - SdCard Data Pin Mux + Select Data pin muxing. Refer to GPIO_*_MUXING_SDCARD_DATAx_* for possible values. + One UINT32 for each data pin [0-4] +**/ + UINT32 SdCardGpioDataPinMux[4]; + +/** Offset 0x008C - SdCard Data Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up. One byte for each data pin [0-4] +**/ + UINT8 SdCardGpioDataPadTermination[4]; + +/** Offset 0x0090 - SdCard Cdb Pin Mux + Select Cdb pin muxing. Refer to GPIO_*_MUXING_SDCARD_CDB* for possible values. +**/ + UINT32 SdCardGpioCdbPinMux; + +/** Offset 0x0094 - SdCard Cdb Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioCdbPadTermination; + +/** Offset 0x0095 +**/ + UINT8 UnusedUpdSpace4[3]; + +/** Offset 0x0098 - SdCard Clock Pin Mux + Select Clock pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK* for possible values. +**/ + UINT32 SdCardGpioClkPinMux; + +/** Offset 0x009C - SdCard Clock Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioClkPadTermination; + +/** Offset 0x009D +**/ + UINT8 UnusedUpdSpace5[3]; + +/** Offset 0x00A0 - SdCard Wp PinMux + Select Wp pin muxing. Refer to GPIO_*_MUXING_SDCARD_WP* for possible values. +**/ + UINT32 SdCardGpioWpPinMux; + +/** Offset 0x00A4 - SdCard Wp Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioWpPadTermination; + +/** Offset 0x00A5 +**/ + UINT8 UnusedUpdSpace6[3]; + +/** Offset 0x00A8 - SdCard Clock Feedback Pin Mux + Select pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK_FB* for possible values. +**/ + UINT32 SdCardGpioClkFbPinMux; + +/** Offset 0x00AC - SdCard Clock Feedback Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 SdCardGpioClkFbPadTermination; + +/** Offset 0x00AD +**/ + UINT8 UnusedUpdSpace7[3]; + +/** Offset 0x00B0 - Emmc Command Pin Mux + Select pin muxing. Refer to GPIO_*_MUXING_EMMC_CMD* for possible values. +**/ + UINT32 EmmcGpioCmdPinMux; + +/** Offset 0x00B4 - Emmc Command Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioCmdPadTermination; + +/** Offset 0x00B5 - Emmc Data Pin Mux + Select pin muxing. Refer to GPIO_*_MUXING_EMMC_DATA_x* for possible values. One + UINT32 for each data pin [0-8] +**/ + UINT8 EmmcGpioDataPinMux[32]; + +/** Offset 0x00D5 - Emmc Data Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up. One byte for each data pin [0-8] +**/ + UINT8 EmmcGpioDataPadTermination[8]; + +/** Offset 0x00DD +**/ + UINT8 UnusedUpdSpace8[3]; + +/** Offset 0x00E0 - Emmc Rclk PinMux + Select Rclk pin muxing. Refer to GPIO_*_MUXING_EMMC_RCLK* for possible values. +**/ + UINT32 EmmcGpioRclkPinMux; + +/** Offset 0x00E4 - Emmc Rclk Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioRclkPadTermination; + +/** Offset 0x00E5 +**/ + UINT8 UnusedUpdSpace9[3]; + +/** Offset 0x00E8 - Emmc Clock Pin Mux + Select Clock pin muxing. Refer to GPIO_*_MUXING_EMMC_CLK* for possible values. +**/ + UINT32 EmmcGpioClkPinMux; + +/** Offset 0x00EC - Emmc Clock Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioClkPadTermination; + +/** Offset 0x00ED +**/ + UINT8 UnusedUpdSpace10[3]; + +/** Offset 0x00F0 - Emmc Resetb PinMux + Select Resetb pin muxing. Refer to GPIO_*_MUXING_EMMC_RESETB* for possible values. +**/ + UINT32 EmmcGpioResetbPinMux; + +/** Offset 0x00F4 - Emmc Resetb Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioResetbPadTermination; + +/** Offset 0x00F5 +**/ + UINT8 UnusedUpdSpace11[3]; + +/** Offset 0x00F8 - Emmc HipMon PinMux + Select HipMon pin muxing. Refer to GPIO_*_MUXING_EMMC_HIP_MON* for possible values. +**/ + UINT32 EmmcGpioHipMonPinMux; + +/** Offset 0x00FC - Emmc HipMon Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioHipMonPadTermination; + +/** Offset 0x00FD - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x00FE +**/ + UINT8 UnusedUpdSpace12[2]; + +/** Offset 0x0100 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0104 - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0108 - SiipRegionBase + Memory Base of Siip Firmware +**/ + UINT32 SiipRegionBase; + +/** Offset 0x010C - SiipRegionSize + Size of Siip Firmware +**/ + UINT32 SiipRegionSize; + +/** Offset 0x0110 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0111 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0112 - PCH Sata Port Multiplier + Enable / Disable SATA Port Multiplier + $EN_DIS +**/ + UINT8 SataPortMultiplier; + +/** Offset 0x0113 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x011B - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0123 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0133 - Enable USB2 ports OTG + Selectively Enable/Disable USB2 OTG Mode. One byte for each port, byte0 for port0, + byte1 for port1, and so on. +**/ + UINT8 USB20Otg[16]; + +/** Offset 0x0143 - Enable USB3 ports OTG + Selectively Enable/Disable USB3 OTG Mode. One byte for each port, byte0 for port0, + byte1 for port1, and so on. +**/ + UINT8 USB30Otg[10]; + +/** Offset 0x014D - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x0157 - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x0158 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x015C - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x015D - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x0165 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x0166 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x0167 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x0168 - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x0169 - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x016A +**/ + UINT8 UnusedUpdSpace13[2]; + +/** Offset 0x016C - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT32 PchHdaVerbTablePtr; + +/** Offset 0x0170 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x0171 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x0172 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0173 - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[7]; + +/** Offset 0x017A - SPI<N> Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, + 1:SerialIoSpiCsActiveHigh +**/ + UINT8 SerialIoSpiCsPolarity[14]; + +/** Offset 0x0188 - SPI<N> Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpiCsEnable[14]; + +/** Offset 0x0196 - SPIn Default Chip Select Output + Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available + options: 0:CS0, 1:CS1 +**/ + UINT8 SerialIoSpiDefaultCsOutput[7]; + +/** Offset 0x019D - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[7]; + +/** Offset 0x01A4 - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[7]; + +/** Offset 0x01AB - SPIn Master Input Slave Output Enable/Disable + 0:Disabled, 1:Enabled. Sets Native Mode for SPIx MISO GPIO if it is Enabled +**/ + UINT8 SerialIoSpiMisoEnable[3]; + +/** Offset 0x01AE - SPIn Delayed Rx Clock setting + 00:As-is, 01:Internal, 10:NegEdge Tx Clock, 11:NegEdge Delayed Rx Clk. Configure + Delayed Rx Clock +**/ + UINT8 SerialIoSpiDelayRxClk[3]; + +/** Offset 0x01B1 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[7]; + +/** Offset 0x01B8 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[7]; + +/** Offset 0x01D4 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[7]; + +/** Offset 0x01DB - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[7]; + +/** Offset 0x01E2 - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[7]; + +/** Offset 0x01E9 - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[7]; + +/** Offset 0x01F0 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[7]; + +/** Offset 0x01F7 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[7]; + +/** Offset 0x01FE +**/ + UINT8 UnusedUpdSpace14[2]; + +/** Offset 0x0200 - SerialIoUartRtsPinMuxPolicy + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMuxPolicy[7]; + +/** Offset 0x021C - SerialIoUartCtsPinMuxPolicy + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMuxPolicy[7]; + +/** Offset 0x0238 - SerialIoUartRxPinMuxPolicy + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMuxPolicy[7]; + +/** Offset 0x0254 - SerialIoUartTxPinMuxPolicy + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMuxPolicy[7]; + +/** Offset 0x0270 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, + 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used + for debug purpose. + 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x0271 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b> + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[7]; + +/** Offset 0x0278 - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[8]; + +/** Offset 0x0280 - Serial IO I2C SDA Pin Muxing + Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for + possible values. +**/ + UINT32 PchSerialIoI2cSdaPinMux[8]; + +/** Offset 0x02A0 - Serial IO I2C SCL Pin Muxing + Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for + possible values. +**/ + UINT32 PchSerialIoI2cSclPinMux[8]; + +/** Offset 0x02C0 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. + 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU +**/ + UINT8 PchSerialIoI2cPadsTermination[8]; + +/** Offset 0x02C8 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x02D8 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x02E8 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x02F8 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x0308 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x0312 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x031C - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x0326 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default + = 00h</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x0330 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x033A +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x0344 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x034E +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x0358 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x0362 +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x036C +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x0376 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x0380 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x0381 - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS +**/ + UINT8 PchTsnEnable; + +/** Offset 0x0382 - PCH TSN Multi VC Enable + Enable/Disable PCH TSN GBE Multiple Virtual Channel + $EN_DIS +**/ + UINT8 PchTsnGbeMultiVcEnable; + +/** Offset 0x0383 - PCH TSN Link Speed + Set PCH TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PchTsnGbeLinkSpeed; + +/** Offset 0x0384 - PCH TSN SGMII Support + Enable/disable SGMII support + $EN_DIS +**/ + UINT8 PchTsnGbeSgmiiEnable; + +/** Offset 0x0385 - PSE TSN Multi VC Enable + Enable/Disable PSE TSN GBE Multiple Virtual Channel + $EN_DIS +**/ + UINT8 PseTsnGbeMultiVcEnable[2]; + +/** Offset 0x0387 - PSE TSN Link Speed + Set TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PseTsnGbeLinkSpeed[2]; + +/** Offset 0x0389 - PSE TSN SGMII Support + Enable/disable SGMII support + $EN_DIS +**/ + UINT8 PseTsnGbeSgmiiEnable[2]; + +/** Offset 0x038B - PSE TSN Phy Interface Type + Set PSE TSN Phy Interface Type + 0: Not Connected, 1: RGMII, 2: SGMII, 3:SGMII+ +**/ + UINT8 PseTsnGbePhyInterfaceType[2]; + +/** Offset 0x038D +**/ + UINT8 UnusedUpdSpace15[3]; + +/** Offset 0x0390 - Tsn Mac Address Sub Region Base + Base address of TSN MAC Address Sub Region +**/ + UINT32 TsnMacAddrBase; + +/** Offset 0x0394 - Tsn Mac Address Sub Region Size + Size of TSN MAC Address Sub Region +**/ + UINT32 TsnMacAddrSize; + +/** Offset 0x0398 - PSE Tsn Ip Config Sub Region Base + Base address of PSE TSN IP Config Sub Region +**/ + UINT32 PseTsnIpConfigBase; + +/** Offset 0x039C - PSE Tsn Ip Config Sub Region Size + Size of PSE TSN IP Config Sub Region +**/ + UINT32 PseTsnIpConfigSize; + +/** Offset 0x03A0 - Tsn Config Sub Region Base + Base address of TSN Config Sub Region +**/ + UINT32 TsnConfigBase; + +/** Offset 0x03A4 - Tsn Config Sub Region Size + Size of TSN Config Sub Region +**/ + UINT32 TsnConfigSize; + +/** Offset 0x03A8 - PSE GBE0 DLL OVERRIDE + Enable/Disable PSE GBE DLL OVERRIDE + $EN_DIS +**/ + UINT8 PseGbeDllOverride[2]; + +/** Offset 0x03AA - PSE GBE TX_Delay + PSE GBE TX_Delay configuration. +**/ + UINT8 PseGbeTxDelay[2]; + +/** Offset 0x03AC - PCIe PTM enable/disable + Enable/disable Precision Time Measurement for PCIE Root Ports. +**/ + UINT8 PciePtm[24]; + +/** Offset 0x03C4 - PCIe DPC enable/disable + Enable/disable Downstream Port Containment for PCIE Root Ports. +**/ + UINT8 PcieDpc[24]; + +/** Offset 0x03DC - PCIe DPC extensions enable/disable + Enable/disable Downstream Port Containment Extensions for PCIE Root Ports. +**/ + UINT8 PcieEdpc[24]; + +/** Offset 0x03F4 - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x03F5 +**/ + UINT8 UnusedUpdSpace16[3]; + +/** Offset 0x03F8 - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x03FC - PCH eSPI Master and Slave BME enabled + PCH eSPI Master and Slave BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeMasterSlaveEnabled; + +/** Offset 0x03FD - PCH SATA use RST Legacy OROM + Use PCH SATA RST Legacy OROM when CSM is Enabled + $EN_DIS +**/ + UINT8 SataRstLegacyOrom; + +/** Offset 0x03FE - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x03FF - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x0400 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x0402 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x0403 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x0404 - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x0405 +**/ + UINT8 UnusedUpdSpace17; + +/** Offset 0x0406 - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x0408 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x0409 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x040A - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x040C - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x040D - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x040E - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x040F - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x0410 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x0412 +**/ + UINT8 UnusedUpdSpace18[2]; + +/** Offset 0x0414 - Trace Hub Memory Base + If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate + trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub + memory is configured properly. +**/ + UINT32 TraceHubMemBase; + +/** Offset 0x0418 - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x0419 +**/ + UINT8 UnusedUpdSpace19[3]; + +/** Offset 0x041C - Pointer of ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x0420 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x0424 - ChipsetInit Sync Enable + Enable/Disable. 0: Disable, 1: Enable +**/ + UINT8 ChipsetInitSyncEnable; + +/** Offset 0x0425 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x0426 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x0428 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x042A - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x042C - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x042D - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x042E - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd[11]; + +/** Offset 0x0439 +**/ + UINT8 UnusedUpdSpace20[3]; + +/** Offset 0x043C - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x0440 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; + +/** Offset 0x0444 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x0445 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x0446 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x0447 +**/ + UINT8 UnusedUpdSpace21; + +/** Offset 0x0448 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194BE404. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* + in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x044C - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394BE605. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* + in GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0450 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x0451 - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x0452 - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x0453 - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0454 - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x0455 - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; + +/** Offset 0x0456 - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. + 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x0457 - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x0458 - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x0459 - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x045A - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x045B - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 WatchDogEnabled; + +/** Offset 0x045C - Manageability Mode set by Mebx + Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. + $EN_DIS +**/ + UINT8 ManageabilityMode; + +/** Offset 0x045D - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 FwProgress; + +/** Offset 0x045E - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. + Setting is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x045F +**/ + UINT8 UnusedUpdSpace22; + +/** Offset 0x0460 - OS Timer + 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x0462 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x0464 - Remote Assistance Trigger Availablilty + Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. + $EN_DIS +**/ + UINT8 RemoteAssistance; + +/** Offset 0x0465 - KVM Switch + Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting + is invalid if AmtEnabled is 0. + $EN_DIS +**/ + UINT8 AmtKvmEnabled; + +/** Offset 0x0466 - KVM Switch + Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. + $EN_DIS +**/ + UINT8 ForcMebxSyncUp; + +/** Offset 0x0467 - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[24]; + +/** Offset 0x047F - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[24]; + +/** Offset 0x0497 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[24]; + +/** Offset 0x04AF - PCIE RP Multi VC Enabled + Enable/Disable PCIE RP Multiple Virtual Channels +**/ + UINT8 PcieRpMultiVcEnabled[24]; + +/** Offset 0x04C7 - PCIE RP VC1 to TC Mapping + PCIE RP Virtual Channel 1 to Traffic Class mapping +**/ + UINT8 PcieRpVc1TcMap[24]; + +/** Offset 0x04DF +**/ + UINT8 UnusedUpdSpace23[1]; + +/** Offset 0x04E0 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[24]; + +/** Offset 0x0510 - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x0511 - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x0512 - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; + +/** Offset 0x0513 - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x0514 - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 307.2, 1: 312 Mhz, + 2: 552 Mhz, 3: 556.8 Mhz, 4: 648 Mhz, 5: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 307.2, 1: 312 Mhz, 2: 552 + Mhz, 3: 556.8 Mhz, 4: 648 Mhz, 5: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x0515 - Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x0516 - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x0517 - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x0518 - Enable or disable HPD of DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI, + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0519 - Enable or disable HPD of DDI port-B device + 1(Default)=DP, 2=MIPI DSI, 3=HDMI + 1:DP, 2:MIPI DSI, 3:HDMI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x051A - Enable or disable HPD of DDI port-C device + 1(Default)= HDMI, 2=DP + 1:HDMI, 2:DP +**/ + UINT8 DdiPortCConfig; + +/** Offset 0x051B - Enable or disable HPD of DDI port A + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x051C - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x051D - Enable or disable HPD of DDI port C + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x051E - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x051F - Enable or disable HPD of DDI port 2 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0520 - Enable or disable HPD of DDI port 3 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0521 - Enable or disable HPD of DDI port 4 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0522 - Enable or disable DDC of DDI port A + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0523 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0524 - Enable or disable DDC of DDI port C + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0525 - Enable DDC setting of DDI Port 1 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0526 - Enable DDC setting of DDI Port 2 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0527 - Enable DDC setting of DDI Port 3 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0528 - Enable DDC setting of DDI Port 4 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0529 +**/ + UINT8 UnusedUpdSpace24[3]; + +/** Offset 0x052C - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Ehl + = ElkhartLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x054C - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x0554 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x0555 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 SaPostMemRsvd[8]; + +/** Offset 0x055D - Enable VMD controller + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x055E - Enable VMD portA Support + Enable/disable to VMD portA Support. + $EN_DIS +**/ + UINT8 VmdPortA; + +/** Offset 0x055F - Enable VMD portB Support + Enable/disable to VMD portB Support. + $EN_DIS +**/ + UINT8 VmdPortB; + +/** Offset 0x0560 - Enable VMD portC Support + Enable/disable to VMD portC Support. + $EN_DIS +**/ + UINT8 VmdPortC; + +/** Offset 0x0561 - Enable VMD portD Support + Enable/disable to VMD portD Support. + $EN_DIS +**/ + UINT8 VmdPortD; + +/** Offset 0x0562 - VMD Config Bar size + Set The VMD Config Bar Size. +**/ + UINT8 VmdCfgBarSz; + +/** Offset 0x0563 - VMD Config Bar Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdCfgBarAttr; + +/** Offset 0x0564 - VMD Mem Bar1 size + Set The VMD Mem Bar1 Size. +**/ + UINT8 VmdMemBarSz1; + +/** Offset 0x0565 - VMD Mem Bar1 Attributes + 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar1Attr; + +/** Offset 0x0566 - VMD Mem Bar2 size + Set The VMD Mem Bar2 Size. +**/ + UINT8 VmdMemBarSz2; + +/** Offset 0x0567 - VMD Mem Bar2 Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar2Attr; + +/** Offset 0x0568 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x0569 +**/ + UINT8 UnusedUpdSpace25; + +/** Offset 0x056A - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x056C - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x056E - USB override in IOM + This policy will enable/disable USB Connect override in IOM + $EN_DIS +**/ + UINT8 UsbOverride; + +/** Offset 0x056F - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x0570 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x0574 - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x0576 - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x0578 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x0579 +**/ + UINT8 UnusedUpdSpace26[1]; + +/** Offset 0x057A - ITBT DMA LTR + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x057E - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x057F - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x0583 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x0587 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x058B - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x058F +**/ + UINT8 UnusedUpdSpace27[1]; + +/** Offset 0x0590 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x0598 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x059C - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x05A0 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x05A8 - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x05AC - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x05B0 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x05B1 - Power State 3 enable/disable + PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>. + For all VR Indexes +**/ + UINT8 Psi3Enable[5]; + +/** Offset 0x05B6 - Power State 4 enable/disable + PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For + all VR Indexes +**/ + UINT8 Psi4Enable[5]; + +/** Offset 0x05BB +**/ + UINT8 UnusedUpdSpace28[1]; + +/** Offset 0x05BC - Imon slope correction + PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. + Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes +**/ + UINT16 ImonSlope[5]; + +/** Offset 0x05C6 - Imon offset correction + PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. + Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b> +**/ + UINT16 ImonOffset[5]; + +/** Offset 0x05D0 - Enable/Disable BIOS configuration of VR + Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes +**/ + UINT8 VrConfigEnable[5]; + +/** Offset 0x05D5 - Thermal Design Current enable/disable + PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: + Enable.For all VR Indexes +**/ + UINT8 TdcEnable[5]; + +/** Offset 0x05DA +**/ + UINT8 UnusedUpdSpace29[2]; + +/** Offset 0x05DC - Thermal Design Current time window + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 TdcTimeWindow[5]; + +/** Offset 0x05F0 - Thermal Design Current Lock + PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For + all VR Indexes +**/ + UINT8 TdcLock[5]; + +/** Offset 0x05F5 - Platform Psys slope correction + PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x05F6 - Platform Psys offset correction + PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/1000, + Range 0-63999. For an offset of 25.348, enter 25348. +**/ + UINT16 PsysOffset; + +/** Offset 0x05F8 - Acoustic Noise Mitigation feature + Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x05F9 - Disable Fast Slew Rate for Deep Package C States for VR domains + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisable[5]; + +/** Offset 0x05FE - Slew Rate configuration for Deep Package C States for VR domains + Slew Rate configuration for Deep Package C States for VR domains based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRate[5]; + +/** Offset 0x0603 +**/ + UINT8 UnusedUpdSpace30[1]; + +/** Offset 0x0604 - Thermal Design Current current limit + PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. + Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes +**/ + UINT16 TdcCurrentLimit[5]; + +/** Offset 0x060E - AcLoadline + PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249. <b>Intel Recommended Defaults vary by domain and SKU. +**/ + UINT16 AcLoadline[5]; + +/** Offset 0x0618 - DcLoadline + PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b> +**/ + UINT16 DcLoadline[5]; + +/** Offset 0x0622 - Power State 1 Threshold current + PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi1Threshold[5]; + +/** Offset 0x062C - Power State 2 Threshold current + PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi2Threshold[5]; + +/** Offset 0x0636 - Power State 3 Threshold current + PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi3Threshold[5]; + +/** Offset 0x0640 - Icc Max limit + PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A +**/ + UINT16 IccMax[5]; + +/** Offset 0x064A - Enable VR specific mailbox command + VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A + VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific + command sent for PS4 exit issue. 11b - Reserved. + $EN_DIS +**/ + UINT8 SendVrMbxCmd; + +/** Offset 0x064B - Enable or Disable TXT + Enable or Disable TXT; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x064C - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. </b>0: Initialize; <b>1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x064D +**/ + UINT8 UnusedUpdSpace31; + +/** Offset 0x064E - FIVR RFI Frequency + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0: + Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; + 0-1535 (Up to 153.5MHz) for 19MHz clock. +**/ + UINT16 FivrRfiFrequency; + +/** Offset 0x0650 - FIVR RFI Spread Spectrum + PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>; + Range: 0.0% to 10.0% (0-100). +**/ + UINT8 FivrSpreadSpectrum; + +/** Offset 0x0651 +**/ + UINT8 UnusedUpdSpace32[3]; + +/** Offset 0x0654 - UFS Soft Strap Start Address + UFS Soft Strap Start Address, Value will be based on the CSE IFWI Layout +**/ + UINT32 UfsStrapAddress; + +/** Offset 0x0658 - CpuBistData + Pointer CPU BIST Data +**/ + UINT32 CpuBistData; + +/** Offset 0x065C - CpuMpPpi + <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. + If not NULL, FSP will use the boot loader's implementation of multiprocessing. + See section 5.1.4 of the FSP Integration Guide for more details. +**/ + UINT32 CpuMpPpi; + +/** Offset 0x0660 - CpuMpHob + <b>Optional</b> pointer for CpuMpHob. If the boot loader is a UEFI boot loader using + API mode instead of dispatch mode, and FspsUpd->FspsConfig.CpuMpPpi != NULL, then + FspsUpd->FspsConfig.CpuMpHob must be != NULL. See section 5.1.4 of the FSP Integration + Guide for more details. +**/ + UINT32 CpuMpHob; + +/** Offset 0x0664 +**/ + UINT8 CpuPostMemRsvd[16]; + +/** Offset 0x0674 - PpinSupport to view Protected Processor Inventory Number + Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this + flag is set) for PPIN Support + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x0675 - Enable or Disable Minimum Voltage Override + Enable or disable Minimum Voltage overrides ; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 EnableMinVoltageOverride; + +/** Offset 0x0676 - Min Voltage for Runtime + PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride + = 1. Range 0 to 1999mV. <b> 0: 0mV </b> +**/ + UINT16 MinVoltageRuntime; + +/** Offset 0x0678 - Base of memory region allocated for Processor Trace + Base address of memory region allocated for Processor Trace. Processor Trace requires + 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b> +**/ + UINT64 ProcessorTraceMemBase; + +/** Offset 0x0680 - Memory region allocation for Processor Trace + Length in bytes of memory region allocated for Processor Trace. Processor Trace + requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b> +**/ + UINT32 ProcessorTraceMemLength; + +/** Offset 0x0684 - Min Voltage for C8 + PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = + 1. Range 0 to 1999mV. <b> 0: 0mV </b> +**/ + UINT16 MinVoltageC8; + +/** Offset 0x0686 - Smbios Type4 Max Speed Override + Provide the option for platform to override the MaxSpeed field of Smbios Type 4. + If this value is not zero, it dominates the field. +**/ + UINT16 SmbiosType4MaxSpeedOverride; + +/** Offset 0x0688 - ReservedCpuPostMemProduction + Reserved for CPU Post-Mem Production + $EN_DIS +**/ + UINT8 ReservedCpuPostMemProduction[6]; + +/** Offset 0x068E - AC Split Lock + Enable/Disable #AC check on split lock. <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 AcSplitLock; + +/** Offset 0x068F - PCH Master Clock Gating Control + Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default + $EN_DIS +**/ + UINT8 PchMasterClockGating; + +/** Offset 0x0690 - PCH Master Power Gating Control + Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default + $EN_DIS +**/ + UINT8 PchMasterPowerGating; + +/** Offset 0x0691 - Sci Pin Mux Enable + Enable/Disable Sci Gpio Pin Mux. <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 SciPinMuxEnable; + +/** Offset 0x0692 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x0693 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x0698 - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x069D +**/ + UINT8 UnusedUpdSpace33[1]; + +/** Offset 0x069E - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x06A8 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x06B2 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x06B3 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x06B4 - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd4[3]; + +/** Offset 0x06B7 - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x06B8 - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x06B9 +**/ + UINT8 UnusedUpdSpace34[3]; + +/** Offset 0x06BC - PCH PSE Log Output Channel + Set PSE Log Output Channel. 0: internal memory; 1-6: UART channels; Other: shut down +**/ + UINT32 PchPseLogOutputChannel; + +/** Offset 0x06C0 - PCH PSE Log Output Size + Set PSE Log Output Size +**/ + UINT16 PchPseLogOutputSize; + +/** Offset 0x06C2 - PCH PSE Log Output Offset + Set PSE Log Output Offset +**/ + UINT16 PchPseLogOutputOffset; + +/** Offset 0x06C4 - PCH PSE OOB Prov State Offset + Set PSE OOB Prov State Offset +**/ + UINT16 PchPseOobProvDone; + +/** Offset 0x06C6 - Enable PCH PSE I2S pins assigned + Set if PSE I2S native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseI2sEnable[2]; + +/** Offset 0x06C8 - PchPseI2sTxPinMux + Select PSE I2S Tx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_TXD* for possible values. +**/ + UINT32 PchPseI2sTxPinMux[2]; + +/** Offset 0x06D0 - PchPseI2sRxPinMux + Select PSE I2S Rx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_RXD* for possible values. +**/ + UINT32 PchPseI2sRxPinMux[2]; + +/** Offset 0x06D8 - PchPseI2sSfrmPinMux + Select PSE I2S Sfrm pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SFRM* for possible values. +**/ + UINT32 PchPseI2sSfrmPinMux[2]; + +/** Offset 0x06E0 - PchPseI2sSclkPinMux + Select PSE I2S Sclk pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SCLK* for possible values. +**/ + UINT32 PchPseI2sSclkPinMux[2]; + +/** Offset 0x06E8 - Enable PCH PSE PWM pins assigned + Set if PSE PWM native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPsePwmEnable; + +/** Offset 0x06E9 - PchPsePwmPinEnable + Set PWM pin to PSE PWM native function. 0: Disable; 1: Enable. +**/ + UINT8 PchPsePwmPinEnable[16]; + +/** Offset 0x06F9 +**/ + UINT8 UnusedUpdSpace35[3]; + +/** Offset 0x06FC - PchPsePwmPinMux + Select PSE Pwm pin muxing start from PWM0 to PWM15. Refer to GPIO_*_MUXING_PSE_PWM* + for possible values. +**/ + UINT32 PchPsePwmPinMux[16]; + +/** Offset 0x073C - Enable PCH PSE UART pins assigned + Set if PSE UART native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseUartEnable[6]; + +/** Offset 0x0742 - Enable PCH PSE HSUART pins assigned + Set if PSE HSUART native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseHsuartEnable[4]; + +/** Offset 0x0746 - Enable PCH PSE QEP pins assigned + Set if PSE QEP native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseQepEnable[4]; + +/** Offset 0x074A - Enable PCH PSE DMA pins assigned + Set if PSE DMA native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseDmaEnable[3]; + +/** Offset 0x074D - Enable PCH PSE GBE pins assigned + Set if PSE GBE native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseGbeEnable[2]; + +/** Offset 0x074F - Enable PCH PSE I2C pins assigned + Set if PSE I2C native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseI2cEnable[8]; + +/** Offset 0x0757 - Enable PCH PSE SPI pins assigned + Set if PSE SPI native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseSpiEnable[4]; + +/** Offset 0x075B - Enable PCH PSE SPI CS0 pins assigned + Set if PSE SPI CS0 pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseSpiCs0Enable[4]; + +/** Offset 0x075F - Enable PCH PSE SPI CS1 pins assigned + Set if PSE SPI CS1 pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseSpiCs1Enable[4]; + +/** Offset 0x0763 +**/ + UINT8 UnusedUpdSpace36[1]; + +/** Offset 0x0764 - PchPseSpiMosiPinMux + Select PSE Spi Mosi pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MOSI* for possible values. +**/ + UINT32 PchPseSpiMosiPinMux[4]; + +/** Offset 0x0774 - PchPseSpiMisoPinMux + Select PSE Spi Miso pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MISO* for possible values. +**/ + UINT32 PchPseSpiMisoPinMux[4]; + +/** Offset 0x0784 - PchPseSpiClkPinMux + Select PSE Spi Clk pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_SCLK* for possible values. +**/ + UINT32 PchPseSpiClkPinMux[4]; + +/** Offset 0x0794 - PchPseSpiCs0PinMux + Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values. +**/ + UINT32 PchPseSpiCs0PinMux[4]; + +/** Offset 0x07A4 - PchPseSpiCs1PinMux + Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values. +**/ + UINT32 PchPseSpiCs1PinMux[4]; + +/** Offset 0x07B4 - Enable PCH PSE ADC pins assigned + Set if PSE ADC native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseAdcEnable; + +/** Offset 0x07B5 - Enable PCH PSE CAN pins assigned + Set if PSE CAN native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseCanEnable[2]; + +/** Offset 0x07B7 - Enable PCH PSE I2S sideband interrupt + Set if PSE I2S are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseI2sSbInterruptEnable[2]; + +/** Offset 0x07B9 - Enable PCH PSE PWM sideband interrupt + Set if PSE PWM are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPsePwmSbInterruptEnable; + +/** Offset 0x07BA - Enable PCH PSE UART sideband interrupt + Set if PSE UART are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseUartSbInterruptEnable[6]; + +/** Offset 0x07C0 - Enable PCH PSE QEP sideband interrupt + Set if PSE QEP are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseQepSbInterruptEnable[4]; + +/** Offset 0x07C4 - Enable PCH PSE DMA sideband interrupt + Set if PSE DMA are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseDmaSbInterruptEnable[3]; + +/** Offset 0x07C7 - Enable PCH PSE I2C sideband interrupt + Set if PSE I2C are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseI2cSbInterruptEnable[8]; + +/** Offset 0x07CF - Enable PCH PSE SPI sideband interrupt + Set if PSE SPI are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseSpiSbInterruptEnable[4]; + +/** Offset 0x07D3 - Enable PCH PSE ADC sideband interrupt + Set if PSE ADC are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseAdcSbInterruptEnable; + +/** Offset 0x07D4 - Enable PCH PSE LH2OSE sideband interrupt + Set if PSE LH2OSE are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseLh2PseSbInterruptEnable; + +/** Offset 0x07D5 - Enable PCH PSE CAN sideband interrupt + Set if PSE CAN are to be set to sideband interrupt. 0: Disable; 1: Enable. +**/ + UINT8 PchPseCanSbInterruptEnable[2]; + +/** Offset 0x07D7 - Enable PCH PSE Timed GPIO pins assigned + Set if PSE Timed GPIO native pins and ownership are to be enabled by BIOS. 0: Disable/pins + are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; + 2: Pins are muxed to PSE IP, the IO is owned by host; +**/ + UINT8 PchPseTimedGpioEnable[2]; + +/** Offset 0x07D9 - Enable PCH PSE Timed GPIO 20 pins allocation + Allocate 20 pins for PCH PSE Timed GPIO. 0: Top 20 pins; 1: Mid 20 pins; 2: Lower 20 pins. +**/ + UINT8 PchPseTimedGpioPinAllocation[2]; + +/** Offset 0x07DB - Enable PCH PSE Timed GPIO Pin to PSE TGPIO native function + Set TGPIO pin to PSE TGPIO native function. 0: Disable; 1: Enable. +**/ + UINT8 PchPseTimedGpioPinEnable[60]; + +/** Offset 0x0817 +**/ + UINT8 UnusedUpdSpace37; + +/** Offset 0x0818 - Pch Pse Tgpio6 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio6PinMux; + +/** Offset 0x081C - Pch Pse Tgpio7 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio7PinMux; + +/** Offset 0x0820 - Pch Pse Tgpio8 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio8PinMux; + +/** Offset 0x0824 - Pch Pse Tgpio9 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio9PinMux; + +/** Offset 0x0828 - Pch Pse Tgpio10 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio10PinMux; + +/** Offset 0x082C - Pch Pse Tgpio11 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio11PinMux; + +/** Offset 0x0830 - Pch Pse Tgpio12 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio12PinMux; + +/** Offset 0x0834 - Pch Pse Tgpio13 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio13PinMux; + +/** Offset 0x0838 - Pch Pse Tgpio14 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio14PinMux; + +/** Offset 0x083C - Pch Pse Tgpio15 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio15PinMux; + +/** Offset 0x0840 - Pch Pse Tgpio16 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio16PinMux; + +/** Offset 0x0844 - Pch Pse Tgpio17 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio17PinMux; + +/** Offset 0x0848 - Pch Pse Tgpio18 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio18PinMux; + +/** Offset 0x084C - Pch Pse Tgpio19 Pin Mux + Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. +**/ + UINT32 PchPseTgpio19PinMux; + +/** Offset 0x0850 - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x0851 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x0852 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x0853 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS +**/ + UINT8 RtcBiosInterfaceLock; + +/** Offset 0x0854 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0855 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[24]; + +/** Offset 0x086D - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[24]; + +/** Offset 0x0885 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[24]; + +/** Offset 0x089D - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[24]; + +/** Offset 0x08B5 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[24]; + +/** Offset 0x08CD - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[24]; + +/** Offset 0x08E5 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[24]; + +/** Offset 0x08FD - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[24]; + +/** Offset 0x0915 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[24]; + +/** Offset 0x092D - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[24]; + +/** Offset 0x0945 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[24]; + +/** Offset 0x095D - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[24]; + +/** Offset 0x0975 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[24]; + +/** Offset 0x098D - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 +**/ + UINT8 ThcPort0Assignment; + +/** Offset 0x098E +**/ + UINT8 UnusedUpdSpace38[2]; + +/** Offset 0x0990 - THC Port 0 Interrupt Pin Mux + Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort0InterruptPinMuxing; + +/** Offset 0x0994 - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x0995 - Touch Host Controller Port 1 ReadFrequency + Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz + 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz +**/ + UINT8 ThcPort1ReadFrequency; + +/** Offset 0x0996 - Touch Host Controller Port 1 WriteFrequency + Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz + 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz +**/ + UINT8 ThcPort1WriteFrequency; + +/** Offset 0x0997 +**/ + UINT8 UnusedUpdSpace39; + +/** Offset 0x0998 - THC Port 1 Interrupt Pin Mux + Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort1InterruptPinMuxing; + +/** Offset 0x099C - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCH_PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[24]; + +/** Offset 0x09B4 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[24]; + +/** Offset 0x09CC - PCIE RP Completion Timeout + The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[24]; + +/** Offset 0x09E4 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[24]; + +/** Offset 0x09FC - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[24]; + +/** Offset 0x0A14 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[24]; + +/** Offset 0x0A2C - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[24]; + +/** Offset 0x0A44 - PCIe override default settings for EQ + Choose PCIe EQ method + $EN_DIS +**/ + UINT8 PcieEqOverrideDefault; + +/** Offset 0x0A45 - PCIe choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieEqMethod; + +/** Offset 0x0A46 - PCIe choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieEqMode; + +/** Offset 0x0A47 - PCIe EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieEqLocalTransmitterOverrideEnable; + +/** Offset 0x0A48 - PCIe number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; + +/** Offset 0x0A49 - PCIe pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PreCursorList[10]; + +/** Offset 0x0A53 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PostCursorList[10]; + +/** Offset 0x0A5D - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PresetList[11]; + +/** Offset 0x0A68 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT32 PcieEqPh1DownstreamPortTransmitterPreset; + +/** Offset 0x0A6C - PCIe EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT32 PcieEqPh1UpstreamPortTransmitterPreset; + +/** Offset 0x0A70 - PCIe EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieEqPh2LocalTransmitterOverridePreset; + +/** Offset 0x0A71 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite; + +/** Offset 0x0A72 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x0A73 - PCI Express Clock Gating + Enable/Disable Clock Gating, 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 TestPcieClockGating; + +/** Offset 0x0A74 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x0A75 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 CpuPcieGen3ProgramStaticEq; + +/** Offset 0x0A76 - Enable/Disable GEN4 Static EQ Phase1 programming + Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 CpuPcieGen4ProgramStaticEq; + +/** Offset 0x0A77 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x0A78 - PCIE IMR + Enables Isolated Memory Region for PCIe. + $EN_DIS +**/ + UINT8 PcieRpImrEnabled; + +/** Offset 0x0A79 - PCIE IMR port number + Selects PCIE root port number for IMR feature. +**/ + UINT8 PcieRpImrSelection; + +/** Offset 0x0A7A - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x0A7B - PCH Pm Pcie Wake From DeepSx + Determine if enable PCIe to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmPcieWakeFromDeepSx; + +/** Offset 0x0A7C - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x0A7D - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x0A7E - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x0A7F - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + UINT8 PchPmDeepSxPol; + +/** Offset 0x0A80 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x0A81 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x0A82 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x0A83 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x0A84 - USB Overcurrent Override for DbC + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when DbC is used to avoid signaling conflicts. + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x0A85 - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x0A86 - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x0A87 - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x0A88 - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + UINT8 PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x0A89 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x0A8A - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x0A8B - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x0A8C - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x0A8D - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x0A8E - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x0A8F - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x0A90 - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + UINT8 EsataSpeedLimit; + +/** Offset 0x0A91 - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + UINT8 SataSpeedLimit; + +/** Offset 0x0A92 - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x0A9A - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + UINT8 SataPortsInterlockSw[8]; + +/** Offset 0x0AA2 - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x0AAA - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x0AB2 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x0ABA - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x0AC2 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x0ACA - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x0ADA - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + UINT8 SataPortsZpOdd[8]; + +/** Offset 0x0AE2 - Enable SATA Port RxPolarity + Reverse RxPolarity. +**/ + UINT8 SataPortsRxPolarity[8]; + +/** Offset 0x0AEA - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + UINT8 SataRstRaidDeviceId; + +/** Offset 0x0AEB - PCH Sata Rst Raid0 + RAID0. + $EN_DIS +**/ + UINT8 SataRstRaid0; + +/** Offset 0x0AEC - PCH Sata Rst Raid1 + RAID1. + $EN_DIS +**/ + UINT8 SataRstRaid1; + +/** Offset 0x0AED - PCH Sata Rst Raid10 + RAID10. + $EN_DIS +**/ + UINT8 SataRstRaid10; + +/** Offset 0x0AEE - PCH Sata Rst Raid5 + RAID5. + $EN_DIS +**/ + UINT8 SataRstRaid5; + +/** Offset 0x0AEF - PCH Sata Rst Irrt + Intel Rapid Recovery Technology. + $EN_DIS +**/ + UINT8 SataRstIrrt; + +/** Offset 0x0AF0 - PCH Sata Rst Orom Ui Banner + OROM UI and BANNER. + $EN_DIS +**/ + UINT8 SataRstOromUiBanner; + +/** Offset 0x0AF1 - PCH Sata Rst Orom Ui Delay + 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). +**/ + UINT8 SataRstOromUiDelay; + +/** Offset 0x0AF2 - PCH Sata Rst Hdd Unlock + Indicates that the HDD password unlock in the OS is enabled. + $EN_DIS +**/ + UINT8 SataRstHddUnlock; + +/** Offset 0x0AF3 - PCH Sata Rst Led Locate + Indicates that the LED/SGPIO hardware is attached and ping to locate feature is + enabled on the OS. + $EN_DIS +**/ + UINT8 SataRstLedLocate; + +/** Offset 0x0AF4 - PCH Sata Rst Irrt Only + Allow only IRRT drives to span internal and external ports. + $EN_DIS +**/ + UINT8 SataRstIrrtOnly; + +/** Offset 0x0AF5 - PCH Sata Rst Smart Storage + RST Smart Storage caching Bit. + $EN_DIS +**/ + UINT8 SataRstSmartStorage; + +/** Offset 0x0AF6 - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + UINT8 SataRstPcieEnable[3]; + +/** Offset 0x0AF9 - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + UINT8 SataRstPcieStoragePort[3]; + +/** Offset 0x0AFC - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + UINT8 SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x0AFF - UFS enable/disable + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x0B01 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable +**/ + UINT8 IehMode; + +/** Offset 0x0B02 - PSF Tcc + Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency + by disable some psf power management features, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PsfTccEnable; + +/** Offset 0x0B03 - TCC Mode Default Flag + Variable to determine TCC mode default value, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 TccModeInitFlag; + +/** Offset 0x0B04 - Tcc Tuning enable/disable + Tcc (Time Coordinated Computing) Tuning Enabled + $EN_DIS +**/ + UINT8 TccTuningEnable; + +/** Offset 0x0B05 +**/ + UINT8 UnusedUpdSpace40[3]; + +/** Offset 0x0B08 - Tcc Register File Base Address + Tcc (Time Coordinated Computing) Register File Base Address +**/ + UINT32 TccConfigBase; + +/** Offset 0x0B0C - Tcc Register File Size + Tcc (Time Coordinated Computing) Register File Size +**/ + UINT32 TccConfigSize; + +/** Offset 0x0B10 - Fusa Display Configuration + Fusa (Functional Safety) Enable Fusa Feature on Display, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 DisplayFusaConfigEnable; + +/** Offset 0x0B11 - Fusa Graphics Configuration + Fusa (Functional Safety) Enable Fusa Feature on Graphics, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 GraphicFusaConfigEnable; + +/** Offset 0x0B12 - Fusa Opio Configuration + Fusa (Functional Safety) Enable Fusa Feature on Opio, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 OpioFusaConfigEnable; + +/** Offset 0x0B13 - Fusa Psf Configuration + Fusa (Functional Safety) Enable Fusa Feature on Psf, 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PsfFusaConfigEnable; + +/** Offset 0x0B14 - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x0B16 - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x0B18 - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x0B1A - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x0B1B - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x0B1C - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x0B1D - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 TTSuggestedSetting; + +/** Offset 0x0B1E - Enable PCH Cross Throttling + Enable/Disable PCH Cross Throttling + $EN_DIS +**/ + UINT8 TTCrossThrottling; + +/** Offset 0x0B1F - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + UINT8 PchDmiTsawEn; + +/** Offset 0x0B20 - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + UINT8 DmiSuggestedSetting; + +/** Offset 0x0B21 - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS0TW; + +/** Offset 0x0B22 - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS1TW; + +/** Offset 0x0B23 - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS2TW; + +/** Offset 0x0B24 - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS3TW; + +/** Offset 0x0B25 - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x0B26 - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x0B27 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x0B28 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x0B29 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x0B2A - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x0B2B - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x0B2C - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x0B2D - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x0B2E - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x0B2F - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x0B30 - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x0B31 - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x0B32 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. + $EN_DIS +**/ + UINT8 PchMemoryThrottlingEnable; + +/** Offset 0x0B33 - Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPmsyncEnable[2]; + +/** Offset 0x0B35 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryC0TransmitEnable[2]; + +/** Offset 0x0B37 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPinSelection[2]; + +/** Offset 0x0B39 +**/ + UINT8 UnusedUpdSpace41; + +/** Offset 0x0B3A - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x0B3C - Enable xHCI Compliance Mode + Compliance Mode can be enabled for testing through this option but this is disabled + by default. + $EN_DIS +**/ + UINT8 PchEnableComplianceMode; + +/** Offset 0x0B3D - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x0B4D - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0B57 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x0B58 - USB Clock Gating Enable + Enable or disable USB clock gating + $EN_DIS +**/ + UINT8 UsbClockGatingEnable; + +/** Offset 0x0B59 - USB Power Gating Enable + Enable or disable USB power gating + $EN_DIS +**/ + UINT8 UsbPowerGatingEnable; + +/** Offset 0x0B5A - USB3 LINK SPEED + Set USB3 LINK SPEED=0 for GEN2, Set USB3 LINK SPEED=1 for GEN1 +**/ + UINT8 USB3LinkSpeed; + +/** Offset 0x0B5B +**/ + UINT8 UnusedUpdSpace42; + +/** Offset 0x0B5C - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x0B60 - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x0B64 - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x0B68 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x0B69 - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x0B6A - PCH Sata Rst Optane Memory + Optane Memory + $EN_DIS +**/ + UINT8 SataRstOptaneMemory; + +/** Offset 0x0B6B - PCH Sata Rst CPU Attached Storage + CPU Attached Storage + $EN_DIS +**/ + UINT8 SataRstCpuAttachedStorage; + +/** Offset 0x0B6C - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x0B6D - Enable Timed GPIO 0. + When FALSE, it disables Timed GPIO 0. + $EN_DIS +**/ + UINT8 EnableTimedGpio0; + +/** Offset 0x0B6E - Enable Timed GPIO 1. + When FALSE, it disables Timed GPIO 1. + $EN_DIS +**/ + UINT8 EnableTimedGpio1; + +/** Offset 0x0B6F - Enable VNN Voltage Raise. + When TRUE, it enable VNN Voltage Raise. + $EN_DIS +**/ + UINT8 EnableVnnVoltageRaise; + +/** Offset 0x0B70 - BgpdtHash[4] + BgpdtHash values +**/ + UINT64 BgpdtHash[4]; + +/** Offset 0x0B90 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x0B94 +**/ + UINT8 UnusedUpdSpace43[4]; + +/** Offset 0x0B98 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x0BA0 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + UINT64 SendEcCmd; + +/** Offset 0x0BA8 - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + UINT8 EcCmdProvisionEav; + +/** Offset 0x0BA9 - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + UINT8 EcCmdLock; + +/** Offset 0x0BAA - Si Config CSM Flag. + Platform specific common policies that used by several silicon components. CSM status flag. + $EN_DIS +**/ + UINT8 SiCsmFlag; + +/** Offset 0x0BAB - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS +**/ + UINT8 SiSkipSsidProgramming; + +/** Offset 0x0BAC - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x0BAE - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; + +/** Offset 0x0BB0 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. This is + only valid when SkipSsidProgramming is FALSE. +**/ + UINT32 SiSsidTablePtr; + +/** Offset 0x0BB4 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. + This is only valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x0BB6 +**/ + UINT8 SiPostMemRsvd[16]; + +/** Offset 0x0BC6 - SATA RST Interrupt Mode + Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. + 0:Msix, 1:Msi, 2:Legacy +**/ + UINT8 SataRstInterrupt; + +/** Offset 0x0BC7 - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x0BC8 - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0BC9 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0BCA - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b> + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x0BCB - PchDmiCwbEnable + Central Write Buffer feature configurable and disabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x0BCC - OS IDLE Mode Enable + Enable/Disable OS Idle Mode + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x0BCD - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS +**/ + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x0BCE - Global Reset TSC Enable + Enable/Disable PMC Global Reset Three Strike Counter feature. If enabled, PMC will + keep the platform in S5 after the third consecutive type 7 global reset occurs + during boot flow + $EN_DIS +**/ + UINT8 PmcGrTscEnable; + +/** Offset 0x0BCF - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x0BD0 - PCIE Eq Ph3 Lane Param Cm + CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieEqPh3LaneParamCm[32]; + +/** Offset 0x0BF0 - PCIE Eq Ph3 Lane Param Cp + CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieEqPh3LaneParamCp[32]; + +/** Offset 0x0C10 - PCIE Hw Eq Gen3 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieHwEqGen3CoeffListCm[5]; + +/** Offset 0x0C15 - PCIE Hw Eq Gen3 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieHwEqGen3CoeffListCp[5]; + +/** Offset 0x0C1A - PCIE Hw Eq Gen4 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieHwEqGen4CoeffListCm[5]; + +/** Offset 0x0C1F - PCIE Hw Eq Gen4 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieHwEqGen4CoeffListCp[5]; + +/** Offset 0x0C24 - Gen3 Root port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen3RootPortPreset[20]; + +/** Offset 0x0C38 - Pcie Gen4 Root port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen4RootPortPreset[20]; + +/** Offset 0x0C4C - Pcie Gen3 End port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen3EndPointPreset[20]; + +/** Offset 0x0C60 - Pcie Gen4 End port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen4EndPointPreset[20]; + +/** Offset 0x0C74 - Pcie Gen3 End port Hint values per lane + Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen3EndPointHint[20]; + +/** Offset 0x0C88 - Pcie Gen4 End port Hint values per lane + Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen4EndPointHint[20]; + +/** Offset 0x0C9C - Skip Cpu Fia Programming + Skip Fia configuration and lock if enable. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuPcieSkipCpuFiaProgramming; + +/** Offset 0x0C9D - PCIE Disable RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuPcieDisableRootPortClockGating; + +/** Offset 0x0C9E - PCIE Disable RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuPcieDisableRootPortPowerGating; + +/** Offset 0x0C9F - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 CpuPcieComplianceTestMode; + +/** Offset 0x0CA0 - PCIE Secure Register Lock + Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, + load CpuPcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 CpuPcieSetSecuredRegisterLock; + +/** Offset 0x0CA1 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 CpuPcieEnablePeerMemoryWrite; + +/** Offset 0x0CA2 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 CpuPcieRpFunctionSwap; + +/** Offset 0x0CA3 +**/ + UINT8 UnusedUpdSpace44; + +/** Offset 0x0CA4 - Pch PCIE device override table pointer + The PCIe device table is being used to override PCIe device ASPM settings. This + is a pointer points to a 32bit address. And it's only used in PostMem phase. Please + refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId + must be 0. +**/ + UINT32 CpuPcieDeviceOverrideTablePtr; + +/** Offset 0x0CA8 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 CpuPcieRpHotPlug[4]; + +/** Offset 0x0CAC - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 CpuPcieRpPmSci[4]; + +/** Offset 0x0CB0 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 CpuPcieRpTransmitterHalfSwing[4]; + +/** Offset 0x0CB4 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 CpuPcieRpAcsEnabled[4]; + +/** Offset 0x0CB8 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 CpuPcieRpEnableCpm[4]; + +/** Offset 0x0CBC - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 CpuPcieRpAdvancedErrorReporting[4]; + +/** Offset 0x0CC0 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 CpuPcieRpUnsupportedRequestReport[4]; + +/** Offset 0x0CC4 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpFatalErrorReport[4]; + +/** Offset 0x0CC8 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpNoFatalErrorReport[4]; + +/** Offset 0x0CCC - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 CpuPcieRpCorrectableErrorReport[4]; + +/** Offset 0x0CD0 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnFatalError[4]; + +/** Offset 0x0CD4 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; + +/** Offset 0x0CD8 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; + +/** Offset 0x0CDC - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 CpuPcieRpMaxPayload[4]; + +/** Offset 0x0CE0 - DPC for PCIE RP Mask + Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcEnabled[4]; + +/** Offset 0x0CE4 - DPC Extensions PCIE RP Mask + Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcExtensionsEnabled[4]; + +/** Offset 0x0CE8 - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 CpuPcieRpSlotImplemented[4]; + +/** Offset 0x0CEC - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen3EqPh3Method[4]; + +/** Offset 0x0CF0 - PCIE RP Gen4 Equalization Phase Method + PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen4EqPh3Method[4]; + +/** Offset 0x0CF4 - Phase3 RP Gen3 EQ enable + Phase3 Gen3 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase + 3, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 CpuPcieRpGen3EqPh3Enable[4]; + +/** Offset 0x0CF8 - Phase3 RP Gen4 EQ enable + Phase3 Gen4 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase + 3, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 CpuPcieRpGen4EqPh3Enable[4]; + +/** Offset 0x0CFC - Phase2-3 RP Gen3 EQ enable + Phase2-3 Gen3 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3, + Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 CpuPcieRpGen3EqPh23Enable[4]; + +/** Offset 0x0D00 - Phase2-3 RP Gen4 EQ enable + Phase2-3 Gen4 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3, + Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 CpuPcieRpGen4EqPh23Enable[4]; + +/** Offset 0x0D04 - PCET Timer + Preset/Coefficient Evaluation Timeout. See CPU_PCIE_PCET. Default is 0x4 +**/ + UINT8 CpuPciePcetTimer[4]; + +/** Offset 0x0D08 - Gen3 Preset/Coeffiecient List Count + Select Gen3 Hardware Autonomous Preset/Coefficient Count. See Gen3 CPU_PCIE_PRESETCOEFF_LIST. + Default is 0x3 +**/ + UINT8 Gen3CpuPciePresetCoeffList[4]; + +/** Offset 0x0D0C - Gen4 Preset/Coeffiecient List Count + Select Gen4 Hardware Autonomous Preset/Coefficient Count. See CPU_PCIE_PRESETCOEFF_LIST. + Default is 0x3 +**/ + UINT8 Gen4CpuPciePresetCoeffList[4]; + +/** Offset 0x0D10 - Presets/Coefficients Evaluation for Gen3 + 8.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See + CPU_PCIE_PX8GTSWLPCE. Default is 0x3 +**/ + UINT8 CpuPciePx8gtswlpce[4]; + +/** Offset 0x0D14 - Presets/Coefficients Evaluation for Gen4 + 16.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See + CPU_PCIE_PX16GTSWLPCE. Default is 0x4 +**/ + UINT8 CpuPciePx16gtswlpce[4]; + +/** Offset 0x0D18 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 CpuPcieRpPhysicalSlotNumber[4]; + +/** Offset 0x0D1C - PCIE RP Aspm + The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is + CpuPcieAspmAutoConfig. +**/ + UINT8 CpuPcieRpAspm[4]; + +/** Offset 0x0D20 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). + Default is CpuPcieL1SubstatesDisabled. +**/ + UINT8 CpuPcieRpL1Substates[4]; + +/** Offset 0x0D24 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 CpuPcieRpLtrEnable[4]; + +/** Offset 0x0D28 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 CpuPcieRpLtrConfigLock[4]; + +/** Offset 0x0D2C - PTM for PCIE RP Mask + Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpPtmEnabled[4]; + +/** Offset 0x0D30 - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 CpuPcieRpDetectTimeoutMs[4]; + +/** Offset 0x0D38 - VC for PCIE RP Mask + Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpVcEnabled[4]; + +/** Offset 0x0D3C - Force GT CLOS on LLC for Real Time Performance + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 GtClosEnable; + +/** Offset 0x0D3D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x0D47 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default + = 4Ch</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x0D51 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x0D5B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + <b>Default = 4Ch</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x0D65 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x0D6F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + <b>Default = 4Ch</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x0D79 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x0D83 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + <b>Default = 4Ch</b>. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x0D8D - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x0D8E - EDRAM Test Mode + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode +**/ + UINT8 EdramTestMode; + +/** Offset 0x0D8F - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x0D90 - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0D91 - Enable/Disable CdynmaxClamp + Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp + $EN_DIS +**/ + UINT8 CdynmaxClampEnable; + +/** Offset 0x0D92 - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x0D93 - Disable Turbo GT + 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency + $EN_DIS +**/ + UINT8 DisableTurboGt; + +/** Offset 0x0D94 - Enable/Disable CdClock Init + Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full + CD clock if not initialized by Gfx PEIM + $EN_DIS +**/ + UINT8 SkipCdClockInit; + +/** Offset 0x0D95 +**/ + UINT8 UnusedUpdSpace45[3]; + +/** Offset 0x0D98 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x0D9C - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x0DA0 - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + UINT8 SaPostMemTestRsvd[6]; + +/** Offset 0x0DA6 - RSR feature + Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b> + $EN_DIS +**/ + UINT8 EnableRsr; + +/** Offset 0x0DA7 - 1-Core Ratio Limit + 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal + to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 +**/ + UINT8 OneCoreRatioLimit; + +/** Offset 0x0DA8 - 2-Core Ratio Limit + 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 TwoCoreRatioLimit; + +/** Offset 0x0DA9 - 3-Core Ratio Limit + 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 ThreeCoreRatioLimit; + +/** Offset 0x0DAA - 4-Core Ratio Limit + 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 FourCoreRatioLimit; + +/** Offset 0x0DAB - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x0DAC - Hardware Duty Cycle Control + Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved + $EN_DIS +**/ + UINT8 HdcControl; + +/** Offset 0x0DAD - Package Long duration turbo mode time + Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) + 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x0DAE - Short Duration Turbo Mode + Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x0DAF - Turbo settings Lock + Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x0DB0 - Package PL3 time window + Package PL3 time window range for this policy from 0 to 64ms +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x0DB1 - Package PL3 Duty Cycle + Package PL3 Duty Cycle; Valid Range is 0 to 100 +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x0DB2 - Package PL3 Lock + Package PL3 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x0DB3 - Package PL4 Lock + Package PL4 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x0DB4 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + <b>10</b>, For all other SKUs the recommended default are <b>0</b> +**/ + UINT8 TccActivationOffset; + +/** Offset 0x0DB5 - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>, + For all other SKUs the recommended default are <b>0: Disabled</b>. + $EN_DIS +**/ + UINT8 TccOffsetClamp; + +/** Offset 0x0DB6 - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; <b>0: Disabled</b>; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x0DB7 - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table.Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x0DB8 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 +**/ + UINT8 Custom1PowerLimit1Time; + +/** Offset 0x0DB9 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 +**/ + UINT8 Custom1TurboActivationRatio; + +/** Offset 0x0DBA - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom1ConfigTdpControl; + +/** Offset 0x0DBB - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 +**/ + UINT8 Custom2PowerLimit1Time; + +/** Offset 0x0DBC - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 +**/ + UINT8 Custom2TurboActivationRatio; + +/** Offset 0x0DBD - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom2ConfigTdpControl; + +/** Offset 0x0DBE - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 +**/ + UINT8 Custom3PowerLimit1Time; + +/** Offset 0x0DBF - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 +**/ + UINT8 Custom3TurboActivationRatio; + +/** Offset 0x0DC0 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 +**/ + UINT8 Custom3ConfigTdpControl; + +/** Offset 0x0DC1 - ConfigTdp mode settings Lock + Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x0DC2 - Load Configurable TDP SSDT + Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x0DC3 - PL1 Enable value + PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x0DC4 - PL1 timewindow + PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 + , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x0DC5 - PL2 Enable Value + PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x0DC6 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x0DC7 - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x0DC8 - Enable or Disable Monitor /MWAIT instructions + Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0DC9 - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x0DCA - Check if FUSA is supported + Check if FUSA is supported; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 IsFusaSupported; + +/** Offset 0x0DCB - AP Idle Manner of waiting for SIPI + AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop. + 1: HALT loop, 2: MWAIT loop, 3: RUN loop +**/ + UINT8 ApIdleManner; + +/** Offset 0x0DCC - Control on Processor Trace output scheme + Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x0DCD - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x0DCE - Enable or Disable Intel SpeedStep Technology + Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x0DCF - Enable or Disable Energy Efficient P-state + Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; + <b>1: Enable</b> + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x0DD0 - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; + <b>1: Enable</b> + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x0DD1 - Enable or Disable T states + Enable or Disable T states; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x0DD2 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x0DD3 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 DisableProcHotOut; + +/** Offset 0x0DD4 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 ProcHotResponse; + +/** Offset 0x0DD5 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x0DD6 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 EnableAllThermalFunctions; + +/** Offset 0x0DD7 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x0DD8 - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0DD9 - Configure C-State Configuration Lock + Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x0DDA - Enable or Disable Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x0DDB - Enable or Disable Package Cstate Demotion + Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x0DDC - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x0DDD - Enable or Disable CState-Pre wake + Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x0DDE - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x0DDF - Enable or Disable IO to MWAIT redirection + Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 CstCfgCtrIoMwaitRedirection; + +/** Offset 0x0DE0 - Set the Max Pkg Cstate + Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep + C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , + 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x0DE1 - TimeUnit for C-State Latency Control0 + TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl0TimeUnit; + +/** Offset 0x0DE2 - TimeUnit for C-State Latency Control1 + TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl1TimeUnit; + +/** Offset 0x0DE3 - TimeUnit for C-State Latency Control2 + TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl2TimeUnit; + +/** Offset 0x0DE4 - TimeUnit for C-State Latency Control3 + TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl3TimeUnit; + +/** Offset 0x0DE5 - TimeUnit for C-State Latency Control4 + Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl4TimeUnit; + +/** Offset 0x0DE6 - TimeUnit for C-State Latency Control5 + TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl5TimeUnit; + +/** Offset 0x0DE7 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: + No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x0DE8 - Lock prochot configuration + Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + UINT8 ProcHotLock; + +/** Offset 0x0DE9 - Configuration for boot TDP selection + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP + Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x0DEA - Max P-State Ratio + Max P-State Ratio, Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x0DEB - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x0E13 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x0E23 +**/ + UINT8 UnusedUpdSpace46; + +/** Offset 0x0E24 - Platform Power Pmax + PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. + Range 0-1024 Watts. Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0E26 - Interrupt Response Time Limit of C-State LatencyContol1 + Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl1Irtl; + +/** Offset 0x0E28 - Interrupt Response Time Limit of C-State LatencyContol2 + Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl2Irtl; + +/** Offset 0x0E2A - Interrupt Response Time Limit of C-State LatencyContol3 + Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl3Irtl; + +/** Offset 0x0E2C - Interrupt Response Time Limit of C-State LatencyContol4 + Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl4Irtl; + +/** Offset 0x0E2E - Interrupt Response Time Limit of C-State LatencyContol5 + Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl5Irtl; + +/** Offset 0x0E30 - Package Long duration turbo mode power limit + Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit1; + +/** Offset 0x0E34 - Package Short duration turbo mode power limit + Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x0E38 - Package PL3 power limit + Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit3; + +/** Offset 0x0E3C - Package PL4 power limit + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit4; + +/** Offset 0x0E40 - Tcc Offset Time Window for RATL + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 TccOffsetTimeWindowForRatl; + +/** Offset 0x0E44 - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x0E48 - Long term Power Limit value for custom cTDP level 1 + Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x0E4C - Short term Power Limit value for custom cTDP level 2 + Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit1; + +/** Offset 0x0E50 - Long term Power Limit value for custom cTDP level 2 + Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit2; + +/** Offset 0x0E54 - Short term Power Limit value for custom cTDP level 3 + Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit1; + +/** Offset 0x0E58 - Long term Power Limit value for custom cTDP level 3 + Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit2; + +/** Offset 0x0E5C - Platform PL1 power + Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x0E60 - Platform PL2 power + Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x0E64 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. (RTH is controlled + through MSR 1FC bit 20)Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x0E65 - Set Three Strike Counter Disable + False (default): Three Strike counter will be incremented and True: Prevents Three + Strike counter from incrementing; <b>0: False</b>; 1: True. + 0: False, 1: True +**/ + UINT8 ThreeStrikeCounterDisable; + +/** Offset 0x0E66 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x0E67 - 5-Core Ratio Limit + 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 FiveCoreRatioLimit; + +/** Offset 0x0E68 - 6-Core Ratio Limit + 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 SixCoreRatioLimit; + +/** Offset 0x0E69 - 7-Core Ratio Limit + 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 SevenCoreRatioLimit; + +/** Offset 0x0E6A - 8-Core Ratio Limit + 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 EightCoreRatioLimit; + +/** Offset 0x0E6B - Intel Turbo Boost Max Technology 3.0 + Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b> + $EN_DIS +**/ + UINT8 EnableItbm; + +/** Offset 0x0E6C - Intel Turbo Boost Max Technology 3.0 Driver + Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled + $EN_DIS +**/ + UINT8 EnableItbmDriver; + +/** Offset 0x0E6D - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x0E6E - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x0E6F - Minimum Ring ratio limit override + Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x0E70 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x0E71 - Enable or Disable Per Core P State OS control + Enable or Disable Per Core P State OS control. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 EnablePerCorePState; + +/** Offset 0x0E72 - Enable or Disable HwP Autonomous Per Core P State OS control + Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; <b>1: + Enable</b> + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x0E73 - Enable or Disable HwP Autonomous EPP Grouping + Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x0E74 - Enable or Disable EPB override over PECI + Enable or Disable EPB override over PECI. <b>0: Disable;</b> 1: Enable + $EN_DIS +**/ + UINT8 EnableEpbPeciOverride; + +/** Offset 0x0E75 - Enable or Disable Fast MSR for IA32_HWP_REQUEST + Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b> + $EN_DIS +**/ + UINT8 EnableFastMsrHwpReq; + +/** Offset 0x0E76 - Enable Configurable TDP + Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; + <b>1: Applies to cTDP</b> + $EN_DIS +**/ + UINT8 ApplyConfigTdp; + +/** Offset 0x0E77 - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + UINT8 ReservedCpuPostMemTest[16]; + +/** Offset 0x0E87 +**/ + UINT8 SecurityPostMemRsvd[16]; + +/** Offset 0x0E97 - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x0E98 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0E99 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0E9A - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0E9B - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x0E9C - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x0ECC - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x0EFC - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[24]; + +/** Offset 0x0F14 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x0F2C - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[24]; + +/** Offset 0x0F5C - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; + +/** Offset 0x0F74 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x0F8C - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; + +/** Offset 0x0FBC - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[24]; + +/** Offset 0x0FD4 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[24]; + +/** Offset 0x1004 - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x1005 - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x1006 - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x1007 - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x1008 - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x1009 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. +**/ + UINT8 PmcLpmS0ixSubStateEnableMask; + +/** Offset 0x100A - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x100B +**/ + UINT8 UnusedUpdSpace47[1]; + +/** Offset 0x100C - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; + +/** Offset 0x1014 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; + +/** Offset 0x101C - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x1020 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x1024 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x102C - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x1030 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x1034 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x103C - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Uptp[4]; + +/** Offset 0x1040 - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Dptp[4]; + +/** Offset 0x1044 - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen4Uptp[4]; + +/** Offset 0x1048 - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen4Dptp[4]; + +/** Offset 0x104C - Enable PSE JTAG debug option + Set if to enable JTAG debug feature for PSE. 0: Disable; 1: Enable. +**/ + UINT8 PchPseJtagEnabled; + +/** Offset 0x104D - Enable PSE JTAG pin option + This option is used to enable or disable PSE JTAG pin pad mode. 0: Disable; 1: Enable. +**/ + UINT8 PchPseJtagPinMux; + +/** Offset 0x104E - Enable PSE SHELL option + Set if to enable PSE Shell feature. 0: Disable; 1: Enable. +**/ + UINT8 PchPseShellEnabled; + +/** Offset 0x104F - Enable PSE ECLITE option + Set if to enable PSE Eclite feature. 0: Disable; 1: Enable. +**/ + UINT8 PchPseEcliteEnabled; + +/** Offset 0x1050 - Enable PSE OOB option + Set if to enable PSE OOB feature. 0: Disable; 1: Enable. +**/ + UINT8 PchPseOobEnabled; + +/** Offset 0x1051 - Enable CPU Temperature Read + Set to enable CPU Temperature Read feature. 0: Disable; 1: Enable. +**/ + UINT8 PchCpuTempSensorEnable; + +/** Offset 0x1052 - Enable PSE WoL option + Set if to enable PSE WoL feature. 0: Disable; 1: Enable. +**/ + UINT8 PchPseWoLEnabled; + +/** Offset 0x1053 +**/ + UINT8 ReservedFspsUpd[13]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x1060 +**/ + UINT8 UnusedUpdSpace48[6]; + +/** Offset 0x1066 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h index e66c68c031..5557e6e93c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h @@ -1,202 +1,202 @@ -/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPTUPD_H__
-#define __FSPTUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
- UINT32 CodeRegionBase;
-
-/** Offset 0x002C
-**/
- UINT32 CodeRegionSize;
-
-/** Offset 0x0030
-**/
- UINT8 Reserved[16];
-} FSPT_CORE_UPD;
-
-/** Fsp T Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - PcdSerialIoUartDebugEnable
- Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
- 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
- UINT8 PcdSerialIoUartDebugEnable;
-
-/** Offset 0x0041 - PcdSerialIoUartNumber
- Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
- Core interface, it cannot be used for debug purpose.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 PcdSerialIoUartNumber;
-
-/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
- Select SerialIo Uart Controller mode
- 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 PcdSerialIoUartMode;
-
-/** Offset 0x0043
-**/
- UINT8 UnusedUpdSpace0;
-
-/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
- Set default BaudRate Supported from 0 - default to 6000000
-**/
- UINT32 PcdSerialIoUartBaudRate;
-
-/** Offset 0x0048 - Pci Express Base Address
- Base address to be programmed for Pci Express
-**/
- UINT64 PcdPciExpressBaseAddress;
-
-/** Offset 0x0050 - Pci Express Region Length
- Region Length to be programmed for Pci Express
-**/
- UINT32 PcdPciExpressRegionLength;
-
-/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
- Set default Parity.
- 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
-**/
- UINT8 PcdSerialIoUartParity;
-
-/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
- Set default word length. 0: Default, 5,6,7,8
-**/
- UINT8 PcdSerialIoUartDataBits;
-
-/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
- Set default stop bits.
- 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
-**/
- UINT8 PcdSerialIoUartStopBits;
-
-/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
- Enables UART hardware flow control, CTS and RTS lines.
- 0: Disable, 1:Enable
-**/
- UINT8 PcdSerialIoUartAutoFlow;
-
-/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
- Select RX pin muxing for SerialIo UART used for debug
-**/
- UINT32 PcdSerialIoUartRxPinMux;
-
-/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
- Select TX pin muxing for SerialIo UART used for debug
-**/
- UINT32 PcdSerialIoUartTxPinMux;
-
-/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
- Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
- for possible values.
-**/
- UINT32 PcdSerialIoUartRtsPinMux;
-
-/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
- Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
- for possible values.
-**/
- UINT32 PcdSerialIoUartCtsPinMux;
-
-/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT
- Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
- = SerialIoUartPci.
-**/
- UINT32 PcdSerialIoUartDebugMmioBase;
-
-/** Offset 0x006C - PcdLpcUartDebugEnable
- Enable to initialize LPC Uart device in FSP.
- 0:Disable, 1:Enable
-**/
- UINT8 PcdLpcUartDebugEnable;
-
-/** Offset 0x006D
-**/
- UINT8 UnusedUpdSpace1[7];
-
-/** Offset 0x0074
-**/
- UINT8 ReservedFsptUpd1[20];
-} FSP_T_CONFIG;
-
-/** Fsp T UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPT_CORE_UPD FsptCoreUpd;
-
-/** Offset 0x0040
-**/
- FSP_T_CONFIG FsptConfig;
-
-/** Offset 0x0088
-**/
- UINT8 UnusedUpdSpace2[6];
-
-/** Offset 0x008E
-**/
- UINT16 UpdTerminator;
-} FSPT_UPD;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0030 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +/** Fsp T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0041 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0042 - PcdSerialIoUartMode - FSPT + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 PcdSerialIoUartMode; + +/** Offset 0x0043 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 PcdSerialIoUartBaudRate; + +/** Offset 0x0048 - Pci Express Base Address + Base address to be programmed for Pci Express +**/ + UINT64 PcdPciExpressBaseAddress; + +/** Offset 0x0050 - Pci Express Region Length + Region Length to be programmed for Pci Express +**/ + UINT32 PcdPciExpressRegionLength; + +/** Offset 0x0054 - PcdSerialIoUartParity - FSPT + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 PcdSerialIoUartParity; + +/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 PcdSerialIoUartDataBits; + +/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 PcdSerialIoUartStopBits; + +/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT + Enables UART hardware flow control, CTS and RTS lines. + 0: Disable, 1:Enable +**/ + UINT8 PcdSerialIoUartAutoFlow; + +/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartRxPinMux; + +/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 PcdSerialIoUartTxPinMux; + +/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 PcdSerialIoUartRtsPinMux; + +/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 PcdSerialIoUartCtsPinMux; + +/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 PcdSerialIoUartDebugMmioBase; + +/** Offset 0x006C - PcdLpcUartDebugEnable + Enable to initialize LPC Uart device in FSP. + 0:Disable, 1:Enable +**/ + UINT8 PcdLpcUartDebugEnable; + +/** Offset 0x006D +**/ + UINT8 UnusedUpdSpace1[7]; + +/** Offset 0x0074 +**/ + UINT8 ReservedFsptUpd1[20]; +} FSP_T_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSP_T_CONFIG FsptConfig; + +/** Offset 0x0088 +**/ + UINT8 UnusedUpdSpace2[6]; + +/** Offset 0x008E +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h index 7c6ed2b27c..30d61e60b0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h @@ -1,252 +1,252 @@ -/** @file
- This file contains definitions required for creation of
- Memory S3 Save data, Memory Info data and Memory Platform
- data hobs.
-
- @copyright
- Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License that accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-@par Specification Reference:
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_TRACE_CACHE_TYPE 3
-
-#define MAX_NODE 1
-#define MAX_CH 2
-#define MAX_DIMM 2
-
-///
-/// Host reset states from MRC.
-///
-#define WARM_BOOT 2
-
-#define R_MC_CHNL_RANK_PRESENT 0x7C
-#define B_RANK0_PRS BIT0
-#define B_RANK1_PRS BIT1
-#define B_RANK2_PRS BIT4
-#define B_RANK3_PRS BIT5
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
- UINT8 Major; ///< Major version number
- UINT8 Minor; ///< Minor version number
- UINT8 Rev; ///< Revision number
- UINT8 Build; ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef __MRC_BOOT_MODE__
-#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
- #ifndef INT32_MAX
- #define INT32_MAX (0x7FFFFFFF)
- #endif //INT32_MAX
-typedef enum {
- bmCold, ///< Cold boot
- bmWarm, ///< Warm boot
- bmS3, ///< S3 resume
- bmFast, ///< Fast boot
- MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
- MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
-} MRC_BOOT_MODE;
-#endif //__MRC_BOOT_MODE__
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
-#endif
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 3
-#endif
-
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
- UINT32 tCK; ///< Memory cycle time, in femtoseconds.
- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
- UINT16 Speed; ///< The maximum capable speed of the device, in MHz
- UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
-} CONTROLLER_INFO;
-
-typedef struct {
- UINT64 BaseAddress; ///< Trace Base Address
- UINT64 TotalSize; ///< Total Trace Region of Same Cache type
- UINT8 CacheType; ///< Trace Cache Type
- UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
- UINT8 Rsvd[2];
-} PSMI_MEM_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT16 DataWidth; ///< Data width, in bits, of this memory device
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
-
- SiMrcVersion Version;
- BOOLEAN EccSupport;
- UINT8 MemoryProfile;
- UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
- UINT8 Ratio;
- UINT8 RefClk;
- UINT32 VddVoltage[MAX_PROFILE_NUM];
- CONTROLLER_INFO Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
- Memory Platform Data Hob
-
- <b>Revision 1:</b>
- - Initial version.
- <b>Revision 2:</b>
- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 BootMode;
- UINT32 TsegSize;
- UINT32 TsegBase;
- UINT32 PrmrrSize;
- UINT64 PrmrrBase;
- UINT32 PramSize;
- UINT64 PramBase;
- UINT64 DismLimit;
- UINT64 DismBase;
- UINT32 GttBase;
- UINT32 MmioSize;
- UINT32 PciEBaseAddress;
- PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
- MEMORY_PLATFORM_DATA Data;
- UINT8 *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
+/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_TRACE_CACHE_TYPE 3 + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + <b>Revision 1:</b> + - Initial version. + <b>Revision 2:</b> + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 PramSize; + UINT64 PramBase; + UINT64 DismLimit; + UINT64 DismBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h index c375feeef0..e855038139 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h @@ -1,72 +1,72 @@ -/** @file
-
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FIRMWARE_VERSION_INFO_H__
-#define __FIRMWARE_VERSION_INFO_H__
-
-#include <IndustryStandard/SmBios.h>
-
-#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
-
-#pragma pack(1)
-
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} INTEL_FIRMWARE_VERSION;
-
-///
-/// Firmware Version Info (FVI) Structure
-///
-typedef struct {
- SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
- SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
- INTEL_FIRMWARE_VERSION Version; ///< Firmware version
-} INTEL_FIRMWARE_VERSION_INFO;
-
-///
-/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
-///
-typedef struct {
- SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
- UINT8 Count; ///< Number of FVI entries in this structure
- INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
-} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
-
-#pragma pack()
-
-#endif
+/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include <IndustryStandard/SmBios.h> + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif |