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-rw-r--r--src/soc/intel/apollolake/acpi/scs.asl43
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index 05aedca5a4..f69f43cda5 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -47,6 +47,49 @@ Scope (\_SB.PCI0) {
Device (SDHA) {
Name (_ADR, 0x001C0000)
Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+ Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 9: Device Readiness Durations
+ * Returns a package of five integers covering
+ * various device related delays in PCIe Base Spec.
+ */
+ If (LEqual (Arg2, 9)) {
+ /*
+ * Function 9 support for revision 3.
+ * ECN link for function definitions
+ * [https://pcisig.com/sites/default/files/
+ * specification_documents/
+ * ECN_fw_latency_optimization_final.pdf]
+ */
+ If (LEqual (Arg1, 3)) {
+ /*
+ * Integer 0: FW reset time.
+ * Integer 1: FW data link up time.
+ * Integer 2: FW functional level reset
+ * time.
+ * Integer 3: FW D3 hot to D0 time.
+ * Integer 4: FW VF enable time.
+ * set ACPI constant Ones for elements
+ * where overriding the default value
+ * is not desired.
+ */
+ Return (Package (5) {0, Ones, Ones,
+ Ones, Ones})
+ }
+ }
+ }
+ Return (Buffer() { 0x00 })
+ }
Method (_PS0, 0, NotSerialized)
{