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-rw-r--r--src/soc/intel/tigerlake/acpi/xhci.asl55
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci_jsl.asl63
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci_tgl.asl63
3 files changed, 132 insertions, 49 deletions
diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl
index 312cc5a88e..9618cf3003 100644
--- a/src/soc/intel/tigerlake/acpi/xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/xhci.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,51 +13,8 @@
* GNU General Public License for more details.
*/
-#include <soc/gpe.h>
-
-/* XHCI Controller 0:14.0 */
-
-Device (XHCI)
-{
- Name (_ADR, 0x00140000)
-
- Name (_PRW, Package () { GPE0_PME_B0, 3 })
-
- Name (_S3D, 3) /* D3 supported in S3 */
- Name (_S0W, 3) /* D3 can wake device in S0 */
- Name (_S3W, 3) /* D3 can wake system from S3 */
-
- Method (_PS0, 0, Serialized)
- {
-
- }
-
- Method (_PS3, 0, Serialized)
- {
-
- }
-
- /* Root Hub for Tigerlake-LP PCH */
- Device (RHUB)
- {
- Name (_ADR, Zero)
-
- /* USB2 */
- Device (HS01) { Name (_ADR, 1) }
- Device (HS02) { Name (_ADR, 2) }
- Device (HS03) { Name (_ADR, 3) }
- Device (HS04) { Name (_ADR, 4) }
- Device (HS05) { Name (_ADR, 5) }
- Device (HS06) { Name (_ADR, 6) }
- Device (HS07) { Name (_ADR, 7) }
- Device (HS08) { Name (_ADR, 8) }
- Device (HS09) { Name (_ADR, 9) }
- Device (HS10) { Name (_ADR, 10) }
-
- /* USB3 */
- Device (SS01) { Name (_ADR, 13) }
- Device (SS02) { Name (_ADR, 14) }
- Device (SS03) { Name (_ADR, 15) }
- Device (SS04) { Name (_ADR, 16) }
- }
-}
+#if CONFIG(SOC_INTEL_TIGERLAKE)
+ #include "xhci_tgl.asl"
+#else
+ #include "xhci_jsl.asl"
+#endif
diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl
new file mode 100644
index 0000000000..fe17b0d1bf
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Jasperlake PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 9) }
+ Device (SS02) { Name (_ADR, 10) }
+ Device (SS03) { Name (_ADR, 11) }
+ Device (SS04) { Name (_ADR, 12) }
+ Device (SS05) { Name (_ADR, 13) }
+ Device (SS06) { Name (_ADR, 14) }
+ }
+}
diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl
new file mode 100644
index 0000000000..312cc5a88e
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+
+ Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Method (_PS0, 0, Serialized)
+ {
+
+ }
+
+ Method (_PS3, 0, Serialized)
+ {
+
+ }
+
+ /* Root Hub for Tigerlake-LP PCH */
+ Device (RHUB)
+ {
+ Name (_ADR, Zero)
+
+ /* USB2 */
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+ Device (HS09) { Name (_ADR, 9) }
+ Device (HS10) { Name (_ADR, 10) }
+
+ /* USB3 */
+ Device (SS01) { Name (_ADR, 13) }
+ Device (SS02) { Name (_ADR, 14) }
+ Device (SS03) { Name (_ADR, 15) }
+ Device (SS04) { Name (_ADR, 16) }
+ }
+}