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-rw-r--r--src/soc/intel/braswell/Makefile.inc1
-rw-r--r--src/soc/intel/braswell/smbus.c29
2 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index a2b7ee5e67..4e90edf15c 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -14,6 +14,7 @@ romstage-y += iosf.c
romstage-y += lpc_init.c
romstage-y += memmap.c
romstage-y += pmutil.c
+romstage-y += smbus.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c
new file mode 100644
index 0000000000..7e1b0dfbb0
--- /dev/null
+++ b/src/soc/intel/braswell/smbus.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2019 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/early_smbus.h>
+#include <soc/iomap.h>
+#include <southbridge/intel/common/smbus.h>
+
+u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
+{
+ return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset);
+}
+
+u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
+{
+ return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
+}