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-rw-r--r--src/drivers/intel/fsp1_1/Kconfig13
-rw-r--r--src/drivers/intel/fsp1_1/cache_as_ram.S23
-rw-r--r--src/mainboard/facebook/fbg1701/Kconfig10
-rw-r--r--src/mainboard/portwell/m107/Kconfig10
4 files changed, 21 insertions, 35 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 1d229520b8..5f8f5b5534 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -56,19 +56,6 @@ config FSP_LOC
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
-config CPU_MICROCODE_CBFS_LEN
- hex "Microcode update region length in bytes"
- default 0x0
- help
- The length in bytes of the microcode update region.
-
-config CPU_MICROCODE_CBFS_LOC
- hex "Microcode update base address in CBFS"
- default 0x0
- help
- The location (base address) in CBFS that contains the microcode update
- binary.
-
config DISPLAY_HOBS
bool "Display hand-off-blocks (HOBs)"
default n
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index f4638d9c18..fea7acb2e2 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -239,11 +239,30 @@ fake_fsp_stack:
.long CONFIG_FSP_LOC /* FSP base address */
CAR_init_params:
- .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
- .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long fake_microcode /* Microcode Location */
+ .long fake_microcode_end - fake_microcode /* Microcode Length */
.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
.long CONFIG_ROM_SIZE /* Firmware Length */
CAR_init_stack:
.long CAR_init_done
.long CAR_init_params
+
+ /* coreboot updates microcode itself. FSP still needs a pointer
+ to something that looks like microcode, so provide it with fake
+ microcode. */
+fake_microcode:
+fake_microcode_header_start:
+ .long 1 /* Header Version */
+ .long 1 /* Microcode revision */
+ .long 0x10232019 /* Date: Time of writing 23-10-2019 */
+ .long 0x00010ff0 /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */
+ .long 0 /* Checksum: not checked by FSP, so won't care */
+ .long 1 /* Loader Revision */
+ .long 1 /* Processor Flags */
+ .long fake_microcode_end - fake_microcode_header_end /* Data Size */
+ .long fake_microcode_end - fake_microcode /* Total Size */
+ .space 12 /* Reserved */
+fake_microcode_header_end:
+ .space 0x10 /* 16 bytes of empty data */
+fake_microcode_end:
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index 3ade727409..41d59ff450 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -50,16 +50,6 @@ config CBFS_SIZE
hex
default 0x00600000
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x10C00
- help
- This should be updated when the microcode patch changes.
-
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xFFFE9400
-
config MRC_SETTINGS_CACHE_SIZE
hex
default 0x08000
diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig
index 3ab20f0b77..e5e3ff590a 100644
--- a/src/mainboard/portwell/m107/Kconfig
+++ b/src/mainboard/portwell/m107/Kconfig
@@ -61,16 +61,6 @@ config CBFS_SIZE
hex
default 0x00800000
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x10C00
- help
- This should be updated when the microcode patch changes.
-
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xFFFE9400
-
config MRC_SETTINGS_CACHE_SIZE
hex
default 0x08000