diff options
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/early_init.c | 2 | ||||
| -rw-r--r-- | src/mainboard/getac/p470/early_init.c | 3 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 2 | ||||
| -rw-r--r-- | src/mainboard/ibase/mb899/early_init.c | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/d945gclf/early_init.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 |
6 files changed, 3 insertions, 11 deletions
diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c index 6d37fed2ef..988d2328f6 100644 --- a/src/mainboard/asus/p5gc-mx/early_init.c +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -94,7 +94,7 @@ static u8 msr_get_fsb(void) void mainboard_late_rcba_config(void) { - /* Enable PCIe Root Port Clock Gate */ + /* Enable only PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index c75caada6e..1ce44ae9d7 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -138,9 +138,6 @@ void mainboard_late_rcba_config(void) /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; - /* This should probably go into the ACPI enable trap */ /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ RCBA32(0x1e84) = 0x00020001; diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c index 7b82059580..f0f598b7af 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -56,6 +56,6 @@ void bootblock_mainboard_early_init(void) void mainboard_late_rcba_config(void) { - /* Enable PCIe Root Port Clock Gate */ + /* Enable only PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; } diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c index 0b005022d8..fd96f66ea8 100644 --- a/src/mainboard/ibase/mb899/early_init.c +++ b/src/mainboard/ibase/mb899/early_init.c @@ -110,7 +110,4 @@ void mainboard_late_rcba_config(void) RCBA16(D29IR) = 0x0237; RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; } diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index b4818e49ca..d31fcc5907 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -32,9 +32,6 @@ void mainboard_late_rcba_config(void) /* Disable unused devices */ RCBA32(FD) |= FD_INTLAN; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; } void bootblock_mainboard_early_init(void) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 13dce61325..6629a0e0f8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -837,6 +837,7 @@ static void ich7_setup_root_complex_topology(void) static void ich7_setup_pci_express(void) { + /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) |= (1 << 0); /* Initialize slot power limit for root ports */ |