diff options
| -rw-r--r-- | src/mainboard/intel/minnowmax/cmos.layout | 6 | ||||
| -rw-r--r-- | src/mainboard/intel/minnowmax/romstage.c | 11 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index a66818861b..c7dc88dec4 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused # MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -133,6 +134,9 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index af63cab4e9..a14472297a 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -21,6 +21,8 @@ #include <baytrail/romstage.h> #include <drivers/intel/fsp/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> #include "chip.h" /** @@ -54,6 +56,7 @@ void late_mainboard_romstage_entry() void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + u8 use_xhci = UpdData->PcdEnableXhci; /* * Minnow Max Board : 1GB SKU uses 2Gb density memory @@ -65,5 +68,13 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) UpdData->PcdMemoryParameters.DIMMDensity += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); + /* Update XHCI UPD value if required */ + get_option(&use_xhci, "use_xhci_over_ehci"); + if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { + UpdData->PcdEnableXhci = use_xhci; + printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + } + return; } |