diff options
| -rw-r--r-- | src/mainboard/google/storm/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/google/storm/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/cbmem.c | 25 |
5 files changed, 35 insertions, 1 deletions
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3f7cbd63da..4c90c4e094 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -38,6 +38,6 @@ config MAINBOARD_PART_NUMBER config DRAM_SIZE_MB int - default 2048 + default 512 endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index cf78e44225..10632d8d5f 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -19,12 +19,15 @@ #include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> void main(void) { void *entry; + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 63d10191f4..4f081f047e 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,6 +6,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING @@ -49,6 +50,9 @@ config RAMSTAGE_BASE hex default 0x4060c000 +config SYS_SDRAM_BASE + hex + default 0x40000000 config STACK_TOP hex diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 94c7cb9089..91cdd935da 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -29,7 +29,9 @@ romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += cbmem.c +ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c new file mode 100644 index 0000000000..b175d6a543 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); +} |