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-rw-r--r--src/drivers/intel/fsp1_1/raminit.c5
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c5
-rw-r--r--src/soc/intel/braswell/include/soc/pei_data.h3
-rw-r--r--src/soc/intel/skylake/include/soc/pei_data.h1
4 files changed, 5 insertions, 9 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 8405c943aa..4ea1f00897 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -28,6 +28,7 @@
void raminit(struct romstage_params *params)
{
+ const bool s3wake = params->power_state->prev_sleep_state == ACPI_S3;
const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
FSP_INFO_HEADER *fsp_header;
@@ -81,7 +82,7 @@ void raminit(struct romstage_params *params)
/* Zero fill RT Buffer data and start populating fields. */
memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
pei_ptr = params->pei_data;
- if (pei_ptr->boot_mode == ACPI_S3) {
+ if (s3wake) {
fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
} else if (pei_ptr->saved_data != NULL) {
fsp_rt_common_buffer.BootMode =
@@ -158,7 +159,7 @@ void raminit(struct romstage_params *params)
/* Migrate CAR data */
printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
- if (pei_ptr->boot_mode != ACPI_S3) {
+ if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes);
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index bfed1213cd..17bd638290 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -101,7 +101,6 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_BEFORE_INITRAM);
pei_data = params->pei_data;
- pei_data->boot_mode = params->power_state->prev_sleep_state;
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
if (CONFIG(ELOG_BOOT_COUNT) && !s3wake)
@@ -129,7 +128,7 @@ void romstage_common(struct romstage_params *params)
params->pei_data->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
- } else if (params->pei_data->boot_mode == ACPI_S3) {
+ } else if (s3wake) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
@@ -149,7 +148,7 @@ void romstage_common(struct romstage_params *params)
if (CONFIG(CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
- if ((params->pei_data->boot_mode != ACPI_S3)
+ if (!s3wake
&& (params->pei_data->data_to_save_size != 0)
&& (params->pei_data->data_to_save != NULL))
mrc_cache_stash_data(MRC_TRAINING_DATA,
diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h
index 50aabed66e..7ea83ba8db 100644
--- a/src/soc/intel/braswell/include/soc/pei_data.h
+++ b/src/soc/intel/braswell/include/soc/pei_data.h
@@ -44,9 +44,6 @@ struct pei_data {
uint8_t spd_ch0_config;
uint8_t spd_ch1_config;
- /* System state information */
- int boot_mode;
-
/* Fast boot and S3 resume MRC data */
int saved_data_size;
const void *saved_data;
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index 02e04c6c02..7406a3322e 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -41,7 +41,6 @@ typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
struct pei_data {
uint32_t pei_version;
- int boot_mode;
int ec_present;
/* Console output function */