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-rw-r--r--src/soc/amd/common/block/cpu/Makefile.inc1
-rw-r--r--src/soc/amd/stoneyridge/Kconfig3
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc3
-rw-r--r--src/soc/amd/stoneyridge/include/soc/northbridge.h4
-rw-r--r--src/soc/amd/stoneyridge/romstage.c44
5 files changed, 45 insertions, 10 deletions
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
index 8e6972ed0a..ecc9afbc6f 100644
--- a/src/soc/amd/common/block/cpu/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -1,2 +1,3 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index beba741c4f..807db25f54 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -53,6 +53,9 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select HAVE_SMI_HANDLER
select SMM_TSEG
+ select RELOCATABLE_RAMSTAGE
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config VBOOT
select AMDFW_OUTSIDE_CBFS
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 5d8973616a..0fd318bfa6 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -63,6 +63,9 @@ verstage-y += reset.c
verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
verstage-y += tsc_freq.c
+postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
+postcar-y += ramtop.c
+
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index f952186d22..45c67c22fd 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -17,7 +17,6 @@
#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
-#include <arch/cpu.h>
#include <arch/io.h>
#include <device/device.h>
@@ -58,7 +57,4 @@ void domain_set_resources(device_t dev);
void fam15_finalize(void *chip_info);
void setup_uma_memory(void);
-/* todo: remove this when postcar stage is in place */
-asmlinkage void chipset_teardown_car(void);
-
#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 6769a262f0..8cd4d43942 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,10 +14,12 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cbmem.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <program_loading.h>
#include <agesawrapper.h>
@@ -27,6 +30,11 @@
asmlinkage void car_stage_entry(void)
{
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
+ void *smm_base;
+ size_t smm_size;
+ uintptr_t tseg_base;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -70,14 +78,38 @@ asmlinkage void car_stage_entry(void)
post_code(0x43);
cbmem_initialize_empty();
+ post_code(0x44);
+ if (postcar_frame_init(&pcf, 1 * KiB))
+ die("Unable to initialize postcar frame.\n");
+
+ /*
+ * We need to make sure ramstage will be run cached. At this point exact
+ * location of ramstage in cbmem is not known. Instruct postcar to cache
+ * 16 megs under cbmem top which is a safe bet to cover ramstage.
+ */
+ top_of_ram = (uintptr_t) cbmem_top();
+ /* cbmem_top() needs to be at least 16 MiB aligned */
+ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+
+ /* Cache the memory-mapped boot media. */
+ postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
/*
- * This writes contents to DRAM backing before teardown.
- * todo: move CAR teardown to postcar implementation.
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
*/
- chipset_teardown_car();
+ smm_region_info(&smm_base, &smm_size);
+ tseg_base = (uintptr_t)smm_base;
+ postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
- post_code(0x50);
- run_ramstage();
+ post_code(0x45);
+ run_postcar_phase(&pcf);
- post_code(0x54); /* Should never see this post code. */
+ post_code(0x50); /* Should never see this post code. */
}