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-rw-r--r--src/drivers/intel/gma/i915_reg.h27
-rw-r--r--src/soc/intel/apollolake/Makefile.inc1
-rw-r--r--src/soc/intel/apollolake/chip.h23
-rw-r--r--src/soc/intel/apollolake/graphics.c75
4 files changed, 126 insertions, 0 deletions
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index b4face49fb..0f3b3d0e49 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -1673,6 +1673,33 @@
#define BLM_PCH_POLARITY (1 << 29)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define UTIL_PIN_CTL 0x48400
+#define UTIL_PIN_ENABLE (1 << 31)
+
+#define UTIL_PIN_PIPE(x) ((x) << 29)
+#define UTIL_PIN_PIPE_MASK (3 << 29)
+#define UTIL_PIN_MODE_PWM (1 << 24)
+#define UTIL_PIN_MODE_MASK (0xf << 24)
+#define UTIL_PIN_POLARITY (1 << 22)
+
+/* BXT backlight register definition. */
+#define _BXT_BLC_PWM_CTL1 0xC8250
+#define BXT_BLC_PWM_ENABLE (1 << 31)
+#define BXT_BLC_PWM_POLARITY (1 << 29)
+#define _BXT_BLC_PWM_FREQ1 0xC8254
+#define _BXT_BLC_PWM_DUTY1 0xC8258
+
+#define _BXT_BLC_PWM_CTL2 0xC8350
+#define _BXT_BLC_PWM_FREQ2 0xC8354
+#define _BXT_BLC_PWM_DUTY2 0xC8358
+
+#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
+ _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
+
/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 517c8ca97d..a20a554be1 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -54,6 +54,7 @@ ramstage-y += cpu.c
ramstage-y += chip.c
ramstage-y += cse.c
ramstage-y += elog.c
+ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += heci.c
ramstage-y += i2c.c
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index ce446a063a..521d3ee06c 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -24,6 +24,22 @@ enum pnp_settings {
PNP_PERF_POWER,
};
+struct soc_intel_apl_pp {
+ unsigned int up_delay_ms;
+ unsigned int down_delay_ms;
+ unsigned int cycle_delay_ms;
+ unsigned int backlight_on_delay_ms;
+ unsigned int backlight_off_delay_ms;
+};
+
+struct soc_intel_apl_blc {
+ unsigned int pwm_hz;
+ enum {
+ GPU_BACKLIGHT_POLARITY_HIGH = 0,
+ GPU_BACKLIGHT_POLARITY_LOW,
+ } polarity;
+};
+
struct soc_intel_apollolake_config {
/* Common structure containing soc config data required by common code*/
@@ -32,6 +48,13 @@ struct soc_intel_apollolake_config {
/* Common struct containing power limits configuration info */
struct soc_power_limits_config power_limits_config;
+ /* IGD panel configuration */
+ struct soc_intel_apl_pp gpu_pp[2];
+ /* Second backlight control shares logic with other pins (aka. display
+ utility pin). Be sure it's used for PWM before setting any value for
+ the secondary controls. */
+ struct soc_intel_apl_blc gpu_blc[2];
+
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
new file mode 100644
index 0000000000..24d47721ab
--- /dev/null
+++ b/src/soc/intel/apollolake/graphics.c
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <stdint.h>
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <intelblocks/graphics.h>
+#include <drivers/intel/gma/i915_reg.h>
+
+#include "chip.h"
+
+static void graphics_configure_panelpower(
+ const struct soc_intel_apl_pp *const pp,
+ uint8_t *const mmio, const unsigned int panel_idx)
+{
+ const unsigned int offset = panel_idx * 0x100;
+ uint32_t reg32;
+
+ reg32 = ((DIV_ROUND_UP(pp->cycle_delay_ms, 100) + 1) & 0x1f) | PANEL_POWER_RESET;
+ write32(mmio + PCH_PP_CONTROL + offset, reg32);
+
+ reg32 = pp->up_delay_ms * 10 << 16;
+ reg32 |= pp->backlight_on_delay_ms * 10;
+ write32(mmio + PCH_PP_ON_DELAYS + offset, reg32);
+
+ reg32 = pp->down_delay_ms * 10 << 16;
+ reg32 |= pp->backlight_off_delay_ms * 10;
+ write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32);
+}
+
+static void graphics_configure_backlight(
+ const struct soc_intel_apl_blc *const blc,
+ uint8_t *const mmio, const unsigned int panel_idx)
+{
+ if (!blc->pwm_hz)
+ return;
+
+ const unsigned int pwm_period = 19200 * 1000 / blc->pwm_hz;
+ write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period);
+ write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2);
+ write32(mmio + BXT_BLC_PWM_CTL(panel_idx),
+ (blc->polarity ? BXT_BLC_PWM_POLARITY : 0));
+
+ /* Second backlight control uses display utility pin. */
+ if (panel_idx == 1) {
+ write32(mmio + UTIL_PIN_CTL, 0); /* Make sure it's disabled, don't know
+ what FSP might have done already. */
+ write32(mmio + UTIL_PIN_CTL, UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
+ }
+}
+
+void graphics_soc_init(struct device *const dev)
+{
+ const struct soc_intel_apollolake_config *const conf = dev->chip_info;
+ const struct resource *mmio_res;
+ void *mmio;
+ unsigned int i;
+
+ /* Some hardware configuration first. */
+
+ if (!conf)
+ return;
+
+ mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!mmio_res || !mmio_res->base)
+ return;
+ mmio = (void *)(uintptr_t)mmio_res->base;
+
+ for (i = 0; i < ARRAY_SIZE(conf->gpu_pp); ++i)
+ graphics_configure_panelpower(&conf->gpu_pp[i], mmio, i);
+
+ for (i = 0; i < ARRAY_SIZE(conf->gpu_blc); ++i)
+ graphics_configure_backlight(&conf->gpu_blc[i], mmio, i);
+}