diff options
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a6bcf0847f..d2ea0ddd2f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -266,6 +266,11 @@ struct soc_intel_tigerlake_config { uint8_t DdiPort2Ddc; uint8_t DdiPort3Ddc; uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0dae0fed47..14997c519a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + mainboard_silicon_init_params(params); } |