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-rw-r--r--src/mainboard/google/chell/devicetree.cb2
-rw-r--r--src/mainboard/google/glados/devicetree.cb2
-rw-r--r--src/mainboard/google/lars/devicetree.cb2
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb2
4 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 9bd06b2e65..1a9f423600 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -42,6 +42,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"
@@ -126,6 +127,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f6aaac36f0..5356cc1952 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -42,6 +42,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enable Root port 1.
register "PcieRpEnable[0]" = "1"
@@ -126,6 +127,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index f08c67e9ea..c662c9998d 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
@@ -129,6 +130,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 16db1130bc..c5dc0283a6 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -29,6 +29,7 @@ chip soc/intel/skylake
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
@@ -210,6 +211,7 @@ chip soc/intel/skylake
device pnp 0c09.0 on end
end
end # LPC Interface
+ device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus