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-rw-r--r--src/northbridge/amd/pi/Kconfig1
-rw-r--r--src/soc/intel/common/basecode/Kconfig7
2 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index 833afae9df..15e685b211 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -29,7 +29,6 @@ config S3_VGA_ROM_RUN
source "src/northbridge/amd/pi/00630F01/Kconfig"
source "src/northbridge/amd/pi/00730F01/Kconfig"
-source "src/northbridge/amd/pi/00660F01/Kconfig"
config HW_MEM_HOLE_SIZEK
hex
diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig
index 1c93244573..9e0f788eb4 100644
--- a/src/soc/intel/common/basecode/Kconfig
+++ b/src/soc/intel/common/basecode/Kconfig
@@ -2,10 +2,3 @@ config SOC_INTEL_COMMON_BASECODE
bool
help
Common coreboot stages and non-IP block for Intel platform
-
-if SOC_INTEL_COMMON_BASECODE
-
-source "src/soc/intel/common/basecode/*/Kconfig"
-source "src/soc/intel/common/basecode/*/*/Kconfig"
-
-endif