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-rw-r--r--src/soc/intel/skylake/chip.c11
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c11
-rw-r--r--src/soc/intel/skylake/include/fsp11/soc/ramstage.h1
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/ramstage.h1
-rw-r--r--src/soc/intel/skylake/pch.c34
5 files changed, 4 insertions, 54 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfa813a692..3e33053abb 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -63,17 +63,10 @@ static struct device_operations cpu_bus_ops = {
static void soc_enable(device_t dev)
{
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
- } else if (dev->path.type == DEVICE_PATH_PCI) {
- /* Handle PCH device enable */
- if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
- (dev->ops == NULL || dev->ops->enable == NULL)) {
- pch_enable_dev(dev);
- }
- }
}
struct chip_operations soc_intel_skylake_ops = {
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index bc0f5a5678..8e5cc2a627 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -74,17 +74,10 @@ static struct device_operations cpu_bus_ops = {
static void soc_enable(device_t dev)
{
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
- } else if (dev->path.type == DEVICE_PATH_PCI) {
- /* Handle PCH device enable */
- if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
- (dev->ops == NULL || dev->ops->enable == NULL)) {
- pch_enable_dev(dev);
- }
- }
}
struct chip_operations soc_intel_skylake_ops = {
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index d7e2fe3546..1dba445a20 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -26,7 +26,6 @@
#define FSP_MEM_UPD MEMORY_INIT_UPD
void soc_irq_settings(FSP_SIL_UPD *params);
-void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
void soc_fsp_load(void);
const char *soc_acpi_name(const struct device *dev);
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 065b6c221f..69439149b3 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -27,7 +27,6 @@
#define FSP_MEM_UPD FSP_M_CONFIG
void mainboard_silicon_init_params(FSP_S_CONFIG *params);
-void pch_enable_dev(device_t dev);
void soc_fsp_load(void);
void soc_init_pre_device(void *chip_info);
void soc_irq_settings(FSP_SIL_UPD *params);
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c
index 7084fa28a4..451bebb083 100644
--- a/src/soc/intel/skylake/pch.c
+++ b/src/soc/intel/skylake/pch.c
@@ -16,14 +16,10 @@
*/
#include <arch/io.h>
-#include <console/console.h>
-#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_def.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
-#include <soc/ramstage.h>
u8 pch_revision(void)
{
@@ -34,33 +30,3 @@ u16 pch_type(void)
{
return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
}
-
-#if ENV_RAMSTAGE
-void pch_enable_dev(device_t dev)
-{
- /* FSP should implement routines to disable PCH IPs */
- u32 reg32;
-
- /* These devices need special enable/disable handling */
- switch (PCI_SLOT(dev->path.pci.devfn)) {
- case PCH_DEV_SLOT_PCIE:
- return;
- }
-
- if (!dev->enabled) {
- printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
-
- /* Ensure memory, io, and bus master are all disabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(dev, PCI_COMMAND, reg32);
- } else {
- /* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
- }
-}
-
-#endif