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-rw-r--r--src/arch/arm/armv7/cache.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index 31819f7f48..1f762b8f9b 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -142,7 +142,15 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void)
{
- dcache_clean_all(); /* includes trailing DSB (in assembly) */
+ uint32_t sctlr;
+
+ sctlr = read_sctlr();
+
+ if (sctlr & SCTLR_C)
+ dcache_clean_all();
+ else if (sctlr & SCTLR_I)
+ dcache_clean_invalidate_all();
+
iciallu(); /* includes BPIALLU (architecturally) */
dsb();
isb();