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-rw-r--r--src/mainboard/amd/gardenia/BiosCallOuts.c21
-rw-r--r--src/mainboard/amd/gardenia/OemCustomize.c18
2 files changed, 18 insertions, 21 deletions
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index c5d86b1082..23ce0c6304 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -31,7 +31,6 @@
#include "BiosCallOuts.h"
#include "northbridge/amd/pi/dimmSpd.h"
#include "northbridge/amd/pi/agesawrapper.h"
-#include <PlatformMemoryConfiguration.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
@@ -129,23 +128,3 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
return AGESA_SUCCESS;
}
-
-#ifdef __PRE_RAM__
-
-const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
- DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
- MOTHER_BOARD_LAYERS (LAYERS_6),
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
- PSO_END
-};
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
- PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
-}
-#endif
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 1619c9544e..8f6c159bbb 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -14,6 +14,7 @@
*/
#include <northbridge/amd/pi/agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
@@ -148,3 +149,20 @@ VOID OemCustomizeInitEarly (
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;
}
+
+static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+ DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ PSO_END
+};
+
+void OemPostParams(AMD_POST_PARAMS *PostParams)
+{
+ PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+}