diff options
7 files changed, 73 insertions, 2 deletions
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index eee260328c..4971c03037 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select DISABLE_SPI_FLASH_ROM_SHARING select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_UART_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 92de72fee4..ece1201c9c 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -46,4 +46,7 @@ void bootblock_mainboard_early_init(void) mdelay(10); } } + + if (variant_has_fpmcu()) + variant_fpmcu_reset(); } diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc index 908a885965..88aa1a4ee5 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += gpio.c +bootblock-y += helpers.c romstage-y += tpm_tis.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 20f4b1f2ca..4023b2908b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> @@ -30,7 +31,7 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* S0A3 */ PAD_NF(GPIO_10, S0A3, PULL_NONE), /* SOC_FP_RST_L */ - PAD_GPO(GPIO_11, LOW), + PAD_GPO(GPIO_11, HIGH), /* SLP_S3_GATED */ PAD_GPO(GPIO_12, LOW), /* GPIO_13 - GPIO_15: Not available */ @@ -66,7 +67,7 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* SPI_CS3_L */ PAD_NF(GPIO_31, SPI_CS3_L, PULL_NONE), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), + PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -229,3 +230,23 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } + +__weak void variant_fpmcu_reset(void) +{ + if (acpi_get_sleep_type() == ACPI_S3) + return; + /* + * SOC_FP_RST_L line is pulled high when platform comes out of reset. + * So, it is required to be driven low before enabling power to + * ensure that power sequencing for the FPMCU is met. + * However, as the FPMCU is initialized only on platform reset, + * the reset line should not be asserted in case of S3 resume. + */ + static const struct soc_amd_gpio fpmcu_bootblock_table[] = { + /* SOC_FP_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), + }; + program_gpios(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table)); +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c new file mode 100644 index 0000000000..b0cca28983 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/iomap.h> + +bool variant_has_fpmcu(void) +{ + DEVTREE_CONST struct device *mmio_dev = NULL; + static const struct device_path fpmcu_path[] = { + { + .type = DEVICE_PATH_MMIO, + .mmio.addr = APU_UART1_BASE + }, + { + .type = DEVICE_PATH_GENERIC, + .generic.id = 0, + .generic.subid = 0 + }, + }; + mmio_dev = find_dev_nested_path( + all_devices->link_list, fpmcu_path, ARRAY_SIZE(fpmcu_path)); + + if (mmio_dev == NULL) + return false; + + return mmio_dev->enabled; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index dccaed0e2c..5fb746291b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -24,4 +24,8 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +void variant_fpmcu_reset(void); + +bool variant_has_fpmcu(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 707a63f1ad..0beeea0e3b 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -98,4 +98,17 @@ chip soc/amd/cezanne end end # I2C2 + device ref uart_1 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" + register "wake" = "GEVENT_5" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + device generic 0 on end + end + end + end # chip soc/amd/cezanne |