diff options
| -rw-r--r-- | src/southbridge/intel/i3100/lpc.c | 120 |
1 files changed, 60 insertions, 60 deletions
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 7b319cf97c..e3c463ba2a 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -242,66 +242,66 @@ static void i3100_pirq_init(device_t dev) } static void i3100_power_options(device_t dev) { - u8 reg8; - u16 reg16; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; - - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - get_option(&pwr_on, "power_on_after_fail"); - reg8 = pci_read_config8(dev, GEN_PMCON_3); - reg8 &= 0xfe; - if (pwr_on) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - /* avoid #S4 assertions */ - reg8 |= (3 << 4); - /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - /* Higher Nibble must be 0 */ - reg8 &= 0x0f; - /* IOCHK# NMI Enable */ - reg8 &= ~(1 << 3); - /* PCI SERR# Enable */ - // reg8 &= ~(1 << 2); - /* PCI SERR# Disable for now */ - reg8 |= (1 << 2); - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - /* Set NMI. */ - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); - } else { - /* Can't mask NMI from PCI-E and NMI_NOW */ - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); - } - outb(reg8, 0x70); - - // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - /* CLKRUN_EN */ - // reg16 |= (1 << 2); - pci_write_config16(dev, GEN_PMCON_1, reg16); - - // Set the board's GPI routing. - // i82801gx_gpi_routing(dev); + u8 reg8; + u16 reg16; + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; + + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + get_option(&pwr_on, "power_on_after_fail"); + reg8 = pci_read_config8(dev, GEN_PMCON_3); + reg8 &= 0xfe; + if (pwr_on) { + reg8 &= ~1; + } else { + reg8 |= 1; + } + /* avoid #S4 assertions */ + reg8 |= (3 << 4); + /* minimum asssertion is 1 to 2 RTCCLK */ + reg8 &= ~(1 << 3); + pci_write_config8(dev, GEN_PMCON_3, reg8); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + /* Higher Nibble must be 0 */ + reg8 &= 0x0f; + /* IOCHK# NMI Enable */ + reg8 &= ~(1 << 3); + /* PCI SERR# Enable */ + // reg8 &= ~(1 << 2); + /* PCI SERR# Disable for now */ + reg8 |= (1 << 2); + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + /* Set NMI. */ + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); + } else { + /* Can't mask NMI from PCI-E and NMI_NOW */ + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= ( 1 << 7); + } + outb(reg8, 0x70); + + // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~((3 << 0) | (1 << 10)); + reg16 |= (1 << 3) | (1 << 5); + /* CLKRUN_EN */ + // reg16 |= (1 << 2); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + // Set the board's GPI routing. + // i82801gx_gpi_routing(dev); } static void i3100_gpio_init(device_t dev) |