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-rw-r--r--src/arch/riscv/bootblock.S2
-rw-r--r--src/arch/riscv/ramstage.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 95e1923ce2..277c3910c0 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -66,7 +66,7 @@ _hart_zero:
# clear any pending interrupts
csrwi mip, 0
- # set up the mstatus register for VM
+ # set up the mstatus register
call mstatus_init
tail main
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
index 906215ca01..c721a126c4 100644
--- a/src/arch/riscv/ramstage.S
+++ b/src/arch/riscv/ramstage.S
@@ -43,7 +43,7 @@ _start:
csrwi mip, 0
call exit_car
- # set up the mstatus register for VM
+ # set up the mstatus register
call mstatus_init
tail main