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-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig2
-rw-r--r--src/southbridge/intel/common/usb_debug.c31
2 files changed, 31 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index bf020f8115..c2720ef4c7 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
select HAVE_HARD_RESET
- select HAVE_USBDEBUG
+ select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 3fed2ab854..9fe22cd176 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -28,7 +28,32 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
- return PCI_DEV(0, 0x1d, 7);
+ u32 class;
+ pci_devfn_t dev;
+
+#if CONFIG_HAVE_USBDEBUG_OPTIONS
+ if (hcd_idx==2)
+ dev = PCI_DEV(0, 0x1a, 0);
+ else
+ dev = PCI_DEV(0, 0x1d, 0);
+#else
+ dev = PCI_DEV(0, 0x1d, 7);
+#endif
+
+ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+#if CONFIG_HAVE_USBDEBUG_OPTIONS
+ if (class != PCI_EHCI_CLASSCODE) {
+ /* If we enter here before RCBA programming, EHCI function may
+ * appear with the highest function number instead.
+ */
+ dev |= PCI_DEV(0, 0, 7);
+ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+ }
+#endif
+ if (class != PCI_EHCI_CLASSCODE)
+ return 0;
+
+ return dev;
}
/* Required for successful build, but currently empty. */
@@ -41,6 +66,10 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
u32 dbgctl;
+ /* Bail out. No console to complain in. */
+ if (!dev)
+ return;
+
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);