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-rw-r--r--src/arch/riscv/bootblock.S6
-rw-r--r--src/arch/riscv/trap_handler.c2
-rw-r--r--src/arch/riscv/trap_util.S4
3 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 63df92bb38..c54c0e235c 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -32,7 +32,11 @@ _start:
# make room for HLS and initialize it
addi sp, sp, -64 // MENTRY_FRAME_SIZE
- csrr a0, mhartid
+ // Once again, the docs and toolchain disagree.
+ // Rather than get fancy I'll just lock this down
+ // until it all stabilizes.
+ //csrr a0, mhartid
+ csrr a0, 0xf14
call hls_init
# poison the stack
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ad4992803c..8c69366ba8 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -29,7 +29,7 @@ void handle_supervisor_call(trapframe *tf) {
switch(call) {
case SBI_ECALL_HART_ID:
printk(BIOS_DEBUG, "Getting hart id...\n");
- returnValue = read_csr(mhartid);
+ returnValue = read_csr(0xf14);//mhartid);
break;
case SBI_ECALL_NUM_HARTS:
/* TODO: parse the hardware-supplied config string and
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 5ee0fddc53..33579590dc 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -119,7 +119,9 @@ trap_entry:
# SMP isn't supported yet, to avoid overwriting the same stack with different
# harts that handle traps at the same time.
- csrr sp, mhartid
+ # someday this gets fixed.
+ //csrr sp, mhartid
+ csrr sp, 0xf14
.Lsmp_hang:
bnez sp, .Lsmp_hang