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-rw-r--r--src/cpu/amd/Kconfig1
-rw-r--r--src/cpu/amd/Makefile.inc1
-rw-r--r--src/cpu/amd/geode_lx/Kconfig56
-rw-r--r--src/cpu/amd/geode_lx/Makefile.inc18
-rw-r--r--src/cpu/amd/geode_lx/cache_as_ram.inc225
-rw-r--r--src/cpu/amd/geode_lx/cpubug.c84
-rw-r--r--src/cpu/amd/geode_lx/cpureginit.c256
-rw-r--r--src/cpu/amd/geode_lx/geode_lx_init.c69
-rw-r--r--src/cpu/amd/geode_lx/msrinit.c60
-rw-r--r--src/cpu/amd/geode_lx/syspreinit.c39
-rw-r--r--src/device/Kconfig3
-rw-r--r--src/device/oprom/realmode/x86.c76
-rw-r--r--src/northbridge/amd/lx/Kconfig39
-rw-r--r--src/northbridge/amd/lx/Makefile.inc11
-rw-r--r--src/northbridge/amd/lx/generic_sdram.c42
-rw-r--r--src/northbridge/amd/lx/grphinit.c99
-rw-r--r--src/northbridge/amd/lx/northbridge.c425
-rw-r--r--src/northbridge/amd/lx/northbridge.h31
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c754
-rw-r--r--src/northbridge/amd/lx/pll_reset.c82
-rw-r--r--src/northbridge/amd/lx/raminit.c775
-rw-r--r--src/northbridge/amd/lx/raminit.h37
-rw-r--r--src/southbridge/amd/cs5536/Kconfig27
-rw-r--r--src/southbridge/amd/cs5536/Makefile.inc27
-rw-r--r--src/southbridge/amd/cs5536/chip.h39
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c714
-rw-r--r--src/southbridge/amd/cs5536/cs5536.h454
-rw-r--r--src/southbridge/amd/cs5536/early_setup.c276
-rw-r--r--src/southbridge/amd/cs5536/early_smbus.c39
-rw-r--r--src/southbridge/amd/cs5536/ide.c57
-rw-r--r--src/southbridge/amd/cs5536/pirq.c34
-rw-r--r--src/southbridge/amd/cs5536/smbus.c187
-rw-r--r--src/southbridge/amd/cs5536/smbus.h32
33 files changed, 1 insertions, 5068 deletions
diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index f4504a2efb..7a6d9568ce 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -7,7 +7,6 @@ source src/cpu/amd/socket_ASB2/Kconfig
source src/cpu/amd/socket_F_1207/Kconfig
source src/cpu/amd/family_10h-family_15h/Kconfig
-source src/cpu/amd/geode_lx/Kconfig
source src/cpu/amd/agesa/Kconfig
source src/cpu/amd/pi/Kconfig
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 11a1c5b38e..72c6aa2696 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -5,7 +5,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2
subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
-subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi
diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig
deleted file mode 100644
index 82a5d46da3..0000000000
--- a/src/cpu/amd/geode_lx/Kconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-config CPU_AMD_GEODE_LX
- bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
-
-if CPU_AMD_GEODE_LX
-
-config CPU_SPECIFIC_OPTIONS
- def_bool y
- select NO_MMCONF_SUPPORT
- select TSC_MONOTONIC_TIMER
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
-
-config DCACHE_BSP_STACK_SLUSH
- hex
- default 0x1000
-
-config DCACHE_AP_STACK_SIZE
- hex
- default 0x400
-
-config GEODE_VSA
- bool
- default y
-
-config GEODE_VSA_FILE
- bool "Add a VSA image"
- default y
- help
- Select this option if you have an AMD Geode LX vsa that you would
- like to add to your ROM.
-
- You will be able to specify the location and file name of the
- image later.
-
-config VSA_FILENAME
- string "AMD Geode LX VSA path and filename"
- depends on GEODE_VSA_FILE
- default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
- help
- The path and filename of the file to use as VSA.
-
-endif # CPU_AMD_GEODE_LX
diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc
deleted file mode 100644
index 99be61e374..0000000000
--- a/src/cpu/amd/geode_lx/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-
-romstage-y += cpureginit.c
-romstage-y += syspreinit.c
-romstage-y += msrinit.c
-
-ramstage-y += geode_lx_init.c
-ramstage-y += cpubug.c
-
-cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
-
-cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
-vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
-vsa-type = stage
-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
deleted file mode 100644
index 8250d729b4..0000000000
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
-#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
-
-#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
-#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
-#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
-#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
-#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
-
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/post_code.h>
-
-/**
- * DCacheSetup
- * Setup data cache for use as RAM for a stack.
- */
-DCacheSetup:
- /* Save the BIST result */
- movl %eax, %ebx
-
- invd
- /* set cache properties */
- movl $CPU_RCONF_DEFAULT, %ecx
- rdmsr
- movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
- wrmsr
-
- /* in LX DCDIS is set after POR which disables the cache..., clear this bit */
- movl $CPU_DM_CONFIG0,%ecx
- rdmsr
- andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
- wrmsr
-
- /* get cache timing params from BIOS config data locations and apply */
- /* fix delay controls for DM and IM arrays */
- /* fix delay controls for DM and IM arrays */
- movl $CPU_BC_MSS_ARRAY_CTL0, %ecx
- xorl %edx, %edx
- movl $0x2814D352, %eax
- wrmsr
-
- movl $CPU_BC_MSS_ARRAY_CTL1, %ecx
- xorl %edx, %edx
- movl $0x1068334D, %eax
- wrmsr
-
- movl $CPU_BC_MSS_ARRAY_CTL2, %ecx
- movl $0x00000106, %edx
- movl $0x83104104, %eax
- wrmsr
-
- movl $GLCP_FIFOCTL, %ecx
- rdmsr
- movl $0x00000005, %edx
- wrmsr
-
- /* Enable setting */
- movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
- xorl %edx, %edx
- movl $0x01, %eax
- wrmsr
-
- /* Get cleaned up. */
- xorl %edi, %edi
- xorl %esi, %esi
- xorl %ebp, %ebp
-
- /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
- /* remember, there is NO stack yet... */
-
- /* Tell cache we want to fill WAY 0 starting at the top */
- xorl %edx, %edx
- xorl %eax, %eax
- movl $CPU_DC_INDEX, %ecx
- wrmsr
-
- /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
- movl $LX_STACK_BASE, %ebp /* init to start address */
- orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
-
- /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
- movl $LX_NUM_CACHELINES, %edi
-DCacheSetupFillWay:
-
- /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
- /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
- movw $0x04, %si
- xorl %edx, %edx
- xorl %eax, %eax
- movl $CPU_DC_DATA, %ecx
-DCacheSetup_quadWordLoop:
- wrmsr
- decw %si
- jnz DCacheSetup_quadWordLoop
-
- /* Set the tag for this line, need to do this for every new cache line to validate it! */
- /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
- xorl %edx, %edx
- movl %ebp, %eax
- movl $CPU_DC_TAG, %ecx
- wrmsr
-
- /* switch to next line */
- /* lines are in Bits10:4 */
- /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
- movl $CPU_DC_INDEX, %ecx
- rdmsr
- addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
- wrmsr
-
- decl %edi
- jnz DCacheSetupFillWay
-
- /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
- addl $LX_CACHEWAY_SIZE, %ebp
- cmpl $LX_STACK_END, %ebp
- jge leave_DCacheSetup
- movl $LX_NUM_CACHELINES, %edi
-
- /* switch to next way */
- movl $CPU_DC_INDEX, %ecx
- rdmsr
- addl $0x01, %eax
- andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
- wrmsr
-
- jmp DCacheSetupFillWay
-
-leave_DCacheSetup:
- xorl %edi, %edi
- xorl %esi, %esi
- xorl %ebp, %ebp
-
- /* Disable the cache, but ... DO NOT INVALIDATE the tags. */
- /* Memory reads and writes will all hit in the cache. */
- /* Cache updates and memory write-backs will not occur ! */
- movl %cr0, %eax
- orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
- movl %eax, %cr0
-
- /* Now point sp to the cached stack. */
- /* The stack will be fully functional at this location. No system memory is required at all ! */
- /* set up the stack pointer */
- movl $LX_STACK_END, %eax
- movl %eax, %esp
-
- /* test the stack*/
- movl $0x0F0F05A5A, %edx
- pushl %edx
- popl %ecx
- cmpl %ecx, %edx
- je DCacheSetupGood
-
- post_code(0xc5)
-DCacheSetupBad:
- hlt /* issues */
- jmp DCacheSetupBad
-DCacheSetupGood:
- /* Go do early init and memory setup */
-
- /* Restore the BIST result */
- movl %ebx, %eax
- movl %esp, %ebp
- pushl %eax
-
- post_code(0x23)
-
- /* Call romstage.c main function */
- call mainboard_romstage_entry
-
-.global done_cache_as_ram_main
-done_cache_as_ram_main:
-
- /* We now run over the stack-in-cache,
- * copying it back to itself to invalidate the cache */
-
- push %edi
- mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
- push %esi
- mov $(CONFIG_DCACHE_RAM_BASE),%edi
- mov %edi,%esi
- cld
- rep movsl %ds:(%esi),%es:(%edi)
- pop %esi
- pop %edi
-
- /* Clear the cache out to RAM */
- wbinvd
- /* re-enable the cache */
- movl %cr0, %eax
- xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
- movl %eax, %cr0
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
-
- /* TODO For suspend/resume low memory needs backup store. */
-
- cld /* clear direction flag */
-
- /* copy coreboot from it's initial load location to
- * the location it is compiled to run at.
- * Normally this is copying from FLASH ROM to RAM.
- */
- call copy_and_run
-
-.Lhlt:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .Lhlt
diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
deleted file mode 100644
index 7e7d81b19d..0000000000
--- a/src/cpu/amd/geode_lx/cpubug.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-
-/**
- *
- * pcideadlock
- *
- * Bugtool #465 and #609
- * PCI cache deadlock
- * There is also fix code in cache and PCI functions.
- * This bug is very is pervasive.
- */
-static void pcideadlock(void)
-{
- msr_t msr;
-
- /*
- * forces serialization of all load misses. Setting this bit prevents the
- * DM pipe from backing up if a read request has to be held up waiting
- * for PCI writes to complete.
- */
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- /* write serialize memory hole to PCI. Need to unWS when something is
- * shadowed regardless of cachablility.
- */
- msr.lo = 0x021212121;
- msr.hi = 0x021212121;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-}
-
-/**
- * DisableMemoryReorder
- *
- * PBZ 3659:
- * The MC reordered transactions incorrectly and breaks coherency.
- * Disable reordering and take a potential performance hit.
- * This is safe to do here and not in MC init since there is nothing
- * to maintain coherency with and the cache is not enabled yet.
- */
-static void disablememoryreadorder(void)
-{
- msr_t msr;
-
- msr = rdmsr(MC_CF8F_DATA);
- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
- wrmsr(MC_CF8F_DATA, msr);
-}
-
-/* For CPU version C3. Should be the only released version */
-void cpubug(void)
-{
- pcideadlock();
- disablememoryreadorder();
- printk(BIOS_DEBUG, "Done cpubug fixes\n");
-}
diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c
deleted file mode 100644
index a61501e58e..0000000000
--- a/src/cpu/amd/geode_lx/cpureginit.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <spd.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <northbridge/amd/lx/raminit.h>
-#include <northbridge/amd/lx/northbridge.h>
-
-/**
- * Delay Control Settings table from AMD (MCP 0x4C00000F).
- */
-static const msrinit_t delay_msr_table[] = {
- {CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}},
- {CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}},
- {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
-};
-
-static const struct delay_controls {
- u8 dimms;
- u8 devices;
- u32 slow_hi;
- u32 slow_low;
- u32 fast_hi;
- u32 fast_low;
-} delay_control_table[] = {
- /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */
- { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 },
- { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 },
- { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 },
- { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 },
- { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 },
- { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
- { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
- { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 },
-};
-
-/*
- * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
- * in slot 0, but it should be clear for all 2 DIMM settings and if a
- * single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
- *
- * Settings for single DIMM and no VTT termination (like DB800 platform)
- * 0xF2F100FF 0x56960004
- * -------------------------------------
- * ADDR/CTL have 22 ohm series R
- * DQ/DQM/DQS have 33 ohm series R
- */
-
-/**
- * This is Black Magic DRAM timing juju[1].
- *
- * DRAM delay depends on CPU clock, memory bus clock, memory bus loading,
- * memory bus termination, your middle initial (ha! caught you!), GeodeLink
- * clock rate, and DRAM timing specifications.
- *
- * From this the code computes a number which is "known to work". No,
- * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
- * is hooked up, then just don't do anything. This code was written by a master
- * of the Dark Arts at AMD and should not be modified in any way.
- *
- * [1] (http://www.thefreedictionary.com/juju)
- *
- * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
- * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
- * @param terminated The bus is terminated. (mainboard dependent).
- */
-static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
-{
- u32 glspeed;
- u8 spdbyte0, spdbyte1, dimms, i;
- msr_t msr;
-
- glspeed = GeodeLinkSpeed();
-
- /* Fix delay controls for DM and IM arrays. */
- for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++)
- wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr);
-
- msr = rdmsr(GLCP_FIFOCTL);
- msr.hi = 0x00000005;
- wrmsr(GLCP_FIFOCTL, msr);
-
- /* Enable setting. */
- msr.hi = 0;
- msr.lo = 0x00000001;
- wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr);
-
- /* Debug Delay Control setup check.
- * Leave it alone if it has been setup. FS2 or something is here.
- */
- msr = rdmsr(GLCP_DELAY_CONTROLS);
- if (msr.lo & ~(DELAY_LOWER_STATUS_MASK))
- return;
-
- /* Delay Controls based on DIMM loading. UGH!
- * Number of devices = module width (SPD 6) / device width (SPD 13)
- * * physical banks (SPD 5)
- *
- * Note: We only support a module width of 64.
- */
- dimms = 0;
- spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
- if (spdbyte0 != 0xFF) {
- dimms++;
- spdbyte0 = (u8)64 / spdbyte0 *
- (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
- } else {
- spdbyte0 = 0;
- }
-
- spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
- if (spdbyte1 != 0xFF) {
- dimms++;
- spdbyte1 = (u8)64 / spdbyte1 *
- (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
- } else {
- spdbyte1 = 0;
- }
-
- /* Zero GLCP_DELAY_CONTROLS MSR */
- msr.hi = msr.lo = 0;
-
- /* Save some power, disable clock to second DIMM if it is empty. */
- if (spdbyte1 == 0)
- msr.hi |= DELAY_UPPER_DISABLE_CLK135;
-
- spdbyte0 += spdbyte1;
-
- if ((dimms == 1) && (terminated == DRAM_TERMINATED)) {
- msr.hi = 0xF2F100FF;
- msr.lo = 0x56960004;
- } else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
- if ((dimms == delay_control_table[i].dimms) &&
- (spdbyte0 <= delay_control_table[i].devices)) {
- if (glspeed < 334) {
- msr.hi |= delay_control_table[i].slow_hi;
- msr.lo |= delay_control_table[i].slow_low;
- } else {
- msr.hi |= delay_control_table[i].fast_hi;
- msr.lo |= delay_control_table[i].fast_low;
- }
- break;
- }
- }
- wrmsr(GLCP_DELAY_CONTROLS, msr);
-}
-
-void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
-{
- int msrnum;
- msr_t msr;
-
- /* Castle 2.0 BTM periodic sync period. */
- /* [40:37] 1 sync record per 256 bytes */
- printk(BIOS_DEBUG, "Castle 2.0 BTM periodic sync period.\n");
- msrnum = CPU_PF_CONF;
- msr = rdmsr(msrnum);
- msr.hi |= (0x8 << 5);
- wrmsr(msrnum, msr);
-
- /*
- * LX performance setting.
- * Enable Quack for fewer re-RAS on the MC
- */
- printk(BIOS_DEBUG, "Enable Quack for fewer re-RAS on the MC\n");
- msrnum = GLIU0_ARB;
- msr = rdmsr(msrnum);
- msr.hi &= ~ARB_UPPER_DACK_EN_SET;
- msr.hi |= ARB_UPPER_QUACK_EN_SET;
- wrmsr(msrnum, msr);
-
- msrnum = GLIU1_ARB;
- msr = rdmsr(msrnum);
- msr.hi &= ~ARB_UPPER_DACK_EN_SET;
- msr.hi |= ARB_UPPER_QUACK_EN_SET;
- wrmsr(msrnum, msr);
-
- /* GLIU port active enable, limit south pole masters
- * (AES and PCI) to one outstanding transaction.
- */
- printk(BIOS_DEBUG, " GLIU port active enable\n");
- msrnum = GLIU1_PORT_ACTIVE;
- msr = rdmsr(msrnum);
- msr.lo &= ~0x880;
- wrmsr(msrnum, msr);
-
- /* Set the Delay Control in GLCP */
- printk(BIOS_DEBUG, "Set the Delay Control in GLCP\n");
- SetDelayControl(dimm0, dimm1, terminated);
-
- /* Enable RSDC */
- printk(BIOS_DEBUG, "Enable RSDC\n");
- msrnum = CPU_AC_SMM_CTL;
- msr = rdmsr(msrnum);
- msr.lo |= SMM_INST_EN_SET;
- wrmsr(msrnum, msr);
-
- /* FPU imprecise exceptions bit */
- printk(BIOS_DEBUG, "FPU imprecise exceptions bit\n");
- msrnum = CPU_FPU_MSR_MODE;
- msr = rdmsr(msrnum);
- msr.lo |= FPU_IE_SET;
- wrmsr(msrnum, msr);
-
- /* Power Savers (Do after BIST) */
- /* Enable Suspend on HLT & PAUSE instructions */
- printk(BIOS_DEBUG, "Enable Suspend on HLT & PAUSE instructions\n");
- msrnum = CPU_XC_CONFIG;
- msr = rdmsr(msrnum);
- msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
- wrmsr(msrnum, msr);
-
- /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
- printk(BIOS_DEBUG, "Enable SUSP and allow TSC to run in Suspend\n");
- msrnum = CPU_BC_CONF_0;
- msr = rdmsr(msrnum);
- msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
- msr.lo &= 0x0F0FFFFFF;
- msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
- wrmsr(msrnum, msr);
-
- /* Disable the debug clock to save power. */
- /* NOTE: leave it enabled for fs2 debug */
- if (debug_clock_disable && 0) {
- msrnum = GLCP_DBGCLKCTL;
- msr.hi = 0;
- msr.lo = 0;
- wrmsr(msrnum, msr);
- }
-
- /* Setup throttling delays to proper mode if it is ever enabled. */
- printk(BIOS_DEBUG, "Setup throttling delays to proper mode\n");
- msrnum = GLCP_TH_OD;
- msr.hi = 0;
- msr.lo = 0x00000603C;
- wrmsr(msrnum, msr);
- printk(BIOS_DEBUG, "Done cpuRegInit\n");
-}
diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c
deleted file mode 100644
index e620131d6b..0000000000
--- a/src/cpu/amd/geode_lx/geode_lx_init.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de>
- * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <arch/io.h>
-
-static void vsm_end_post_smi(void)
-{
- __asm__ volatile ("push %ax\n"
- "mov $0x5000, %ax\n"
- ".byte 0x0f, 0x38\n" "pop %ax\n");
-}
-
-static void geode_lx_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "geode_lx_init\n");
-
- /* Turn on caching if we haven't already */
- x86_enable_cache();
-
- /* Enable the local CPU APICs */
- //setup_lapic();
-
- // do VSA late init
- vsm_end_post_smi();
-
- // Set gate A20 (legacy vsm disables it in late init)
- printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
- outb(0x02, 0x92);
- printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
-
- printk(BIOS_DEBUG, "CPU geode_lx_init DONE\n");
-};
-
-static struct device_operations cpu_dev_ops = {
- .init = geode_lx_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- {X86_VENDOR_AMD, 0x05A2},
- {0, 0},
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
deleted file mode 100644
index 827bb61f3a..0000000000
--- a/src/cpu/amd/geode_lx/msrinit.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <northbridge/amd/lx/northbridge.h>
-
-static const msrinit_t msr_table[] =
-{
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
- * Rom Properties: Write Serialize, WriteProtect.
- * RomBase: 0xFFFC0
- * SysTop to RomBase Properties: Write Back.
- * SysTop: 0x000A0
- * System Memory Properties: (Write Back) */
- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-
- /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
- * It doesn't really matter in fact how much, however, because the only usage
- * of this extended memory will be to host the ramstage stage at RAMBASE,
- * currently 1Mb.
- * These registers will be set to their correct value by the Northbridge init code.
- *
- * WARNING: if ramstage could not be loaded, these registers are probably
- * incorrectly set here. You may comment the following two lines and set RAMBASE
- * to 0x4000 to revert to the previous behavior for LX-boards.
- */
- {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
- {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
-};
-
-void lx_msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(msr_table); i++)
- wrmsr(msr_table[i].index, msr_table[i].msr);
-}
diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c
deleted file mode 100644
index f30c0598e4..0000000000
--- a/src/cpu/amd/geode_lx/syspreinit.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <cpu/amd/lxdef.h>
-
-/**
- * StartTimer1
- *
- * Entry: none
- * Exit: Starts Timer 1 for port 61 use
- * Destroys: Al,
- */
-static void StartTimer1(void)
-{
- outb(0x56, 0x43);
- outb(0x12, 0x41);
-}
-
-void SystemPreInit(void)
-{
- /* they want a jump ... */
- StartTimer1();
-}
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 66f57d96ca..85f1d65719 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -170,7 +170,7 @@ choice
prompt "Option ROM execution type"
default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86
- depends on VGA_ROM_RUN || GEODE_VSA
+ depends on VGA_ROM_RUN
config PCI_OPTION_ROM_RUN_REALMODE
prompt "Native mode"
@@ -185,7 +185,6 @@ config PCI_OPTION_ROM_RUN_REALMODE
config PCI_OPTION_ROM_RUN_YABEL
prompt "Secure mode"
bool
- depends on !GEODE_VSA
help
If you select this option, the x86emu CPU emulator will be used to
execute PCI Option ROMs.
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index d9fac36b66..20c6ea9808 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -355,82 +355,6 @@ void run_bios(struct device *dev, unsigned long addr)
#endif
}
-#if IS_ENABLED(CONFIG_GEODE_VSA)
-
-#define VSA2_BUFFER 0x60000
-#define VSA2_ENTRY_POINT 0x60020
-
-// TODO move to a header file.
-void do_vsmbios(void);
-
-/* VSA virtual register helper */
-static u32 VSA_vrRead(u16 classIndex)
-{
- u32 eax, ebx, ecx, edx;
- asm volatile (
- "movw $0x0AC1C, %%dx\n"
- "orl $0x0FC530000, %%eax\n"
- "outl %%eax, %%dx\n"
- "addb $2, %%dl\n"
- "inw %%dx, %%ax\n"
- : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
- : "a"(classIndex)
- );
-
- return eax;
-}
-
-void do_vsmbios(void)
-{
- printk(BIOS_DEBUG, "Preparing for VSA...\n");
-
- /* Set up C interrupt handlers */
- setup_interrupt_handlers();
-
- /* Setting up realmode IDT */
- setup_realmode_idt();
-
- /* Make sure the code is placed. */
- setup_realmode_code();
-
- if ((uintptr_t)cbfs_boot_load_stage_by_name("vsa") !=
- VSA2_ENTRY_POINT) {
- printk(BIOS_ERR, "Failed to load VSA.\n");
- return;
- }
-
- unsigned char *buf = (unsigned char *)VSA2_BUFFER;
- printk(BIOS_DEBUG, "VSA: Buffer @%p *[0k]=%02x\n", buf, buf[0]);
- printk(BIOS_DEBUG, "VSA: Signature *[0x20-0x23] is %02x:%02x:%02x:%02x\n",
- buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
-
- /* Check for code to emit POST code at start of VSA. */
- if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
- (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
- printk(BIOS_WARNING, "VSA: Signature incorrect. Install failed.\n");
- return;
- }
-
- printk(BIOS_DEBUG, "Calling VSA module...\n");
-
- /* ECX gets SMM, EDX gets SYSMEM */
- realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM,
- MSR_GLIU0_SYSMEM, 0x0, 0x0);
-
- printk(BIOS_DEBUG, "... VSA module returned.\n");
-
- /* Restart timer 1 */
- outb(0x56, 0x43);
- outb(0x12, 0x41);
-
- /* Check that VSA is running OK */
- if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
- printk(BIOS_DEBUG, "VSM: VSA2 VR signature verified.\n");
- else
- printk(BIOS_ERR, "VSM: VSA2 VR signature not valid. Install failed.\n");
-}
-#endif
-
/* interrupt_handler() is called from assembler code only,
* so there is no use in putting the prototype into a header file.
*/
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
deleted file mode 100644
index 53a0e0556b..0000000000
--- a/src/northbridge/amd/lx/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-config NORTHBRIDGE_AMD_LX
- bool
- select GEODE_VSA
- select LATE_CBMEM_INIT
- select NO_RELOCATABLE_RAMSTAGE
-
-if NORTHBRIDGE_AMD_LX
-
-config VIDEO_MB
- int
- default 8
-
-config PLL_MANUAL_CONFIG
- bool
-
-if PLL_MANUAL_CONFIG
-
-# "Core/GLIU Frequency"
-config CORE_GLIU_500_266
- bool # "500MHz / 266MHz"
-
-config CORE_GLIU_500_333
- bool # "500MHz / 333MHz"
-
-config CORE_GLIU_500_400
- bool # "500MHz / 400MHz"
-
-config PLLMSRhi
- hex
- default 0x39c if CORE_GLIU_500_266
- default 0x49c if CORE_GLIU_500_333
- default 0x59c if CORE_GLIU_500_400
-
-config PLLMSRlo
- hex
-
-endif
-
-endif
diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc
deleted file mode 100644
index e36139ff6d..0000000000
--- a/src/northbridge/amd/lx/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-ifeq ($(CONFIG_NORTHBRIDGE_AMD_LX),y)
-
-ramstage-y += northbridge.c
-ramstage-y += northbridgeinit.c
-ramstage-y += grphinit.c
-
-romstage-y += raminit.c
-romstage-y += generic_sdram.c
-romstage-y += pll_reset.c
-
-endif
diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c
deleted file mode 100644
index e0869cdbca..0000000000
--- a/src/northbridge/amd/lx/generic_sdram.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <northbridge/amd/lx/raminit.h>
-
-/* Setup SDRAM */
-void sdram_initialize(int controllers, const struct mem_controller *ctrl)
-{
- int i;
- /* Set the registers we can set once to reasonable values */
- for (i = 0; i < controllers; i++) {
- printk(BIOS_DEBUG, "Ram1.%02x\n", i);
- sdram_set_registers(ctrl + i);
- }
-
- /* Now setup those things we can auto detect */
- for (i = 0; i < controllers; i++) {
- printk(BIOS_DEBUG, "Ram2.%02x\n", i);
- sdram_set_spd_registers(ctrl + i);
- }
-
- /* Now that everything is setup enable the SDRAM.
- * Some chipsets do the work for us while on others
- * we need to it by hand.
- */
- printk(BIOS_DEBUG, "Ram3\n");
-
- sdram_enable(controllers, ctrl);
-
- printk(BIOS_DEBUG, "Ram4\n");
-}
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
deleted file mode 100644
index 1adb9af7c1..0000000000
--- a/src/northbridge/amd/lx/grphinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <stdint.h>
-#include <cpu/amd/vr.h>
-#include <console/console.h>
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <stdlib.h>
-
-void geodelx_vga_msr_init(void);
-void graphics_init(void);
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
-};
-
-static const struct msrinit geodelx_vga_msr[] = {
- /* Enable the GLIU Memory routing to the hardware
- * PDID1 : Port 4, GLIU0
- * PBASE : 0x000A0
- * PMASK : 0xFFFE0
- */
- {.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
- /* Enable the GLIU IO Routing
- * IDID : Port 4, GLIU0
- * IBASE : 0x003c0
- * IMASK : 0xffff0
- */
- {.msrnum = GLIU0_IOD_BM_0, {.lo = 0x3c0ffff0, .hi = 0x80000000}},
- /* Enable the GLIU IO Routing
- * IDID : Port 4, GLIU0
- * IBASE : 0x003d0
- * IMASK : 0xffff0
- */
- {.msrnum = GLIU0_IOD_BM_1, {.lo = 0x3d0ffff0, .hi = 0x80000000}},
-};
-
-void geodelx_vga_msr_init(void)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)
- wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);
-}
-
- /*
- * This function mirrors the Graphics_Init routine in GeodeROM.
- */
-void graphics_init(void)
-{
- uint16_t wClassIndex, wData, res;
-
- /* SoftVG initialization */
- printk(BIOS_DEBUG, "Graphics init...\n");
-
- geodelx_vga_msr_init();
-
- /* Call SoftVG with the main configuration parameters. */
- /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
-
- wClassIndex = (VRC_VG << 8) + VG_CONFIG;
-
- /*
- * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)
- * External Monochrome Card Support(12) 0, NO
- * Controller Priority Select(11) 1, Primary
- * Display Select(10:8) 0x0, CRT
- * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,
- * defined in devicetree.cb
- * PLL Reference Clock Bypass(0) 0, Default
- */
-
- /* Video RAM has to be given in 2MB chunks
- * the value is read @ 7:1 (value in 7:0 looks like /2)
- * so we can add the real value in megabytes
- */
-
- wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
- VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
- vrWrite(wClassIndex, wData);
-
- res = vrRead(wClassIndex);
- printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
-}
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
deleted file mode 100644
index ffaaa19ca3..0000000000
--- a/src/northbridge/amd/lx/northbridge.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/vr.h>
-#include "northbridge.h"
-#include <southbridge/amd/cs5536/cs5536.h>
-
-
-/* here is programming for the various MSRs.*/
-#define IM_QWAIT 0x100000
-
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
-#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
-
-/* these are the 8-bit attributes for controlling RCONF registers */
-#define CACHE_DISABLE (1<<0)
-#define WRITE_ALLOCATE (1<<1)
-#define WRITE_PROTECT (1<<2)
-#define WRITE_THROUGH (1<<3)
-#define WRITE_COMBINE (1<<4)
-#define WRITE_SERIALIZE (1<<5)
-
-/* RAM has none of this stuff */
-#define RAM_PROPERTIES (0)
-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-#define MSR_WS_CD_DEFAULT (0x21212121)
-
-/* 1810-1817 give you 8 registers with which to program protection regions */
-/* the are region configuration range registers, or RRCF */
-/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
-/* so no left-shift needed for top or base */
-#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
-#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
-
-/* build initializer for P2D MSR */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-
-void print_conf(void);
-void graphics_init(void);
-void do_vsmbios(void);
-
-struct msr_defaults {
- int msr_no;
- msr_t msr;
-} msr_defaults[] = {
- {
- 0x1700, {
- .hi = 0,.lo = IM_QWAIT}}, {
- 0x1800, {
- .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =
- DMCF_SERIAL_LOAD_MISSES}},
- /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
- /* for 180a, for now, we assume VSM will configure it */
- /* 180b is left at reset value,a0000-bffff is non-cacheable */
- /* 180c, c0000-dffff is set to write serialize and non-cachable */
- /* oops, 180c will be set by CPU bug handling in cpubug.c */
- //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
- /* 180d is left at default, e0000-fffff is non-cached */
- /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
- /* we will not set 0x180f, the DMM,yet */
- //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
- //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
- //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
- //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
- /* now for GLPCI routing */
- /* GLIU0 */
- P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
- /* GLIU1 */
- P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {
- 0}
-};
-
-/* Print the platform configuration - do before PCI init or it will not
- * work right.
- */
-void print_conf(void)
-{
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
- int i;
- unsigned long iol;
- msr_t msr;
-
- int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
- CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
- CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
- GLCP_DELAY_CONTROLS, GL_END
- };
-
- int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
- MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
- GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
- GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
- MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
- GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
- GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
- GLIU0_GLD_MSR_COH, GL_END
- };
-
- int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
- MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
- MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
- MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
- GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
- GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
- GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
- GLIU1_GLD_MSR_COH, GL_END
- };
-
- int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
- CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
- };
-
- int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
- MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
- MDD_IRQM_PRIM, GL_END
- };
-
- int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
- GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
- GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
- };
-
- int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
- MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
- MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
- };
-
- printk(BIOS_DEBUG, "---------- CPU ------------\n");
-
- for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
- msr = rdmsr(cpu_msr_defs[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
- cpu_msr_defs[i], msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
-
- for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
- msr = rdmsr(gliu0_msr_defs[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
- gliu0_msr_defs[i], msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
-
- for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
- msr = rdmsr(gliu1_msr_defs[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
- gliu1_msr_defs[i], msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- RCONF ------------\n");
-
- for (i = 0; rconf_msr[i] != GL_END; i++) {
- msr = rdmsr(rconf_msr[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
- msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- VARIA ------------\n");
- msr = rdmsr(0x51300010);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
- msr.lo);
-
- msr = rdmsr(0x51400015);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
- msr.lo);
-
- printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
- msr = rdmsr(MDD_IRQM_YLOW);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
- msr.lo);
- msr = rdmsr(MDD_IRQM_YHIGH);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
- msr.hi, msr.lo);
- msr = rdmsr(MDD_IRQM_ZLOW);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
- msr.lo);
- msr = rdmsr(MDD_IRQM_ZHIGH);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
- msr.hi, msr.lo);
-
- printk(BIOS_DEBUG, "---------- PCI ------------\n");
-
- for (i = 0; pci_msr[i] != GL_END; i++) {
- msr = rdmsr(pci_msr[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
- msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
-
- for (i = 0; dma_msr[i] != GL_END; i++) {
- msr = rdmsr(dma_msr[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
- msr.hi, msr.lo);
- }
-
- printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
-
- for (i = 0; cs5536_msr[i] != GL_END; i++) {
- msr = rdmsr(cs5536_msr[i]);
- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
- msr.hi, msr.lo);
- }
-
- iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
- GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
- iol = inl(GPIOL_EVENTS_ENABLE);
- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
- GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
- iol = inl(GPIOL_INPUT_INVERT_ENABLE);
- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
- GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
- iol = inl(GPIO_MAPPER_X);
- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
- iol);
-#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
-}
-
-/* todo: add a resource record. We don't do this here because this may be called when
- * very little of the platform is actually working.
- */
-int sizeram(void)
-{
- msr_t msr;
- int sizem = 0;
- unsigned short dimm;
-
- /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
- msr = rdmsr(MC_CF07_DATA);
- printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
-
- /* dimm 0 */
- dimm = msr.hi;
- /* installed? */
- if ((dimm & 7) != 7) {
- sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
- }
-
- /* dimm 1 */
- dimm = msr.hi >> 16;
- /* installed? */
- if ((dimm & 7) != 7) {
- sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
- }
-
- printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
- return sizem;
-}
-
-static void enable_shadow(struct device *dev)
-{
-}
-
-static void northbridge_init(struct device *dev)
-{
-
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
- enable_shadow(dev);
-
-}
-
-static void northbridge_set_resources(struct device *dev)
-{
- uint8_t line;
-
- struct bus *bus;
- for (bus = dev->link_list; bus; bus = bus->next) {
- if (bus->children) {
- printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
- bus->secondary);
- assign_resources(bus);
- }
- }
-
- /* set a default latency timer */
- pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
-
- /* set a default secondary latency timer */
- if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
- pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
- }
-
- /* zero the irq settings */
- line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
- if (line) {
- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
- }
-
- /* set the cache line size, so far 64 bytes is good for everyone */
- pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
-}
-
-static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = northbridge_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_LXBRIDGE,
-};
-
-#include <cbmem.h>
-
-static void pci_domain_set_resources(struct device *dev)
-{
- int idx;
- u32 tomk;
- struct device *mc_dev;
-
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
- mc_dev = dev->link_list->children;
- if (mc_dev) {
- tomk = restore_top_of_low_cacheable() / 1024;
- /* Report the memory regions
- All memory up to systop except 0xa0000-0xbffff */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
-
- set_late_cbmem_top(tomk * 1024);
- }
-
- assign_resources(dev->link_list);
-}
-
-static void pci_domain_enable(struct device *dev)
-{
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
- // do this here for now -- this chip really breaks our device model
- northbridge_init_early();
- cpubug();
- chipsetinit();
-
- do_vsmbios(); // do the magic stuff here, so prepare your tambourine;)
-
- graphics_init();
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .scan_bus = pci_domain_scan_bus,
- .enable = pci_domain_enable,
-};
-
-static void cpu_bus_init(struct device *dev)
-{
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
- __func__, dev->path.type);
-
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN)
- dev->ops = &pci_domain_ops;
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
- dev->ops = &cpu_bus_ops;
-}
-
-struct chip_operations northbridge_amd_lx_ops = {
- CHIP_NAME("AMD LX Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
deleted file mode 100644
index 51c2c14e75..0000000000
--- a/src/northbridge/amd/lx/northbridge.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_AMD_LX_H
-#define NORTHBRIDGE_AMD_LX_H
-
-/* northbridge.c */
-int sizeram(void);
-
-/* northbridgeinit.c */
-void northbridge_init_early(void);
-
-/* pll_reset.c */
-unsigned int GeodeLinkSpeed(void);
-void lx_pll_reset(void);
-
-void lx_msr_init(void);
-
-#endif
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
deleted file mode 100644
index 9655c0e4e0..0000000000
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <stdlib.h>
-#include <string.h>
-#include "northbridge.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-#include <cbmem.h>
-
-struct gliutable {
- unsigned long desc_name;
- unsigned short desc_type;
- unsigned long hi, lo;
-};
-
-struct gliutable gliu0table[] = {
- {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
- {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
- {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */
- {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */
- {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
- GL0_CPU},
- {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
-};
-
-struct gliutable gliu1table[] = {
- {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
- {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
- {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */
- {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */
- {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
- GL1_GLIU0},
- {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */
- {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
-};
-
-struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
-
-struct msrinit {
- unsigned long msrnum;
- msr_t msr;
-};
-
-struct msrinit ClockGatingDefault[] = {
- {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
- {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
- {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
- {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
- {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}},
- {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
- {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}},
- {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
- {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
- {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
- {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}},
- {0xffffffff, {0xffffffff, 0xffffffff}},
-};
-
-/* */
-/* SET GeodeLink PRIORITY*/
-/* */
-struct msrinit GeodeLinkPriorityTable[] = {
- {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}},
- {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}},
- {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}},
- {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}},
- {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}},
- {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}},
- {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}},
- {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}},
- {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
-};
-
-
-static void writeglmsr(struct gliutable *gl)
-{
- msr_t msr;
-
- msr.lo = gl->lo;
- msr.hi = gl->hi;
- wrmsr(gl->desc_name, msr); // MSR - see table above
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3
-}
-
-static void ShadowInit(struct gliutable *gl)
-{
- msr_t msr;
-
- msr = rdmsr(gl->desc_name);
-
- if (msr.lo == 0) {
- writeglmsr(gl);
- }
-}
-
-static void SysmemInit(struct gliutable *gl)
-{
- msr_t msr;
- int sizembytes, sizebytes;
-
- /*
- * Figure out how much RAM is in the machine and allocate all to the
- * system. We will adjust for SMM now and Frame Buffer later.
- */
- sizembytes = sizeram();
- printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
- sizebytes = sizembytes << 20;
-
- sizebytes -= ((SMM_SIZE * 1024) + 1);
- printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
-
- /* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
- The top 8 bits go into 0-7 of msr.hi. */
- sizebytes--;
- msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
- sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */
- sizebytes &= 0xfff00000;
- sizebytes |= 0x100; /* start at 1MB */
- msr.lo = sizebytes;
-
- wrmsr(gl->desc_name, msr); // MSR - see table above
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
- gl->desc_name, msr.hi, msr.lo);
-}
-
-static void SMMGL0Init(struct gliutable *gl)
-{
- msr_t msr;
- int sizebytes = sizeram() << 20;
- long offset;
-
- sizebytes -= (SMM_SIZE * 1024);
-
- printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
-
- /* calculate the Two's complement offset */
- offset = sizebytes - SMM_OFFSET;
- offset = (offset >> 12) & 0x000fffff;
- printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
-
- msr.hi = offset << 8 | gl->hi;
- msr.hi |= SMM_OFFSET >> 24;
-
- msr.lo = (SMM_OFFSET & 0x00ffffff) << 8;
- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
-
- wrmsr(gl->desc_name, msr); // MSR - See table above
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
- gl->desc_name, msr.hi, msr.lo);
-}
-
-static void SMMGL1Init(struct gliutable *gl)
-{
- msr_t msr;
- printk(BIOS_DEBUG, "%s:\n", __func__);
-
- msr.hi = gl->hi;
- /* I don't think this is needed */
- msr.hi &= 0xffffff00;
- msr.hi |= (SMM_OFFSET >> 24);
- msr.lo = (SMM_OFFSET & 0x00fff000) << 8;
- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
-
- wrmsr(gl->desc_name, msr); // MSR - See table above
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
- gl->desc_name, msr.hi, msr.lo);
-}
-
-static void GLIUInit(struct gliutable *gl)
-{
-
- while (gl->desc_type != GL_END) {
- switch (gl->desc_type) {
- default:
- /* For Unknown types: Write then read MSR */
- writeglmsr(gl);
- case SC_SHADOW: /* Check for a Shadow entry */
- ShadowInit(gl);
- break;
-
- case R_SYSMEM: /* check for a SYSMEM entry */
- SysmemInit(gl);
- break;
-
- case BMO_SMM: /* check for a SMM entry */
- SMMGL0Init(gl);
- break;
-
- case BM_SMM: /* check for a SMM entry */
- SMMGL1Init(gl);
- break;
- }
- gl++;
- }
-
-}
-
- /* ************************************************************************** */
- /* * */
- /* * GLPCIInit */
- /* * */
- /* * Set up GLPCI settings for reads/write into memory */
- /* * R0: 0-640KB, */
- /* * R1: 1MB - Top of System Memory */
- /* * R2: SMM Memory */
- /* * R3: Framebuffer? - not set up yet */
- /* * R4: ?? */
- /* * */
- /* * Entry: */
- /* * Exit: */
- /* * Modified: */
- /* * */
- /* ************************************************************************** */
-static void GLPCIInit(void)
-{
- struct gliutable *gl = NULL;
- int i;
- msr_t msr;
- int msrnum, enable_preempt, enable_cpu_override;
- int nic_grants_control, enable_bus_parking;
-
- /* */
- /* R0 - GLPCI settings for Conventional Memory space. */
- /* */
- msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
- msr.lo = 0; /* 0 */
- msr.lo |=
- GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +
- GLPCI_RC_LOWER_WC_SET;
- msrnum = GLPCI_RC0;
- wrmsr(msrnum, msr);
-
- /* */
- /* R1 - GLPCI settings for SysMem space. */
- /* */
- /* Get systop from GLIU0 SYSTOP Descriptor */
- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
- if (gliu0table[i].desc_type == R_SYSMEM) {
- gl = &gliu0table[i];
- break;
- }
- }
- if (gl) {
- unsigned long pah, pal;
- msrnum = gl->desc_name;
- msr = rdmsr(msrnum);
- /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
- * translates to a base of 0x00100000 and top of 0xffbf0000
- * base of 1M and top of around 256M
- */
- /* we have to create a page-aligned (4KB page) address for base and top */
- /* So we need a high page aligned address (pah) and low page aligned address (pal)
- * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
- */
- pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
- /* we have the page address. Now make it a page-aligned address */
- pah <<= 12;
-
- pal = msr.lo << 12;
- msr.hi = pah;
- msr.lo = pal;
- msr.lo |=
- GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
- GLPCI_RC_LOWER_WC_SET;
- printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
- msr.lo, msr.hi);
- msrnum = GLPCI_RC1;
- wrmsr(msrnum, msr);
- }
-
- /* */
- /* R2 - GLPCI settings for SMM space */
- /* */
- msr.hi =
- ((SMM_OFFSET +
- (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
- msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
- msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
- printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
- msr.hi);
- msrnum = GLPCI_RC2;
- wrmsr(msrnum, msr);
-
- /* this is done elsewhere already, but it does no harm to do it more than once */
- /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
- msr.lo = 0x021212121; /* cache disabled and write serialized */
- msr.hi = 0x021212121; /* cache disabled and write serialized */
-
- msrnum = CPU_RCONF_A0_BF;
- wrmsr(msrnum, msr);
-
- msrnum = CPU_RCONF_C0_DF;
- wrmsr(msrnum, msr);
-
- msrnum = CPU_RCONF_E0_FF;
- wrmsr(msrnum, msr);
-
- /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
- msrnum = GLPCI_A0_BF;
- msr.hi = 0x35353535;
- msr.lo = 0x35353535;
- wrmsr(msrnum, msr);
-
- msrnum = GLPCI_C0_DF;
- msr.hi = 0x35353535;
- msr.lo = 0x35353535;
- wrmsr(msrnum, msr);
-
- msrnum = GLPCI_E0_FF;
- msr.hi = 0x35353535;
- msr.lo = 0x35353535;
- wrmsr(msrnum, msr);
-
- /* Set WSREQ */
- msrnum = CPU_DM_CONFIG0;
- msr = rdmsr(msrnum);
- msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
- msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT; /* reduce to 1 for safe mode */
- wrmsr(msrnum, msr);
-
- /* we are ignoring the 5530 case for now, and perhaps forever. */
-
- /* */
- /* 553x NB Init */
- /* */
-
- /* Arbiter setup */
- enable_preempt =
- GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET |
- GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
- enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;
- enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;
- nic_grants_control =
- (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 <<
- GLPCI_ARB_UPPER_H2_SHIFT);
-
- msrnum = GLPCI_ARB;
- msr = rdmsr(msrnum);
-
- msr.hi |= nic_grants_control;
- msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking;
- wrmsr(msrnum, msr);
-
- msrnum = GLPCI_CTRL;
- msr = rdmsr(msrnum);
-
- msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
- msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
-
- msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
- msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
-
- msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
- msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
-
- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
-
- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
-
- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
-
- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
- msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
-
- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
- msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
- wrmsr(msrnum, msr);
-
- /* Set GLPCI Latency Timer */
- msrnum = GLPCI_CTRL;
- msr = rdmsr(msrnum);
- msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */
- wrmsr(msrnum, msr);
-
- /* GLPCI_SPARE */
- msrnum = GLPCI_SPARE;
- msr = rdmsr(msrnum);
- msr.lo &= ~0x7;
- msr.lo |=
- GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET |
- GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET |
- GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
- wrmsr(msrnum, msr);
-}
-
- /* ************************************************************************** */
- /* * */
- /* * ClockGatingInit */
- /* * */
- /* * Enable Clock Gating. */
- /* * */
- /* * Entry: */
- /* * Exit: */
- /* * Modified: */
- /* * */
- /* ************************************************************************** */
-static void ClockGatingInit(void)
-{
- msr_t msr;
- struct msrinit *gating = ClockGatingDefault;
- int i;
-
- for (i = 0; gating->msrnum != 0xffffffff; i++) {
- msr = rdmsr(gating->msrnum);
- msr.hi |= gating->msr.hi;
- msr.lo |= gating->msr.lo;
- /* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
- gating->msrnum, msr.hi, msr.lo); */// GX3
- wrmsr(gating->msrnum, msr); // MSR - See the table above
- gating += 1;
- }
-
-}
-
-static void GeodeLinkPriority(void)
-{
- msr_t msr;
- struct msrinit *prio = GeodeLinkPriorityTable;
- int i;
-
- for (i = 0; prio->msrnum != 0xffffffff; i++) {
- msr = rdmsr(prio->msrnum);
- msr.hi |= prio->msr.hi;
- msr.lo &= ~0xfff;
- msr.lo |= prio->msr.lo;
- /* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
- prio->msrnum, msr.hi, msr.lo); */// GX3
- wrmsr(prio->msrnum, msr); // MSR - See the table above
- prio += 1;
- }
-}
-
-/*
- * Get the GLIU0 shadow register settings
- * If the setShadow function is used then all shadow descriptors
- * will stay sync'ed.
- */
-static uint64_t getShadow(void)
-{
- msr_t msr;
-
- msr = rdmsr(MSR_GLIU0_SHADOW);
- return (((uint64_t) msr.hi) << 32) | msr.lo;
-}
-
-/*
- * Set the cache RConf registers for the memory hole.
- * Keeps all cache shadow descriptors sync'ed.
- * This is part of the PCI lockup solution
- * Entry: EDX:EAX is the shadow settings
- */
-static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
-{
-
- // ok this is whacky bit translation time.
- int bit;
- uint8_t shadowByte;
- msr_t msr = { 0, 0 };
- shadowByte = (uint8_t) (shadowLo >> 16);
-
- // load up D000 settings in edx.
- for (bit = 7; bit >= 4; bit--) {
- msr.hi <<= 8;
- msr.hi |= 1; // cache disable PCI/Shadow memory
- if (shadowByte & (1 << bit))
- msr.hi |= 0x20; // write serialize PCI memory
- }
-
- // load up C000 settings in eax.
- for (; bit >= 0; bit--) {
- msr.lo <<= 8;
- msr.lo |= 1; // cache disable PCI/Shadow memory
- if (shadowByte & (1 << bit))
- msr.lo |= 0x20; // write serialize PCI memory
- }
-
- wrmsr(CPU_RCONF_C0_DF, msr);
-
- shadowByte = (uint8_t) (shadowLo >> 24);
-
- // load up F000 settings in edx.
- for (bit = 7; bit >= 4; bit--) {
- msr.hi <<= 8;
- msr.hi |= 1; // cache disable PCI/Shadow memory
- if (shadowByte & (1 << bit))
- msr.hi |= 0x20; // write serialize PCI memory
- }
-
- // load up E000 settings in eax.
- for (; bit >= 0; bit--) {
- msr.lo <<= 8;
- msr.lo |= 1; // cache disable PCI/Shadow memory
- if (shadowByte & (1 << bit))
- msr.lo |= 0x20; // write serialize PCI memory
- }
-
- wrmsr(CPU_RCONF_E0_FF, msr);
-}
-
-/*
- * Set the GLPCI registers for the memory hole.
- * Keeps all cache shadow descriptors sync'ed.
- * Entry: EDX:EAX is the shadow settings
- */
-static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
-{
- msr_t msr;
-
-// Set the Enable Register.
- msr = rdmsr(GLPCI_REN);
- msr.lo &= 0xFFFF00FF;
- msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
- wrmsr(GLPCI_REN, msr);
-}
-
-/*
- * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
- * Keeps all shadow descriptors sync'ed.
- * Entry: EDX:EAX is the shadow settings
- */
-static void setShadow(uint64_t shadowSettings)
-{
- int i;
- msr_t msr;
- struct gliutable *pTable;
- uint32_t shadowLo, shadowHi;
-
- shadowLo = (uint32_t) shadowSettings;
- shadowHi = (uint32_t) (shadowSettings >> 32);
-
- setShadowRCONF(shadowHi, shadowLo);
- setShadowGLPCI(shadowHi, shadowLo);
-
- for (i = 0; gliutables[i]; i++) {
- for (pTable = gliutables[i]; pTable->desc_type != GL_END;
- pTable++) {
- if (pTable->desc_type == SC_SHADOW) {
-
- msr = rdmsr(pTable->desc_name);
- msr.lo = (uint32_t) shadowSettings;
- msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX
- msr.hi |=
- ((uint32_t) (shadowSettings >> 32)) &
- 0x0000FFFF;
- wrmsr(pTable->desc_name, msr); // MSR - See the table above
- }
- }
- }
-}
-
-static void rom_shadow_settings(void)
-{
-
- uint64_t shadowSettings = getShadow();
- shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes
- shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF
- shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF
- setShadow(shadowSettings);
-}
-
-/***************************************************************************
- *
- * L1Init
- * Set up RCONF_DEFAULT and any other RCONF registers needed
- *
- * DEVRC_RCONF_DEFAULT:
- * ROMRC(63:56) = 04h ; write protect ROMBASE
- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
- * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
- * SYSTOP(27:8) = top of system memory
- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
- *
- ***************************************************************************/
-#define SYSMEM_RCONF_WRITETHROUGH 8
-#define DEVRC_RCONF_DEFAULT 0x21ul
-#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
-#define ROMRC_RCONF_DEFAULT 0x25
-
-static void enable_L1_cache(void)
-{
- struct gliutable *gl = NULL;
- int i;
- msr_t msr;
- uint8_t SysMemCacheProp;
-
- /* Locate SYSMEM entry in GLIU0table */
- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
- if (gliu0table[i].desc_type == R_SYSMEM) {
- gl = &gliu0table[i];
- break;
- }
- }
- if (gl == 0) {
- post_code(0xCE); /* POST_RCONFInitError */
- while (1) ;
- }
-// sysdescfound:
- msr = rdmsr(gl->desc_name);
-
- /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the
- * top 8 bits go into 0-7 of edx.
- */
- msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
- msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
- msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8
-
- // Set Default SYSMEM region properties
- msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // NOT writethrough == writeback 8 (or ~8)
-
- // Set PCI space cache properties
- msr.hi = (DEVRC_RCONF_DEFAULT >> 4); // setting is split betwwen hi and lo...
- msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
-
- // Set the ROMBASE. This is usually FFFC0000h
- msr.hi |=
- (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
-
- // Set ROMBASE cache properties.
- msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
-
- // now program RCONF_DEFAULT
- wrmsr(CPU_RCONF_DEFAULT, msr);
- printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
- msr.lo);
-
- // RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
- // Set to match system memory cache properties.
- msr = rdmsr(CPU_RCONF_DEFAULT);
- SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
- msr = rdmsr(CPU_RCONF_BYPASS);
- msr.lo =
- (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
- wrmsr(CPU_RCONF_BYPASS, msr);
-
- printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
- msr.lo);
-}
-
-static void enable_L2_cache(void)
-{
- msr_t msr;
-
- /* Instruction Memory Configuration register
- * set EBE bit, required when L2 cache is enabled
- */
- msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= 0x400;
- wrmsr(CPU_IM_CONFIG, msr);
-
- /* Data Memory Subsystem Configuration register
- * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
- */
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= 0x4000;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- /* invalidate L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x10;
- wrmsr(CPU_BC_L2_CONF, msr);
-
- /* Enable L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x0f;
- wrmsr(CPU_BC_L2_CONF, msr);
-
- printk(BIOS_DEBUG, "L2 cache enabled\n");
-}
-
-static void setup_lx_cache(void)
-{
- msr_t msr;
-
- enable_L1_cache();
- enable_L2_cache();
-
- // Make sure all INVD instructions are treated as WBINVD. We do this
- // because we've found some programs which require this behavior.
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- x86_enable_cache();
- wbinvd();
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- uint32_t systop;
- msr_t msr;
-
- msr = rdmsr(MSR_GLIU0_SYSMEM);
- systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
- systop += 0x1000; /* 4K */
-
- return systop;
-}
-
-/****************************************************************************/
-/* * northbridge_init_early */
-/* **/
-/* * Core Logic initialization: Host bridge*/
-/* **/
-/* ***************************************************************************/
-void northbridge_init_early(void)
-{
- int i;
- printk(BIOS_DEBUG, "Enter %s\n", __func__);
-
- for (i = 0; gliutables[i]; i++)
- GLIUInit(gliutables[i]);
-
- /* Now that the descriptor to memory is set up. */
- /* The memory controller needs one read to synch its lines before it can be used. */
- read32(zeroptr);
-
- GeodeLinkPriority();
-
- setup_lx_cache();
-
- rom_shadow_settings();
-
- GLPCIInit();
-
- ClockGatingInit();
-
- __asm__ __volatile__("FINIT\n");
- printk(BIOS_DEBUG, "Exit %s\n", __func__);
-}
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
deleted file mode 100644
index cb332ead12..0000000000
--- a/src/northbridge/amd/lx/pll_reset.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "northbridge.h"
-
-void lx_pll_reset(void)
-{
- msr_t msrGlcpSysRstpll;
-
- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
-
- printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n",
- GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
-
- post_code(POST_PLL_INIT);
-
- if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
- printk(BIOS_DEBUG, "Configuring PLL.\n");
- if (CONFIG_PLL_MANUAL_CONFIG) {
- post_code(POST_PLL_MANUAL);
- /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;
-
- /* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;
- } else {
- /*automatic configuration (straps) */
- post_code(POST_PLL_STRAP);
- msrGlcpSysRstpll.lo &=
- ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
- msrGlcpSysRstpll.lo |=
- (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
- msrGlcpSysRstpll.lo &=
- ~(RSTPPL_LOWER_COREBYPASS_SET |
- RSTPPL_LOWER_MBBYPASS_SET);
- msrGlcpSysRstpll.lo |=
- RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
- }
- /* Use SWFLAGS to remember: "we've already been here" */
- msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
-
- /* "reset the chip" value */
- msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
-
- /* You should never get here..... The chip has reset. */
- post_code(POST_PLL_RESET_FAIL);
- die("CONFIGURING PLL FAILURE\n");
-
- }
- printk(BIOS_DEBUG, "PLL configured.\n");
- return;
-}
-
-unsigned int GeodeLinkSpeed(void)
-{
- unsigned int speed;
- msr_t msr;
-
- msr = rdmsr(GLCP_SYS_RSTPLL);
- speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
- if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
- ++speed;
- }
- return (speed);
-}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
deleted file mode 100644
index 8de85a346e..0000000000
--- a/src/northbridge/amd/lx/raminit.c
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <arch/io.h>
-#include <spd.h>
-#include <stddef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include "raminit.h"
-#include "northbridge.h"
-
-static const unsigned char NumColAddr[] = {
- 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
-};
-
-static void banner(const char *s)
-{
- printk(BIOS_DEBUG, " * %s\n", s);
-}
-
-static void __noreturn hcf(void)
-{
- printk(BIOS_EMERG, "DIE\n");
- /* this guarantees we flush the UART fifos (if any) and also
- * ensures that things, in general, keep going so no debug output
- * is lost
- */
- while (1)
- printk(BIOS_EMERG, "%c", 0);
-}
-
-static void auto_size_dimm(unsigned int dimm)
-{
- uint32_t dimm_setting;
- uint16_t dimm_size;
- uint8_t spd_byte;
- msr_t msr;
-
- dimm_setting = 0;
-
- banner("Check present");
- /* Check that we have a dimm */
- if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
- return;
- }
-
- banner("MODBANKS");
- /* Field: Module Banks per DIMM */
- /* EEPROM byte usage: (5) Number of DIMM Banks */
- spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
- if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
- printk(BIOS_EMERG, "Number of module banks not compatible\n");
- post_code(ERROR_BANK_SET);
- hcf();
- }
- dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
- banner("FIELDBANKS");
-
- /* Field: Banks per SDRAM device */
- /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
- spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
- if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
- printk(BIOS_EMERG, "Number of device banks not compatible\n");
- post_code(ERROR_BANK_SET);
- hcf();
- }
- dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
- banner("SPDNUMROWS");
-
- /*; Field: DIMM size
- *; EEPROM byte usage: (3) Number of Row Addresses
- *; (4) Number of Column Addresses
- *; (5) Number of DIMM Banks
- *; (31) Module Bank Density
- *; Size = Module Density * Module Banks
- */
- if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
- || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
- printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
- hcf();
- }
- banner("SPDBANKDENSITY");
-
- dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
- banner("DIMMSIZE");
- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
-
- /* Module Density * Module Banks */
- dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
- banner("BEFORT CTZ");
- dimm_size = __builtin_ctz(dimm_size);
- banner("TEST DIMM SIZE > 8");
- if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
- printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
- post_code(ERROR_DENSITY_DIMM);
- hcf();
- }
- dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
- banner("PAGESIZE");
-
-/*; Field: PAGE size
-*; EEPROM byte usage: (4) Number of Column Addresses
-*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
-*
-*; But this really works by magic.
-*;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
-*;that MC generates, here is how the MC assigns the pa onto the ma pins:
-*
-*;ma 12 11 10 09 08 07 06 05 04 03 02 01 00
-*;-------------------------------------------
-*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
-*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
-*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
-*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
-*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
-*;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)
-*; *AP = autoprecharge bit
-*
-*;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
-*;so lower 3 address bits are dont_cares.So from the table above,
-*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h),
-*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/
-
- spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
- banner("MAXCOLADDR");
- if (spd_byte > MAX_COL_ADDR) {
- printk(BIOS_EMERG, "DIMM page size not compatible\n");
- post_code(ERROR_SET_PAGE);
- hcf();
- }
- banner(">12address test");
- spd_byte -= 7;
- if (spd_byte > 5) { /* if the value is above 6 it means > 12 address lines */
- spd_byte = 7; /* which means > 32k so set to disabled */
- }
- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */
-
- banner("RDMSR CF07");
- msr = rdmsr(MC_CF07_DATA);
- banner("WRMSR CF07");
- if (dimm == DIMM0) {
- msr.hi &= 0xFFFF0000;
- msr.hi |= dimm_setting;
- } else {
- msr.hi &= 0x0000FFFF;
- msr.hi |= dimm_setting << 16;
- }
- wrmsr(MC_CF07_DATA, msr);
- banner("ALL DONE");
-}
-
-static void checkDDRMax(void)
-{
- uint8_t spd_byte0, spd_byte1;
- uint16_t speed;
-
- /* PC133 identifier */
- spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
-
- /* I don't think you need this check.
- if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) {
- printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
- post_code(POST_PLL_MEM_FAIL);
- hcf();
- } */
-
- /* Use the slowest DIMM */
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- /* Turn SPD ns time into MHz. Check what the asm does to this math. */
- speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
-
- /* current speed > max speed? */
- if (GeodeLinkSpeed() > speed) {
- printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
- post_code(POST_PLL_MEM_FAIL);
- hcf();
- }
-}
-
-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
-
-static void set_refresh_rate(void)
-{
- uint8_t spd_byte0, spd_byte1;
- uint16_t rate0, rate1;
- msr_t msr;
-
- spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
- spd_byte0 &= 0xF;
- if (spd_byte0 > 5) {
- spd_byte0 = 5;
- }
- rate0 = REF_RATE[spd_byte0];
-
- spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
- spd_byte1 &= 0xF;
- if (spd_byte1 > 5) {
- spd_byte1 = 5;
- }
- rate1 = REF_RATE[spd_byte1];
-
- /* Use the faster rate (lowest number) */
- if (rate0 > rate1) {
- rate0 = rate1;
- }
-
- msr = rdmsr(MC_CF07_DATA);
- msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
- << CF07_LOWER_REF_INT_SHIFT;
- wrmsr(MC_CF07_DATA, msr);
-}
-
-const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-
-static u8 getcasmap(u32 dimm, u16 glspeed)
-{
- u16 dimm_speed;
- u8 spd_byte, casmap, casmap_shift = 0;
-
- /************************** DIMM0 **********************************/
- casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
- if (casmap != 0xFF) {
- /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
- if (spd_byte != 0) {
- /* Turn SPD ns time into MHz. Check what the asm does to this math. */
- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
- if (dimm_speed >= glspeed) {
- casmap_shift = 1; /* -.5 is a shift of 1 */
- /* IF -1 timing is supported, check -1 timing > GeodeLink */
- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
- if (spd_byte != 0) {
- /* Turn SPD ns time into MHz. Check what the asm does to this math. */
- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
- if (dimm_speed >= glspeed) {
- casmap_shift = 2; /* -1 is a shift of 2 */
- }
- } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
- } else {
- casmap_shift = 0;
- }
- } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
- /* set the casmap based on the shift to limit possible CAS settings */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap &= 0xFF << (spd_byte - casmap_shift);
- } else { /* No DIMM */
- casmap = 0;
- }
- return casmap;
-}
-
-static void setCAS(void)
-{
-/*;*****************************************************************************
-;*
-;* setCAS
-;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
-;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
-;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
-;*
-;* The CAS setting is based on the information provided in each DIMMs SPD.
-;* The speed at which a DIMM can run is described relative to the slowest
-;* CAS the DIMM supports. Each speed for the relative CAS settings is
-;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
-;* speed, the CAS setting is removed from the list of good settings for
-;* the DIMM. This is done for both DIMMs and the lists are compared to
-;* find the lowest common CAS latency setting. If there are no CAS settings
-;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
-;*
-;* Entry:
-;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
-;* Destroys: We really use everything !
-;*****************************************************************************/
- uint16_t glspeed;
- uint8_t spd_byte, casmap0, casmap1;
- msr_t msr;
-
- glspeed = GeodeLinkSpeed();
-
- casmap0 = getcasmap(DIMM0, glspeed);
- casmap1 = getcasmap(DIMM1, glspeed);
-
- /********************* CAS_LAT MAP COMPARE ***************************/
- if (casmap0 == 0) {
- spd_byte = CASDDR[__builtin_ctz(casmap1)];
- } else if (casmap1 == 0) {
- spd_byte = CASDDR[__builtin_ctz(casmap0)];
- } else if ((casmap0 &= casmap1)) {
- spd_byte = CASDDR[__builtin_ctz(casmap0)];
- } else {
- printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
- post_code(ERROR_DIFF_DIMMS);
- hcf();
- }
-
- msr = rdmsr(MC_CF8F_DATA);
- msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
- msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
- wrmsr(MC_CF8F_DATA, msr);
-}
-
-static void set_latencies(void)
-{
- uint32_t memspeed, dimm_setting;
- uint8_t spd_byte0, spd_byte1;
- msr_t msr;
-
- memspeed = GeodeLinkSpeed() / 2;
- dimm_setting = 0;
-
- /* MC_CF8F setup */
- /* tRAS */
- spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
- spd_byte1 = (spd_byte0 * memspeed) / 1000;
- if (((spd_byte0 * memspeed) % 1000)) {
- ++spd_byte1;
- }
- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
-
- /* tRP */
- spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
- ++spd_byte1;
- }
- dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
-
- /* tRCD */
- spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
- ++spd_byte1;
- }
- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
-
- /* tRRD */
- spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
- ++spd_byte1;
- }
- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
-
- /* tRC = tRP + tRAS */
- dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
- << CF8F_LOWER_ACT2ACTREF_SHIFT;
-
- msr = rdmsr(MC_CF8F_DATA);
- msr.lo &= 0xF00000FF;
- msr.lo |= dimm_setting;
- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
- wrmsr(MC_CF8F_DATA, msr);
-
- /* MC_CF1017 setup */
- /* tRFC */
- spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- if (spd_byte0 < spd_byte1) {
- spd_byte0 = spd_byte1;
- }
-
- if (spd_byte0) {
- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
- spd_byte1 = (spd_byte0 * memspeed) / 1000;
- if (((spd_byte0 * memspeed) % 1000)) {
- ++spd_byte1;
- }
- } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
- spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
- }
- dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
- msr = rdmsr(MC_CF1017_DATA);
- msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
- msr.lo |= dimm_setting;
- wrmsr(MC_CF1017_DATA, msr);
-
- /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200MHz mem) other wise it stay default(1) */
- if (memspeed > 198) {
- msr = rdmsr(MC_CF1017_DATA);
- msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
- msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
- wrmsr(MC_CF1017_DATA, msr);
- }
-}
-
-static void set_extended_mode_registers(void)
-{
- uint8_t spd_byte0, spd_byte1;
- msr_t msr;
- spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
- if (spd_byte0 == 0xFF) {
- spd_byte0 = 0;
- }
- spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
- if (spd_byte1 == 0xFF) {
- spd_byte1 = 0;
- }
- spd_byte1 &= spd_byte0;
-
- msr = rdmsr(MC_CF07_DATA);
- if (spd_byte1 & 1) { /* Drive Strength Control */
- msr.lo |= CF07_LOWER_EMR_DRV_SET;
- }
- if (spd_byte1 & 2) { /* FET Control */
- msr.lo |= CF07_LOWER_EMR_QFC_SET;
- }
- wrmsr(MC_CF07_DATA, msr);
-}
-
-#undef TLA_MEMORY_DEBUG
-#ifdef TLA_MEMORY_DEBUG
-static void EnableMTest(void)
-{
- msr_t msr;
-
- msr = rdmsr(GLCP_DELAY_CONTROLS);
- msr.hi &= ~(7 << 20); /* clear bits 54:52 */
- if (GeodeLinkSpeed() < 200) {
- msr.hi |= 2 << 20;
- }
- wrmsr(GLCP_DELAY_CONTROLS, msr);
-
- msr = rdmsr(MC_CFCLK_DBUG);
- msr.hi |=
- CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
- CFCLK_UPPER_MTST_RBEX_EN_SET;
- msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
- wrmsr(MC_CFCLK_DBUG, msr);
-
- printk(BIOS_INFO, "Enabled MTest for TLA debug\n");
-}
-#endif
-
-void sdram_set_registers(const struct mem_controller *ctrl)
-{
- msr_t msr;
- uint32_t msrnum;
-
- /* Set Timing Control */
- msrnum = MC_CF1017_DATA;
- msr = rdmsr(msrnum);
- msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
- if (GeodeLinkSpeed() < 334) {
- msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
- } else {
- msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
- }
- wrmsr(msrnum, msr);
-
- /* Set Refresh Staggering */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo &= ~0xF0;
- msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
- wrmsr(msrnum, msr);
-
- /* Memory Interleave: Set HOI here otherwise default is LOI */
- /* msrnum = MC_CF8F_DATA;
- msr = rdmsr(msrnum);
- msr.hi |= CF8F_UPPER_HOI_LOI_SET;
- wrmsr(msrnum, msr); */
-}
-
-void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
- uint8_t spd_byte;
-
- banner("sdram_set_spd_register");
- post_code(POST_MEM_SETUP); // post_70h
-
- spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
- banner("Check DIMM 0");
- /* Check DIMM is not Register and not Buffered DIMMs. */
- if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
- hcf();
- }
- banner("Check DIMM 1");
- spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
- if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
- post_code(ERROR_UNSUPPORTED_DIMM);
- hcf();
- }
-
- post_code(POST_MEM_SETUP2); // post_72h
- banner("Check DDR MAX");
-
- /* Check that the memory is not overclocked. */
- checkDDRMax();
-
- /* Size the DIMMS */
- post_code(POST_MEM_SETUP3); // post_73h
- banner("AUTOSIZE DIMM 0");
- auto_size_dimm(DIMM0);
- post_code(POST_MEM_SETUP4); // post_74h
- banner("AUTOSIZE DIMM 1");
- auto_size_dimm(DIMM1);
-
- /* Set CAS latency */
- banner("set cas latency");
- post_code(POST_MEM_SETUP5); // post_75h
- setCAS();
-
- /* Set all the other latencies here (tRAS, tRP....) */
- banner("set all latency");
- set_latencies();
-
- /* Set Extended Mode Registers */
- banner("set emrs");
- set_extended_mode_registers();
-
- banner("set ref rate");
- /* Set Memory Refresh Rate */
- set_refresh_rate();
-
-}
-
-/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
- * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
-void sdram_enable(int controllers, const struct mem_controller *ctrl)
-{
- uint32_t i, msrnum;
- msr_t msr;
-
-/*********************************************************************
-;* Turn on MC/DIMM interface per JEDEC
-;* 1) Clock stabilizes > 200us
-;* 2) Assert CKE
-;* 3) Precharge All to put all banks into an idles state
-;* 4) EMRS to enable DLL
-;* 6) MRS w/ memory config & reset DLL set
-;* 7) Wait 200 clocks (2us)
-;* 8) Precharge All and 2 Auto refresh
-;* 9) MRS w/ memory config & reset DLL clear
-;* 8) DDR SDRAM ready for normal operation
-;********************************************************************/
- post_code(POST_MEM_ENABLE); // post_76h
-
-#ifdef TLA_MEMORY_DEBUG
- /* Only enable MTest for TLA memory debug */
- EnableMTest();
-#endif
-
- /* If both Page Size = "Not Installed" we have a problems and should halt. */
- msr = rdmsr(MC_CF07_DATA);
- if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
- ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- printk(BIOS_EMERG, "No memory in the system\n");
- post_code(ERROR_NO_DIMMS);
- hcf();
- }
-
- /* Set CKEs */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
- wrmsr(msrnum, msr);
-
- /* Force Precharge All on next command, EMRS */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
- wrmsr(msrnum, msr);
-
- /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
- wrmsr(msrnum, msr);
- msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
- wrmsr(msrnum, msr);
-
- /* Clear Force Precharge All */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
- wrmsr(msrnum, msr);
-
- /* MRS Reset DLL - set */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
- wrmsr(msrnum, msr);
- msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
- wrmsr(msrnum, msr);
-
- /* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */
- /* Wait 2 PORT61 ticks. between 15us and 30us */
- /* This would be endless if the timer is stuck. */
- while ((inb(0x61))); /* find the first edge */
- while (!(~inb(0x61)));
-
- /* Force Precharge All on the next command, auto-refresh */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
- wrmsr(msrnum, msr);
-
- /* Manually AUTO refresh #1 */
- /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= CF07_LOWER_REF_TEST_SET;
- wrmsr(msrnum, msr);
- msr.lo &= ~CF07_LOWER_REF_TEST_SET;
- wrmsr(msrnum, msr);
-
- /* Clear Force Precharge All */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
- wrmsr(msrnum, msr);
-
- /* Manually AUTO refresh */
- /* The MC should insert the right delay between the refreshes */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= CF07_LOWER_REF_TEST_SET;
- wrmsr(msrnum, msr);
- msr.lo &= ~CF07_LOWER_REF_TEST_SET;
- wrmsr(msrnum, msr);
-
- /* MRS Reset DLL - clear */
- msrnum = MC_CF07_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= CF07_LOWER_PROG_DRAM_SET;
- wrmsr(msrnum, msr);
- msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
- wrmsr(msrnum, msr);
-
- /* Allow MC to tristate during idle cycles with MTEST OFF */
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
- wrmsr(msrnum, msr);
-
- /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
- msr = rdmsr(MC_CF07_DATA);
- if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
- (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
- msrnum = GLCP_DELAY_CONTROLS;
- msr = rdmsr(msrnum);
- msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
- wrmsr(msrnum, msr);
- }
-
- /* Set PMode0 Sensitivity Counter */
- msr.lo = 0; /* pmode 0 = 0 most aggressive */
- msr.hi = 0x200; /* pmode 1 = 200h */
- wrmsr(MC_CF_PMCTR, msr);
-
- /* Set PMode1 Up delay enable */
- msrnum = MC_CF1017_DATA;
- msr = rdmsr(msrnum);
- msr.lo |= (209 << 8); /* bits[15:8] = 209 */
- wrmsr(msrnum, msr);
-
- banner("DRAM controller init done.\n");
- post_code(POST_MEM_SETUP_GOOD); //0x7E
-
- /* make sure there is nothing stale in the cache */
- /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
-
- /* The RAM dll needs a write to lock on so generate a few dummy writes */
- /* Note: The descriptor needs to be enabled to point at memory */
- for (i = 0; i < 5; i++) {
- write32(zeroptr + i, i);
- }
- /* SWAPSiF for PBZ 4112 (Errata 34) */
- /* check for failed DLL settings now that we have done a memory write. */
- msrnum = GLCP_DELAY_CONTROLS;
- msr = rdmsr(msrnum);
- if ((msr.lo & 0x7FF) == 0x104) {
-
- /* If you had it you would need to clear out the fail boot count flag */
- /* (depending on where it counts from etc). */
-
- /* The reset we are about to perform clears the PM_SSC register in the */
- /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
- /* it would do a normal boot */
-
- /* Reset the system */
- msrnum = MDD_SOFT_RESET;
- msr = rdmsr(msrnum);
- msr.lo |= 1;
- wrmsr(msrnum, msr);
- }
- printk(BIOS_INFO, "RAM DLL lock\n");
-
-}
diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h
deleted file mode 100644
index a1c0fcde20..0000000000
--- a/src/northbridge/amd/lx/raminit.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-#include <stdint.h>
-
-#define DIMM_SOCKETS 2
-
-struct mem_controller {
- uint16_t channel0[DIMM_SOCKETS];
-};
-
-void sdram_set_registers(const struct mem_controller *ctrl);
-void sdram_set_spd_registers(const struct mem_controller *ctrl);
-void sdram_enable(int controllers, const struct mem_controller *ctrl);
-
-void sdram_initialize(int controllers, const struct mem_controller *ctrl);
-
-/* mainboard specific */
-int spd_read_byte(unsigned int device, unsigned int address);
-
-#endif
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig
deleted file mode 100644
index 6b06c33642..0000000000
--- a/src/southbridge/amd/cs5536/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_AMD_CS5536
- bool
- select UDELAY_TSC
-
-if SOUTHBRIDGE_AMD_CS5536
-
-config NO_EARLY_SMBUS
- def_bool n
- help
- Skip the CS5536 early SMBUS initialization.
-
-endif
diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc
deleted file mode 100644
index 4bd88ac587..0000000000
--- a/src/southbridge/amd/cs5536/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
-
-romstage-y += early_smbus.c
-romstage-y += early_setup.c
-
-ramstage-y += cs5536.c
-ramstage-y += ide.c
-ramstage-y += pirq.c
-ramstage-y += smbus.c
-romstage-y += smbus.c
-
-endif
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
deleted file mode 100644
index f5411c04f2..0000000000
--- a/src/southbridge/amd/cs5536/chip.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOUTHBRIDGE_AMD_CS5536
-#define _SOUTHBRIDGE_AMD_CS5536
-
-#define MAX_UNWANTED_VPCI 8 /* increase if needed */
-
-struct southbridge_amd_cs5536_config {
- unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
- unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
- unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */
- unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
- unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
- unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */
- unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
- unsigned char com1_enable; /* enable COM1 */
- unsigned int com1_address; /* e.g. 0x3F8 */
- unsigned int com1_irq; /* e.g. 4 */
- unsigned char com2_enable; /* enable COM2 */
- unsigned int com2_address; /* e.g. 0x2F8 */
- unsigned int com2_irq; /* e.g. 3 */
- unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */
-};
-
-#endif /* _SOUTHBRIDGE_AMD_CS5536 */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
deleted file mode 100644
index 956994d623..0000000000
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <device/smbus.h>
-#include <console/console.h>
-#include <stdint.h>
-#include <pc80/isa-dma.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8259.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/vr.h>
-#include <stdlib.h>
-#include "chip.h"
-#include "cs5536.h"
-#include "smbus.h"
-
-struct msrinit {
- u32 msrnum;
- msr_t msr;
-};
-
-/* Master Configuration Register for Bus Masters.*/
-static struct msrinit SB_MASTER_CONF_TABLE[] = {
- {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
- {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
- {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
- {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}},
- {0, {0, 0}}
-};
-
-/* 5536 Clock Gating*/
-static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
- /* MSR Setting*/
- {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
- {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
- {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
- {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
- {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
- {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
- {0, {0, 0}}
-};
-
-struct acpiinit {
- u16 ioreg;
- u32 regdata;
-};
-
-static struct acpiinit acpi_init_table[] = {
- {ACPI_IO_BASE + 0x00, 0x01000000},
- {ACPI_IO_BASE + 0x08, 0},
- {ACPI_IO_BASE + 0x0C, 0},
- {ACPI_IO_BASE + 0x1C, 0},
- {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
- {ACPI_IO_BASE + 0x00, 0x0000FFFF},
- {PMS_IO_BASE + PM_SCLK, 0x000000E00},
- {PMS_IO_BASE + PM_SED, 0x000004601},
- {PMS_IO_BASE + PM_SIDD, 0x000008C02},
- {PMS_IO_BASE + PM_WKD, 0x0000000A0},
- {PMS_IO_BASE + PM_WKXD, 0x0000000A0},
- {0, 0}
-};
-
-struct FLASH_DEVICE {
- unsigned char fType; /* Flash type: NOR or NAND */
- unsigned char fInterface; /* Flash interface: I/O or Memory */
- unsigned long fMask; /* Flash size/mask */
-};
-
-static struct FLASH_DEVICE FlashInitTable[] = {
- {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */
- {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */
- {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */
- {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
-};
-
-#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
-
-static u32 FlashPort[] = {
- MDD_LBAR_FLSH0,
- MDD_LBAR_FLSH1,
- MDD_LBAR_FLSH2,
- MDD_LBAR_FLSH3
-};
-
-/* ***************************************************************************/
-/* **/
-/* * pmChipsetInit*/
-/* **/
-/* * Program ACPI LBAR and initialize ACPI registers.*/
-/* **/
-/* ***************************************************************************/
-static void pmChipsetInit(void)
-{
- u32 val = 0;
- u16 port;
-
- port = (PMS_IO_BASE + 0x010);
- val = 0x0E00; /* 1ms */
- outl(val, port);
-
- /* PM_WKXD */
- /* Make sure bits[3:0]=0000b to clear the */
- /* saved Sx state */
- port = (PMS_IO_BASE + 0x034);
- val = 0x0A0; /* 5ms */
- outl(val, port);
-
- /* PM_WKD */
- port = (PMS_IO_BASE + 0x030);
- outl(val, port);
-
- /* PM_SED */
- port = (PMS_IO_BASE + 0x014);
- val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */
- outl(val, port);
-
- /* PM_SIDD */
- port = (PMS_IO_BASE + 0x020);
- val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */
- outl(val, port);
-}
-
-/***************************************************************************
- *
- * ChipsetFlashSetup
- *
- * Flash LBARs need to be setup before VSA init so the PCI BARs have
- * correct size info. Call this routine only if flash needs to be
- * configured (don't call it if you want IDE).
- *
- **************************************************************************/
-static void ChipsetFlashSetup(void)
-{
- msr_t msr;
- int i;
- int numEnabled = 0;
-
- printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n");
- for (i = 0; i < FlashInitTableLen; i++) {
- if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
- printk(BIOS_DEBUG, "Enable CS%d\n", i);
- /* we need to configure the memory/IO mask */
- msr = rdmsr(FlashPort[i]);
- msr.hi = 0; /* start with the "enabled" bit clear */
- if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
- msr.hi |= 0x00000002;
- else
- msr.hi &= ~0x00000002;
- if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
- msr.hi |= 0x00000004;
- else
- msr.hi &= ~0x00000004;
- msr.hi |= FlashInitTable[i].fMask;
- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
- msr.hi, msr.lo);
- wrmsr(FlashPort[i], msr);
-
- /* now write-enable the device */
- msr = rdmsr(MDD_NORF_CNTRL);
- msr.lo |= (1 << i);
- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
- msr.hi, msr.lo);
- wrmsr(MDD_NORF_CNTRL, msr);
-
- /* update the number enabled */
- numEnabled++;
- }
- }
-
- printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n");
-
-}
-
-/* ***************************************************************************/
-/* **/
-/* * enable_ide_nand_flash_header */
-/* Run after VSA init to enable the flash PCI device header */
-/* **/
-/* ***************************************************************************/
-static void enable_ide_nand_flash_header(void)
-{
- /* Tell VSA to use FLASH PCI header. Not IDE header. */
- outl(0x80007A40, 0xCF8);
- outl(0xDEADBEEF, 0xCFC);
-}
-
-#define RTC_CENTURY 0x32
-#define RTC_DOMA 0x3D
-#define RTC_MONA 0x3E
-
-static void lpc_init(struct southbridge_amd_cs5536_config *sb)
-{
- msr_t msr;
-
- if (sb->lpc_serirq_enable) {
- msr.lo = sb->lpc_serirq_enable;
- msr.hi = 0;
- wrmsr(MDD_IRQM_LPC, msr);
- if (sb->lpc_serirq_polarity) {
- msr.lo = sb->lpc_serirq_polarity << 16;
- msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */
- msr.hi = 0;
- wrmsr(MDD_LPC_SIRQ, msr);
- }
- }
-
- /* Allow DMA from LPC */
- msr = rdmsr(MDD_DMA_MAP);
- msr.lo = 0x7777;
- wrmsr(MDD_DMA_MAP, msr);
-
- /* enable the RTC/CMOS century byte at address 32h */
- msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
- msr.lo = RTC_CENTURY;
- wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
-
- /* enable the RTC/CMOS day of month and month alarms */
- msr = rdmsr(MDD_RTC_DOMA_IND);
- msr.lo = RTC_DOMA;
- wrmsr(MDD_RTC_DOMA_IND, msr);
-
- msr = rdmsr(MDD_RTC_MONA_IND);
- msr.lo = RTC_MONA;
- wrmsr(MDD_RTC_MONA_IND, msr);
-
- cmos_init(0);
-
- isa_dma_init();
-}
-
-
-/**
- * Depending on settings in the config struct, enable COM1 or COM2 or both.
- *
- * If the enable is NOT set, the UARTs are explicitly disabled, which is
- * required if (e.g.) there is a Super I/O attached that does COM1 or COM2.
- *
- * @param sb Southbridge config structure.
- */
-static void uarts_init(struct southbridge_amd_cs5536_config *sb)
-{
- msr_t msr;
- u16 addr = 0;
- u32 gpio_addr;
- struct device *dev;
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
- gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
- gpio_addr &= ~1; /* Clear I/O bit */
- printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
-
- /* This could be extended to support IR modes. */
-
- /* COM1 */
- if (sb->com1_enable) {
- printk(BIOS_SPEW, "uarts_init: enable COM1\n");
- /* Set the address. */
- switch (sb->com1_address) {
- case 0x3F8:
- addr = 7;
- break;
- case 0x3E8:
- addr = 6;
- break;
- case 0x2F8:
- addr = 5;
- break;
- case 0x2E8:
- addr = 4;
- break;
- }
- msr = rdmsr(MDD_LEG_IO);
- msr.lo |= addr << 16;
- wrmsr(MDD_LEG_IO, msr);
-
- /* Set the IRQ. */
- msr = rdmsr(MDD_IRQM_YHIGH);
- msr.lo |= sb->com1_irq << 24;
- wrmsr(MDD_IRQM_YHIGH, msr);
-
- /* GPIO8 - UART1_TX */
- /* Set: Output Enable (0x4) */
- outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
- /* Set: OUTAUX1 Select (0x10) */
- outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
-
- /* GPIO9 - UART1_RX */
- /* Set: Input Enable (0x20) */
- outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
- outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
-
- /* Set: GPIO 8 + 9 Pull Up (0x18) */
- outl(GPIOL_8_SET | GPIOL_9_SET,
- gpio_addr + GPIOL_PULLUP_ENABLE);
-
- /* Enable COM1.
- *
- * Bit 1 = device enable
- * Bit 4 = allow access to the upper banks
- */
- msr.lo = (1 << 4) | (1 << 1);
- msr.hi = 0;
- wrmsr(MDD_UART1_CONF, msr);
- } else {
- /* Reset and disable COM1. */
- printk(BIOS_SPEW, "uarts_init: disable COM1\n");
- msr = rdmsr(MDD_UART1_CONF);
- msr.lo = 1; /* Reset */
- wrmsr(MDD_UART1_CONF, msr);
- msr.lo = 0; /* Disabled */
- wrmsr(MDD_UART1_CONF, msr);
-
- /* Disable the IRQ. */
- msr = rdmsr(MDD_LEG_IO);
- msr.lo &= ~(0xF << 16);
- wrmsr(MDD_LEG_IO, msr);
- }
-
- /* COM2 */
- if (sb->com2_enable) {
- printk(BIOS_SPEW, "uarts_init: enable COM2\n");
- switch (sb->com2_address) {
- case 0x3F8:
- addr = 7;
- break;
- case 0x3E8:
- addr = 6;
- break;
- case 0x2F8:
- addr = 5;
- break;
- case 0x2E8:
- addr = 4;
- break;
- }
- msr = rdmsr(MDD_LEG_IO);
- msr.lo |= addr << 20;
- wrmsr(MDD_LEG_IO, msr);
- printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address);
-
- /* Set the IRQ. */
- msr = rdmsr(MDD_IRQM_YHIGH);
- msr.lo |= sb->com2_irq << 28;
- wrmsr(MDD_IRQM_YHIGH, msr);
- printk(BIOS_SPEW, "uarts_init: set COM2 irq\n");
-
- /* GPIO3 - UART2_RX */
- /* Set: Input Enable (0x20) */
- outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
- outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
-
- /* GPIO4 - UART2_TX */
- /* Set: Output Enable (0x4) */
- outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
- printk(BIOS_SPEW, "uarts_init: set output enable\n");
- /* Set: OUTAUX1 Select (0x10) */
- outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
- printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
-
- /* Set: GPIO 3 + 4 Pull Up (0x18) */
- outl(GPIOL_3_SET | GPIOL_4_SET,
- gpio_addr + GPIOL_PULLUP_ENABLE);
- printk(BIOS_SPEW, "uarts_init: set pullup COM2\n");
-
- /* Enable COM2.
- *
- * Bit 1 = device enable
- * Bit 4 = allow access to the upper banks
- */
- msr.lo = (1 << 4) | (1 << 1);
- msr.hi = 0;
- wrmsr(MDD_UART2_CONF, msr);
- printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");
- } else {
- printk(BIOS_SPEW, "uarts_init: disable COM2\n");
- /* Reset and disable COM2. */
- msr = rdmsr(MDD_UART2_CONF);
- msr.lo = 1; /* Reset */
- wrmsr(MDD_UART2_CONF, msr);
- msr.lo = 0; /* Disabled */
- wrmsr(MDD_UART2_CONF, msr);
-
- /* Disable the IRQ. */
- msr = rdmsr(MDD_LEG_IO);
- msr.lo &= ~(0xF << 20);
- wrmsr(MDD_LEG_IO, msr);
- }
-}
-
-
-#define HCCPARAMS 0x08
-#define IPREG04 0xA0
- #define USB_HCCPW_SET (1 << 1)
-#define UOCCAP 0x00
- #define APU_SET (1 << 15)
-#define UOCMUX 0x04
-#define PMUX_HOST 0x02
-#define PMUX_DEVICE 0x03
- #define PUEN_SET (1 << 2)
-#define UDCDEVCTL 0x404
- #define UDC_SD_SET (1 << 10)
-#define UOCCTL 0x0C
- #define PADEN_SET (1 << 7)
-
-static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
-{
- void *bar;
- msr_t msr;
- struct device *dev;
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
- if (dev) {
-
- /* Serial Short Detect Enable */
- msr = rdmsr(USB2_SB_GLD_MSR_CONF);
- msr.hi |= USB2_UPPER_SSDEN_SET;
- wrmsr(USB2_SB_GLD_MSR_CONF, msr);
-
- /* write to clear diag register */
- wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
-
- bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-
- /* Make HCCPARAMS writable */
- write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
-
- /* ; EECP=50h, IST=01h, ASPC=1 */
- write32(bar + HCCPARAMS, 0x00005012);
- }
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev) {
- bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-
- write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
-
- /* Host or Device? */
- if (sb->enable_USBP4_device) {
- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);
- } else {
- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);
- }
-
- /* Overcurrent configuration */
- if (sb->enable_USBP4_overcurrent) {
- write32(bar + UOCCAP, read32(bar + UOCCAP)
- | sb->enable_USBP4_overcurrent);
- }
- }
-
- /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
- * then perform the following sequence:
- *
- * - set SD bit in DEVCTRL udc register
- * - set PADEN (former OTGPADEN) bit in uoc register
- * - set APU bit in uoc register */
- if (sb->enable_USBP4_device) {
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
- if (dev) {
- bar = (void *)pci_read_config32(dev,
- PCI_BASE_ADDRESS_0);
- write32(bar + UDCDEVCTL,
- read32(bar + UDCDEVCTL) | UDC_SD_SET);
-
- }
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev) {
- bar = (void *)pci_read_config32(dev,
- PCI_BASE_ADDRESS_0);
- write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
- write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
- }
- }
-
- /* Disable virtual PCI UDC and OTG headers */
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
- if (dev) {
- pci_write_config32(dev, 0x7C, 0xDEADBEEF);
- }
-
- dev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
- if (dev) {
- pci_write_config32(dev, 0x7C, 0xDEADBEEF);
- }
-}
-
-/****************************************************************************
- *
- * ChipsetInit
- *
- * Called from northbridge init (Pre-VSA).
- *
- ****************************************************************************/
-void chipsetinit(void)
-{
- struct device *dev;
- msr_t msr;
- u32 msrnum;
- struct southbridge_amd_cs5536_config *sb;
- struct msrinit *csi;
-
- dev = dev_find_slot(0, PCI_DEVFN(0xf, 0));
-
- if (!dev) {
- printk(BIOS_ERR, "CS5536 not found.\n");
- return;
- }
-
- sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
-
- if (!sb) {
- printk(BIOS_ERR, "CS5536 configuration not found.\n");
- return;
- }
-
- post_code(P80_CHIPSET_INIT);
-
- /* we hope NEVER to be in coreboot when S3 resumes
- if (! IsS3Resume()) */
- {
- struct acpiinit *aci = acpi_init_table;
- for (; aci->ioreg; aci++) {
- outl(aci->regdata, aci->ioreg);
- inl(aci->ioreg);
- }
-
- pmChipsetInit();
- }
-
- /* set hd IRQ */
- outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
-
- /* Allow IO read and writes during a ATA DMA operation. */
- /* This could be done in the HD ROM but do it here for easier debugging. */
- msrnum = ATA_SB_GLD_MSR_ERR;
- msr = rdmsr(msrnum);
- msr.lo &= ~0x100;
- wrmsr(msrnum, msr);
-
- /* Enable Post Primary IDE. */
- msrnum = GLPCI_SB_CTRL;
- msr = rdmsr(msrnum);
- msr.lo |= GLPCI_CRTL_PPIDE_SET;
- wrmsr(msrnum, msr);
-
- csi = SB_MASTER_CONF_TABLE;
- for (; csi->msrnum; csi++) {
- msr.lo = csi->msr.lo;
- msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
- }
-
- /* Flash BAR size Setup */
- printk(BIOS_INFO, "%sDoing ChipsetFlashSetup()\n",
- sb->enable_ide_nand_flash == 1 ? "" : "Not ");
- if (sb->enable_ide_nand_flash == 1)
- ChipsetFlashSetup();
-
- /* */
- /* Set up Hardware Clock Gating */
- /* */
- {
- csi = CS5536_CLOCK_GATING_TABLE;
- for (; csi->msrnum; csi++) {
- msr.lo = csi->msr.lo;
- msr.hi = csi->msr.hi;
- wrmsr(csi->msrnum, msr); // MSR - see table above
- }
- }
-}
-
-static void southbridge_init(struct device *dev)
-{
- struct southbridge_amd_cs5536_config *sb =
- (struct southbridge_amd_cs5536_config *)dev->chip_info;
- int i;
- /*
- * struct device *gpiodev;
- * unsigned short gpiobase = MDD_GPIO;
- */
-
- printk(BIOS_INFO, "cs5536: %s\n", __func__);
-
- if (!sb) {
- printk(BIOS_ERR, "CS5536 configuration not found.\n");
- return;
- }
-
- setup_i8259();
- lpc_init(sb);
- uarts_init(sb);
-
- if (sb->enable_gpio_int_route) {
- vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
- (sb->enable_gpio_int_route & 0xFFFF));
- vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
- (sb->enable_gpio_int_route >> 16));
- }
-
- printk(BIOS_DEBUG, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__,
- sb->enable_ide_nand_flash);
- if (sb->enable_ide_nand_flash == 1) {
- enable_ide_nand_flash_header();
- }
-
- enable_USB_port4(sb);
-
- /* disable unwanted virtual PCI devices */
- for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
- printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
- sb->unwanted_vpci[i]);
- outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
- outl(0xDEADBEEF, 0xCFC);
- }
-}
-
-static void cs5536_read_resources(struct device *dev)
-{
- struct resource *res;
-
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, 1);
- res->base = 0x0UL;
- res->size = 0x1000UL;
- res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void southbridge_enable(struct device *dev)
-{
- printk(BIOS_DEBUG, "cs5536: %s: dev is %p\n", __func__, dev);
-
-}
-
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x10);
-
- return do_smbus_read_byte(res->base, device, address);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- .read_byte = lsmbus_read_byte,
-};
-
-static void scan_lpc_smbus(struct device *dev)
-{
- /* FIXME. Do we have mixed LPC/SMBus device node here. */
- scan_smbus(dev);
-}
-
-static struct device_operations southbridge_ops = {
- .read_resources = cs5536_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = southbridge_init,
- .scan_bus = scan_lpc_smbus,
- .ops_smbus_bus = &lops_smbus_bus,
-};
-
-static const struct pci_driver cs5536_pci_driver __pci_driver = {
- .ops = &southbridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_CS5536_ISA
-};
-
-struct chip_operations southbridge_amd_cs5536_ops = {
- CHIP_NAME("AMD Geode CS5536 Southbridge")
- /* This is only called when this device is listed in the
- * static device tree.
- */
- .enable_dev = southbridge_enable,
-};
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
deleted file mode 100644
index 06c504a1aa..0000000000
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CS5536_H
-#define _CS5536_H
-
-#define Cx5536_ID ( 0x208F1022)
-
-/* SouthBridge Equates */
-#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
-#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
-#define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
-#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
-
-#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
-#define SMBUS_IO_BASE 0x6000
-#define GPIO_IO_BASE 0x6100
-#define MFGPT_IO_BASE 0x6200
-#define ACPI_IO_BASE 0x9C00
-#define PMS_IO_BASE 0x9D00
-
-#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
-#define CHIPSET_DEV_NUM 15
-#define IDSEL_BASE 11 /* bit 11 = device 1 */
-
-/* Cs5536 as follows. */
-/* SB_GLIU */
-/* port0 - GLIU */
-/* port1 - GLPCI */
-/* port2 - USB Controller #2 */
-/* port3 - ATA-5 Controller */
-/* port4 - MDD */
-/* port5 - AC97 */
-/* port6 - USB Controller #1 */
-/* port7 - GLCP */
-
-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
-#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
-#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
-#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
-#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
-#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
-#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
-#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
-
-/* GLIU */
-#define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00)
-#define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01)
-#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
-
-/* USB1 */
-#define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00)
-#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
-#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
-
-/* USB2 */
-#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)
-#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
-#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
-#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
-#define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05)
-#define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08)
-#define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09)
-#define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A)
-#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
-
-/* ATA */
-#define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00)
-#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
-#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
-#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
-#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
-
-/* AC97 */
-#define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00)
-#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
-#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
-
-/* GLPCI */
-#define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00)
-#define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01)
-#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
-#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
-#define GLPCI_CRTL_PPIDE_SET (1 << 17)
-
-/* GLCP */
-#define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00)
-#define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01)
-#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
-#define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10)
-
-/* MDD */
-#define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00)
-#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
-#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
-#define LBAR_EN (0x01)
-#define IO_MASK (0x1f)
-#define MEM_MASK (0x0FFFFF)
-#define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08)
-#define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09)
-#define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A)
-#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
-#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
-#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
-#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
-#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
-
-#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
-#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
-#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
-#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
-#define MDD_LEG_IO (MSR_SB_MDD + 0x14)
-#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
-#define MDD_SOFT_IRQ (MSR_SB_MDD + 0x16)
-#define MDD_SOFT_RESET (MSR_SB_MDD + 0x17)
-#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
-#define MDD_NORF_T01 (MSR_SB_MDD + 0x19)
-#define MDD_NORF_T23 (MSR_SB_MDD + 0x1A)
-#define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B)
-#define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C)
-#define MDD_AC_DMA (MSR_SB_MDD + 0x1E)
-#define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F)
-
-#define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20)
-#define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x21)
-#define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x22)
-#define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x23)
-#define MDD_IRQM_PRIM (MSR_SB_MDD + 0x24)
-#define MDD_IRQM_LPC (MSR_SB_MDD + 0x25)
-#define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x26)
-#define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x27)
-
-#define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x28)
-#define MDD_MFGPT_NR (MSR_SB_MDD + 0x29)
-#define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x2A)
-#define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x2B)
-
-#define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x30)
-#define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x31)
-#define MDD_FLOP_S372 (MSR_SB_MDD + 0x32)
-#define MDD_FLOP_S377 (MSR_SB_MDD + 0x33)
-
-#define MDD_PIC_S (MSR_SB_MDD + 0x34)
-#define MDD_PIT_S (MSR_SB_MDD + 0x36)
-#define MDD_PIT_CNTRL (MSR_SB_MDD + 0x37)
-
-#define MDD_UART1_MOD (MSR_SB_MDD + 0x38)
-#define MDD_UART1_DON (MSR_SB_MDD + 0x39)
-#define MDD_UART1_CONF (MSR_SB_MDD + 0x3A)
-#define MDD_UART2_MOD (MSR_SB_MDD + 0x3C)
-#define MDD_UART2_DON (MSR_SB_MDD + 0x3D)
-#define MDD_UART2_CONF (MSR_SB_MDD + 0x3E)
-
-#define MDD_DMA_MAP (MSR_SB_MDD + 0x40)
-#define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x41)
-#define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x42)
-#define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x43)
-#define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x44)
-#define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x45)
-#define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x46)
-#define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x47)
-#define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x48)
-#define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x49)
-
-#define MDD_LPC_EADDR (MSR_SB_MDD + 0x4C)
-#define MDD_LPC_ESTAT (MSR_SB_MDD + 0x4D)
-#define MDD_LPC_SIRQ (MSR_SB_MDD + 0x4E)
-#define MDD_LPC_RES (MSR_SB_MDD + 0x4F)
-
-#define MDD_PML_TMR (MSR_SB_MDD + 0x50)
-#define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x54)
-#define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x55)
-#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x56)
-#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x57)
-
-/* LBUS Device Equates - */
-
-/* SMBus */
-#define SMB_SDA 0x00
-#define SMB_STS 0x01
-#define SMB_STS_SLVSTP (0x01 << 7)
-#define SMB_STS_SDAST (0x01 << 6)
-#define SMB_STS_BER (0x01 << 5)
-#define SMB_STS_NEGACK (0x01 << 4)
-#define SMB_STS_STASTR (0x01 << 3)
-#define SMB_STS_NMATCH (0x01 << 2)
-#define SMB_STS_MASTER (0x01 << 1)
-#define SMB_STS_XMIT (0x01 << 0)
-
-#define SMB_CTRL_STS 0x02
-#define SMB_CSTS_TGSCL (0x01 << 5)
-#define SMB_CSTS_TSDA (0x01 << 4)
-#define SMB_CSTS_GCMTCH (0x01 << 3)
-#define SMB_CSTS_MATCH (0x01 << 2)
-#define SMB_CSTS_BB (0x01 << 1)
-#define SMB_CSTS_BUSY (0x01 << 0)
-
-#define SMB_CTRL1 0x03
-#define SMB_CTRL1_STASTRE (0x01 << 7)
-#define SMB_CTRL1_NMINTE (0x01 << 6)
-#define SMB_CTRL1_GCMEN (0x01 << 5)
-#define SMB_CTRL1_ACK (0x01 << 4)
-#define SMB_CTRL1_RSVD (0x01 << 3)
-#define SMB_CTRL1_INTEN (0x01 << 2)
-#define SMB_CTRL1_STOP (0x01 << 1)
-#define SMB_CTRL1_START (0x01 << 0)
-
-#define SMB_ADD 0x04
-#define SMB_ADD_SAEN (0x01 << 7)
-
-#define SMB_CTRL2 0x05
-#define SMB_CTRL2_ENABLE (0x01 << 0)
-
-#define SMB_CTRL3 0x06
-
-/* GPIO */
-#define GPIOL_0_SET (1 << 0)
-#define GPIOL_1_SET (1 << 1)
-#define GPIOL_2_SET (1 << 2)
-#define GPIOL_3_SET (1 << 3)
-#define GPIOL_4_SET (1 << 4)
-#define GPIOL_5_SET (1 << 5)
-#define GPIOL_6_SET (1 << 6)
-#define GPIOL_7_SET (1 << 7)
-#define GPIOL_8_SET (1 << 8)
-#define GPIOL_9_SET (1 << 9)
-#define GPIOL_10_SET (1 << 10)
-#define GPIOL_11_SET (1 << 11)
-#define GPIOL_12_SET (1 << 12)
-#define GPIOL_13_SET (1 << 13)
-#define GPIOL_14_SET (1 << 14)
-#define GPIOL_15_SET (1 << 15)
-
-#define GPIOL_0_CLEAR (1 << 16)
-#define GPIOL_1_CLEAR (1 << 17)
-#define GPIOL_2_CLEAR (1 << 18)
-#define GPIOL_3_CLEAR (1 << 19)
-#define GPIOL_4_CLEAR (1 << 20)
-#define GPIOL_5_CLEAR (1 << 21)
-#define GPIOL_6_CLEAR (1 << 22)
-#define GPIOL_7_CLEAR (1 << 23)
-#define GPIOL_8_CLEAR (1 << 24)
-#define GPIOL_9_CLEAR (1 << 25)
-#define GPIOL_10_CLEAR (1 << 26)
-#define GPIOL_11_CLEAR (1 << 27)
-#define GPIOL_12_CLEAR (1 << 28)
-#define GPIOL_13_CLEAR (1 << 29)
-#define GPIOL_14_CLEAR (1 << 30)
-#define GPIOL_15_CLEAR (1 << 31)
-
-#define GPIOH_16_SET (1 << 0)
-#define GPIOH_17_SET (1 << 1)
-#define GPIOH_18_SET (1 << 2)
-#define GPIOH_19_SET (1 << 3)
-#define GPIOH_20_SET (1 << 4)
-#define GPIOH_21_SET (1 << 5)
-#define GPIOH_22_SET (1 << 6)
-#define GPIOH_23_SET (1 << 7)
-#define GPIOH_24_SET (1 << 8)
-#define GPIOH_25_SET (1 << 9)
-#define GPIOH_26_SET (1 << 10)
-#define GPIOH_27_SET (1 << 11)
-#define GPIOH_28_SET (1 << 12)
-#define GPIOH_29_SET (1 << 13)
-#define GPIOH_30_SET (1 << 14)
-#define GPIOH_31_SET (1 << 15)
-
-#define GPIOH_16_CLEAR (1 << 16)
-#define GPIOH_17_CLEAR (1 << 17)
-#define GPIOH_18_CLEAR (1 << 18)
-#define GPIOH_19_CLEAR (1 << 19)
-#define GPIOH_20_CLEAR (1 << 20)
-#define GPIOH_21_CLEAR (1 << 21)
-#define GPIOH_22_CLEAR (1 << 22)
-#define GPIOH_23_CLEAR (1 << 23)
-#define GPIOH_24_CLEAR (1 << 24)
-#define GPIOH_25_CLEAR (1 << 25)
-#define GPIOH_26_CLEAR (1 << 26)
-#define GPIOH_27_CLEAR (1 << 27)
-#define GPIOH_28_CLEAR (1 << 28)
-#define GPIOH_29_CLEAR (1 << 29)
-#define GPIOH_30_CLEAR (1 << 30)
-#define GPIOH_31_CLEAR (1 << 31)
-
-/* GPIO LOW Bank Bit Registers */
-#define GPIOL_OUTPUT_VALUE (0x00)
-#define GPIOL_OUTPUT_ENABLE (0x04)
-#define GPIOL_OUT_OPENDRAIN (0x08)
-#define GPIOL_OUTPUT_INVERT_ENABLE (0x0C)
-#define GPIOL_OUT_AUX1_SELECT (0x10)
-#define GPIOL_OUT_AUX2_SELECT (0x14)
-#define GPIOL_PULLUP_ENABLE (0x18)
-#define GPIOL_PULLDOWN_ENABLE (0x1C)
-#define GPIOL_INPUT_ENABLE (0x20)
-#define GPIOL_INPUT_INVERT_ENABLE (0x24)
-#define GPIOL_IN_FILTER_ENABLE (0x28)
-#define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C)
-#define GPIOL_READ_BACK (0x30)
-#define GPIOL_IN_AUX1_SELECT (0x34)
-#define GPIOL_EVENTS_ENABLE (0x38)
-#define GPIOL_LOCK_ENABLE (0x3C)
-#define GPIOL_IN_POSEDGE_ENABLE (0x40)
-#define GPIOL_IN_NEGEDGE_ENABLE (0x44)
-#define GPIOL_IN_POSEDGE_STATUS (0x48)
-#define GPIOL_IN_NEGEDGE_STATUS (0x4C)
-
-/* GPIO High Bank Bit Registers */
-#define GPIOH_OUTPUT_VALUE (0x80)
-#define GPIOH_OUTPUT_ENABLE (0x84)
-#define GPIOH_OUT_OPENDRAIN (0x88)
-#define GPIOH_OUTPUT_INVERT_ENABLE (0x8C)
-#define GPIOH_OUT_AUX1_SELECT (0x90)
-#define GPIOH_OUT_AUX2_SELECT (0x94)
-#define GPIOH_PULLUP_ENABLE (0x98)
-#define GPIOH_PULLDOWN_ENABLE (0x9C)
-#define GPIOH_INPUT_ENABLE (0xA0)
-#define GPIOH_INPUT_INVERT_ENABLE (0xA4)
-#define GPIOH_IN_FILTER_ENABLE (0xA8)
-#define GPIOH_IN_EVENTCOUNT_ENABLE (0xAC)
-#define GPIOH_READ_BACK (0xB0)
-#define GPIOH_IN_AUX1_SELECT (0xB4)
-#define GPIOH_EVENTS_ENABLE (0xB8)
-#define GPIOH_LOCK_ENABLE (0xBC)
-#define GPIOH_IN_POSEDGE_ENABLE (0xC0)
-#define GPIOH_IN_NEGEDGE_ENABLE (0xC4)
-#define GPIOH_IN_POSEDGE_STATUS (0xC8)
-#define GPIOH_IN_NEGEDGE_STATUS (0xCC)
-
-/* Input Conditioning Function Registers */
-#define GPIO_00_FILTER_AMOUNT (0x50)
-#define GPIO_00_FILTER_COUNT (0x52)
-#define GPIO_00_EVENT_COUNT (0x54)
-#define GPIO_00_EVENTCOMPARE_VALUE (0x56)
-#define GPIO_01_FILTER_AMOUNT (0x58)
-#define GPIO_01_FILTER_COUNT (0x5A)
-#define GPIO_01_EVENT_COUNT (0x5C)
-#define GPIO_01_EVENTCOMPARE_VALUE (0x5E)
-#define GPIO_02_FILTER_AMOUNT (0x60)
-#define GPIO_02_FILTER_COUNT (0x62)
-#define GPIO_02_EVENT_COUNT (0x64)
-#define GPIO_02_EVENTCOMPARE_VALUE (0x66)
-#define GPIO_03_FILTER_AMOUNT (0x68)
-#define GPIO_03_FILTER_COUNT (0x6A)
-#define GPIO_03_EVENT_COUNT (0x6C)
-#define GPIO_03_EVENTCOMPARE_VALUE (0x6E)
-#define GPIO_04_FILTER_AMOUNT (0x70)
-#define GPIO_04_FILTER_COUNT (0x72)
-#define GPIO_04_EVENT_COUNT (0x74)
-#define GPIO_04_EVENTCOMPARE_VALUE (0x76)
-#define GPIO_05_FILTER_AMOUNT (0x78)
-#define GPIO_05_FILTER_COUNT (0x7A)
-#define GPIO_05_EVENT_COUNT (0x7C)
-#define GPIO_05_EVENTCOMPARE_VALUE (0x7E)
-#define GPIO_06_FILTER_AMOUNT (0xD0)
-#define GPIO_06_FILTER_COUNT (0xD2)
-#define GPIO_06_EVENT_COUNT (0xD4)
-#define GPIO_06_EVENTCOMPARE_VALUE (0xD6)
-#define GPIO_07_FILTER_AMOUNT (0xD8)
-#define GPIO_07_FILTER_COUNT (0xDA)
-#define GPIO_07_EVENT_COUNT (0xDC)
-#define GPIO_07_EVENTCOMPARE_VALUE (0xDE)
-
-/* R/W GPIO Interrupt &PME Mapper Registers */
-#define GPIO_MAPPER_X (0xE0)
-#define GPIO_MAPPER_Y (0xE4)
-#define GPIO_MAPPER_Z (0xE8)
-#define GPIO_MAPPER_W (0xEC)
-#define GPIO_FE_SELECT_0 (0xF0)
-#define GPIO_FE_SELECT_1 (0xF1)
-#define GPIO_FE_SELECT_2 (0xF2)
-#define GPIO_FE_SELECT_3 (0xF3)
-#define GPIO_FE_SELECT_4 (0xF4)
-#define GPIO_FE_SELECT_5 (0xF5)
-#define GPIO_FE_SELECT_6 (0xF6)
-#define GPIO_FE_SELECT_7 (0xF7)
-
-/* Event Counter Decrement Registers */
-#define GPIOL_IN_EVENT_DECREMENT (0xF8)
-#define GPIOH_IN_EVENT_DECREMENT (0xFC)
-
-/* PMC register */
-#define PM_SSD (0x00)
-#define PM_SCXA (0x04)
-#define PM_SCYA (0x08)
-#define PM_SODA (0x0C)
-#define PM_SCLK (0x10)
-#define PM_SED (0x14)
-#define PM_SCXD (0x18)
-#define PM_SCYD (0x1C)
-#define PM_SIDD (0x20)
-#define PM_WKD (0x30)
-#define PM_WKXD (0x34)
-#define PM_RD (0x38)
-#define PM_WKXA (0x3C)
-#define PM_FSD (0x40)
-#define PM_TSD (0x44)
-#define PM_PSD (0x48)
-#define PM_NWKD (0x4C)
-#define PM_AWKD (0x50)
-#define PM_SSC (0x54)
-
-/* FLASH device macros */
-#define FLASH_TYPE_NONE 0 /* No flash device installed */
-#define FLASH_TYPE_NAND 1 /* NAND device */
-#define FLASH_TYPE_NOR 2 /* NOR device */
-
-#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
-#define FLASH_IF_IO 2 /* I/O interface for Flash device */
-
-/* Flash Memory Mask values */
-#define FLASH_MEM_DEFAULT 0x00000000
-#define FLASH_MEM_4K 0xFFFFF000
-#define FLASH_MEM_8K 0xFFFFE000
-#define FLASH_MEM_16K 0xFFFFC000
-#define FLASH_MEM_128K 0xFFFE0000
-#define FLASH_MEM_512K 0xFFFC0000
-#define FLASH_MEM_4M 0xFFC00000
-#define FLASH_MEM_8M 0xFF800000
-#define FLASH_MEM_16M 0xFF000000
-
-/* Flash IO Mask values */
-#define FLASH_IO_DEFAULT 0x00000000
-#define FLASH_IO_16B 0x0000FFF0
-#define FLASH_IO_32B 0x0000FFE0
-#define FLASH_IO_64B 0x0000FFC0
-#define FLASH_IO_128B 0x0000FF80
-#define FLASH_IO_256B 0x0000FF00
-
-#if !defined(__ASSEMBLER__)
-#if defined(__PRE_RAM__)
-void cs5536_setup_onchipuart(int uart);
-void cs5536_disable_internal_uart(void);
-void cs5536_early_setup(void);
-
-void cs5536_enable_smbus(void);
-int smbus_read_byte(unsigned int device, unsigned int address);
-#else
-void chipsetinit(void);
-#endif
-#endif
-
-#endif /* _CS5536_H */
diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
deleted file mode 100644
index a95a0b4521..0000000000
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
- * This file implements the initialization sequence documented in section 4.2 of
- * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide.
- */
-
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "cs5536.h"
-
-/**
- * @brief Setup PCI IDSEL for CS5536
- */
-static void cs5536_setup_extmsr(void)
-{
- msr_t msr;
-
- /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
- msr.hi = msr.lo = 0x00000000;
-#if CS5536_GLINK_PORT_NUM <= 4
- msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
-#else
- msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
-#endif
- wrmsr(GLPCI_ExtMSR, msr);
-}
-
-static void cs5536_setup_idsel(void)
-{
- /* write IDSEL to the write once register at address 0x0000 */
- outl(0x1 << (CS5536_DEV_NUM + 10), 0);
-}
-
-static void cs5536_usb_swapsif(void)
-{
- msr_t msr;
-
- msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
- //USB Serial short detect bit.
- if (msr.hi & 0x10) {
- /* We need to preserve bits 32,33,35 and not clear any BIST
- * error, but clear the SERSHRT error bit */
-
- msr.hi &= 0xFFFFFFFB;
- wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
- }
-}
-
-static void cs5536_setup_iobase(void)
-{
- msr_t msr;
- /* setup LBAR for SMBus controller */
- msr.hi = 0x0000f001;
- msr.lo = SMBUS_IO_BASE;
- wrmsr(MDD_LBAR_SMB, msr);
-
- /* setup LBAR for GPIO */
- msr.hi = 0x0000f001;
- msr.lo = GPIO_IO_BASE;
- wrmsr(MDD_LBAR_GPIO, msr);
-
- /* setup LBAR for MFGPT */
- msr.hi = 0x0000f001;
- msr.lo = MFGPT_IO_BASE;
- wrmsr(MDD_LBAR_MFGPT, msr);
-
- /* setup LBAR for ACPI */
- msr.hi = 0x0000f001;
- msr.lo = ACPI_IO_BASE;
- wrmsr(MDD_LBAR_ACPI, msr);
-
- /* setup LBAR for PM Support */
- msr.hi = 0x0000f001;
- msr.lo = PMS_IO_BASE;
- wrmsr(MDD_LBAR_PMS, msr);
-}
-
-static void cs5536_setup_power_button(void)
-{
-#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON)
- outl(0x40020000, PMS_IO_BASE + 0x40);
-#endif
-
- /* setup WORK_AUX/GPIO24, it is the external signal for 5536
- * vsb_work_aux controls all voltage rails except Vstandby & Vmem.
- * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
- * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.
- */
- outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
- outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
-
-}
-
-static void cs5536_setup_gpio(void)
-{
- uint32_t val;
-
- /* setup GPIO pins 14/15 for SDA/SCL */
- val = GPIOL_15_SET | GPIOL_14_SET;
- /* Output Enable */
- outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
- /* Output AUX1 */
- outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
- /* Input Enable */
- outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
- /* Input AUX1 */
- outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-}
-
-void cs5536_disable_internal_uart(void)
-{
- msr_t msr;
- /* The UARTs default to enabled.
- * Disable and reset them and configure them later. (SIO init)
- */
- msr = rdmsr(MDD_UART1_CONF);
- msr.lo = 1; // reset
- wrmsr(MDD_UART1_CONF, msr);
- msr.lo = 0; // disabled
- wrmsr(MDD_UART1_CONF, msr);
-
- msr = rdmsr(MDD_UART2_CONF);
- msr.lo = 1; // reset
- wrmsr(MDD_UART2_CONF, msr);
- msr.lo = 0; // disabled
- wrmsr(MDD_UART2_CONF, msr);
-}
-
-static void cs5536_setup_cis_mode(void)
-{
- msr_t msr;
-
- /* Setup CPU serial SouthBridge interface to mode C. */
- msr = rdmsr(GLPCI_SB_CTRL);
- msr.lo &= ~0x18;
- msr.lo |= 0x10;
- wrmsr(GLPCI_SB_CTRL, msr);
-}
-
-/**
- * Enable the on-chip UART.
- *
- * See page 412 of the AMD Geode CS5536 Companion Device data book.
- */
-static void cs5536_setup_onchipuart1(void)
-{
- msr_t msr;
-
- /* Setup early for polling only mode.
- * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
- * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
- * 2. Enable UART I/O space in MDD.
- * MSR 0x51400014 bit 18:16
- * 3. Enable UART controller.
- * MSR 0x5140003A bit 0, 1
- */
-
- /* GPIO8 - UART1_TX */
- /* Set: Output Enable (0x4) */
- outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
- /* Set: OUTAUX1 Select (0x10) */
- outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
-
- /* GPIO9 - UART1_RX */
- /* Set: Input Enable (0x20) */
- outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
- outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
-
- /* Set address to 0x3F8. */
- msr = rdmsr(MDD_LEG_IO);
- msr.lo |= 0x7 << 16;
- wrmsr(MDD_LEG_IO, msr);
-
- /* Bit 1 = DEVEN (device enable)
- * Bit 4 = EN_BANKS (allow access to the upper banks)
- */
- msr.lo = (1 << 4) | (1 << 1);
- msr.hi = 0;
-
- /* Enable COM1. */
- wrmsr(MDD_UART1_CONF, msr);
-}
-
-static void cs5536_setup_onchipuart2(void)
-{
- msr_t msr;
-
- /* GPIO4 - UART2_TX */
- /* Set: Output Enable (0x4) */
- outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
- /* Set: OUTAUX1 Select (0x10) */
- outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
- /* GPIO4 - UART2_RX */
- /* Set: Input Enable (0x20) */
- outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
- outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
-
- /* Set: GPIO 3 + 3 Pull Up (0x18) */
- outl(GPIOL_3_SET | GPIOL_4_SET,
- GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
-
- /* set address to 2F8 */
- msr = rdmsr(MDD_LEG_IO);
- msr.lo |= 0x5 << 20;
- wrmsr(MDD_LEG_IO, msr);
-
- /* Bit 1 = DEVEN (device enable)
- * Bit 4 = EN_BANKS (allow access to the upper banks
- */
- msr.lo = (1 << 4) | (1 << 1);
- msr.hi = 0;
-
- /* enable COM2 */
- wrmsr(MDD_UART2_CONF, msr);
-}
-
-void cs5536_setup_onchipuart(int uart)
-{
- switch (uart) {
- case 1:
- cs5536_setup_onchipuart1();
- break;
- case 2:
- cs5536_setup_onchipuart2();
- break;
- }
-}
-
-
-/* note: you can't do prints in here in most cases,
- * and we don't want to hang on serial, so they are
- * commented out
- */
-void cs5536_early_setup(void)
-{
- msr_t msr;
-
- cs5536_setup_extmsr();
- cs5536_setup_cis_mode();
-
- msr = rdmsr(GLCP_SYS_RSTPLL);
- if (msr.lo & (0x3f << 26)) {
- /* PLL is already set and we are reboot from PLL reset */
- //printk(BIOS_DEBUG, "reboot from BIOS reset\n");
- return;
- }
- //printk(BIOS_DEBUG, "Setup idsel\n");
- cs5536_setup_idsel();
- //printk(BIOS_DEBUG, "Setup iobase\n");
- cs5536_usb_swapsif();
- cs5536_setup_iobase();
- //printk(BIOS_DEBUG, "Setup gpio\n");
- cs5536_setup_gpio();
- //printk(BIOS_DEBUG, "Setup smbus\n");
- cs5536_enable_smbus();
- //printk(BIOS_DEBUG, "Setup power button\n");
- cs5536_setup_power_button();
-}
diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c
deleted file mode 100644
index a1cf50bb15..0000000000
--- a/src/southbridge/amd/cs5536/early_smbus.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include "cs5536.h"
-#include "smbus.h"
-
-/* initialization for SMBus Controller */
-void cs5536_enable_smbus(void)
-{
-
- if (IS_ENABLED(CONFIG_NO_EARLY_SMBUS))
- return;
-
- /* Set SCL freq and enable SMB controller */
- /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */
- outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
-
- /* Setup SMBus host controller address to 0xEF */
- outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD);
-
-}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/amd/cs5536/ide.c b/src/southbridge/amd/cs5536/ide.c
deleted file mode 100644
index 53723e6a5a..0000000000
--- a/src/southbridge/amd/cs5536/ide.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "cs5536.h"
-
-#define IDE_CFG 0x40
- #define CHANEN (1L << 1)
- #define PWB (1L << 14)
- #define CABLE (1L << 16)
-#define IDE_DTC 0x48
-#define IDE_CAST 0x4C
-#define IDE_ETC 0x50
-
-static void ide_init(struct device *dev)
-{
- uint32_t ide_cfg;
-
- printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);
- /* GPIO and IRQ setup are handled in the main chipset code. */
-
- // Enable the channel and Post Write Buffer
- // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
- ide_cfg = pci_read_config32(dev, IDE_CFG);
- ide_cfg |= CHANEN | PWB;
- pci_write_config32(dev, IDE_CFG, ide_cfg);
-}
-
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = 0,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE,
-};
diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c
deleted file mode 100644
index 75bb16853a..0000000000
--- a/src/southbridge/amd/cs5536/pirq.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)
-void pirq_assign_irqs(const unsigned char pIntAtoD[4])
-{
- struct device *pdev;
-
- pdev = dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
-
- if (pdev) {
- pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12
- | pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));
- }
-}
-#endif
diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c
deleted file mode 100644
index ddbcdf2683..0000000000
--- a/src/southbridge/amd/cs5536/smbus.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include "cs5536.h"
-#include "smbus.h"
-
-#define SMBUS_TIMEOUT (1000)
-
-static void smbus_delay(void)
-{
- /* inb(0x80); */
-}
-
-static int smbus_wait(unsigned smbus_io_base)
-{
- unsigned long loops = SMBUS_TIMEOUT;
- unsigned char val;
-
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0)
- break;
- if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
- /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
- return SMBUS_ERROR;
- }
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-/* generate a smbus start condition */
-int smbus_start_condition(unsigned smbus_io_base)
-{
- unsigned char val;
-
- /* issue a START condition */
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
- /* check for bus conflict */
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_BER) != 0)
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-int smbus_check_stop_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- /* check for SDA status */
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_CTRL1);
- if ((val & SMB_CTRL1_STOP) == 0) {
- break;
- }
- outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-int smbus_stop_condition(unsigned smbus_io_base)
-{
- outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_ack(unsigned smbus_io_base, int state)
-{
- unsigned char val = inb(smbus_io_base + SMB_CTRL1);
-
-/* if (state) */
- outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-/* else
- outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-*/
- return 0;
-}
-
-int smbus_send_slave_address(unsigned smbus_io_base,
- unsigned char device)
-{
- unsigned char val;
-
- /* send the slave address */
- outb(device, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
- /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
- return SMBUS_ERROR;
- }
- return smbus_wait(smbus_io_base);
-}
-
-int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
- unsigned char val;
-
- /* send the command */
- outb(command, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-static unsigned char smbus_get_result(unsigned smbus_io_base)
-{
- return inb(smbus_io_base + SMB_SDA);
-}
-
-unsigned char do_smbus_read_byte(unsigned smbus_io_base,
- unsigned char device,
- unsigned char address)
-{
- unsigned char error = 0;
-
- if ((smbus_check_stop_condition(smbus_io_base))) {
- error = 1;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 2;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
- error = 3;
- goto err;
- }
-
- smbus_ack(smbus_io_base, 1);
-
- if ((smbus_send_command(smbus_io_base, address))) {
- error = 4;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 5;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
- error = 6;
- goto err;
- }
-
- if ((smbus_stop_condition(smbus_io_base))) {
- error = 7;
- goto err;
- }
-
- return smbus_get_result(smbus_io_base);
-
-err:
- printk(BIOS_DEBUG, "SMBUS READ ERROR: %02x device: %02x\n", error, device);
- /* stop, clean up the error, and leave */
- smbus_stop_condition(smbus_io_base);
- outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
- outb(0x0, smbus_io_base + SMB_STS);
- return 0xFF;
-}
diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h
deleted file mode 100644
index 3d67acee10..0000000000
--- a/src/southbridge/amd/cs5536/smbus.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CS5536_SMBUS_H
-#define _CS5536_SMBUS_H
-
-#include <device/smbus_def.h>
-
-int smbus_start_condition(unsigned smbus_io_base);
-int smbus_stop_condition(unsigned smbus_io_base);
-int smbus_check_stop_condition(unsigned smbus_io_base);
-int smbus_send_slave_address(unsigned smbus_io_base,
- unsigned char device);
-int smbus_send_command(unsigned smbus_io_base, unsigned char command);
-
-unsigned char do_smbus_read_byte(unsigned smbus_io_base,
- unsigned char device,
- unsigned char address);
-
-#endif /* _CS5536_SMBUS_H */