diff options
34 files changed, 52 insertions, 52 deletions
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb index 50ab93c83a..0640f389ab 100644 --- a/src/mainboard/dell/s1850/Config.lb +++ b/src/mainboard/dell/s1850/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/dell/s1850/auto.c b/src/mainboard/dell/s1850/auto.c index 406181342f..78406138cb 100644 --- a/src/mainboard/dell/s1850/auto.c +++ b/src/mainboard/dell/s1850/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "s2850_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/dell/s1850/failover.c b/src/mainboard/dell/s1850/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/dell/s1850/failover.c +++ b/src/mainboard/dell/s1850/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb index c355640cc1..69795b0026 100644 --- a/src/mainboard/intel/jarrell/Config.lb +++ b/src/mainboard/intel/jarrell/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 +chip northbridge/intel/e7520 device pci_domain 0 on device pci 00.0 on end device pci 00.1 on end diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c index f102746636..d5e68e2343 100644 --- a/src/mainboard/intel/jarrell/auto.c +++ b/src/mainboard/intel/jarrell/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "power_reset_check.c" #include "jarrell_fixups.c" #include "superio/nsc/pc87427/pc87427_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #define SIO_GPIO_BASE 0x680 @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" #include "debug.c" diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/intel/jarrell/failover.c +++ b/src/mainboard/intel/jarrell/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb index 8d4ada557b..a246f16e5c 100644 --- a/src/mainboard/supermicro/x6dai_g/Config.lb +++ b/src/mainboard/supermicro/x6dai_g/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7525 # mch +chip northbridge/intel/e7525 # mch device pci_domain 0 on chip southbridge/intel/esb6300 # esb6300 register "pirq_a_d" = "0x0b0a0a05" diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c index f148a8c38b..9c5fce59a3 100644 --- a/src/mainboard/supermicro/x6dai_g/auto.c +++ b/src/mainboard/supermicro/x6dai_g/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7525/raminit.h" +#include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -19,7 +19,7 @@ #include "watchdog.c" #include "reset.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7525/memory_initialized.c" +#include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" @@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7525/raminit.c" +#include "northbridge/intel/e7525/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dai_g/failover.c b/src/mainboard/supermicro/x6dai_g/failover.c index 1a4a88ebfa..29b7eeda5f 100644 --- a/src/mainboard/supermicro/x6dai_g/failover.c +++ b/src/mainboard/supermicro/x6dai_g/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7525/memory_initialized.c" +#include "northbridge/intel/e7525/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb index 672da8233c..60be506e28 100644 --- a/src/mainboard/supermicro/x6dhe_g/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # MCH +chip northbridge/intel/e7520 # MCH chip drivers/generic/debug # DEBUGGING device pnp 00.0 on end device pnp 00.1 off end diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c index be5affc04c..fd78ab43d3 100644 --- a/src/mainboard/supermicro/x6dhe_g/auto.c +++ b/src/mainboard/supermicro/x6dhe_g/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g/failover.c b/src/mainboard/supermicro/x6dhe_g/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/supermicro/x6dhe_g/failover.c +++ b/src/mainboard/supermicro/x6dhe_g/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb index 92567883d2..37986b9605 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Config.lb +++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # MCH +chip northbridge/intel/e7520 # MCH chip drivers/generic/debug # DEBUGGING device pnp 00.0 off end device pnp 00.1 off end diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c index 854a74a132..afd389c03e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g2_fixups.c" #include "superio/nsc/pc87427/pc87427_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c index b4966a7f18..934cdb4d28 100644 --- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c +++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhe_g_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/failover.c b/src/mainboard/supermicro/x6dhe_g2/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/supermicro/x6dhe_g2/failover.c +++ b/src/mainboard/supermicro/x6dhe_g2/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb index 2fb4ac6602..3b4826bdfc 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c index 6df3e66da0..41e85991ec 100644 --- a/src/mainboard/supermicro/x6dhr_ig/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhr_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/failover.c b/src/mainboard/supermicro/x6dhr_ig/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/supermicro/x6dhr_ig/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb index bfc9c2180c..c3c6b9a8f9 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb +++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb @@ -132,7 +132,7 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc dir /pc80 config chip.h -chip northbridge/intel/E7520 # mch +chip northbridge/intel/e7520 # mch device pci_domain 0 on chip southbridge/intel/i82801er # i82801er # USB ports diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c index 1998d34ab6..70607d016b 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/auto.c +++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c @@ -11,7 +11,7 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82801er/i82801er_early_smbus.c" -#include "northbridge/intel/E7520/raminit.h" +#include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -20,7 +20,7 @@ #include "reset.c" #include "x6dhr2_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/intel/E7520/raminit.c" +#include "northbridge/intel/e7520/raminit.c" #include "sdram/generic_sdram.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/failover.c b/src/mainboard/supermicro/x6dhr_ig2/failover.c index 5029d98611..c5f3f8089d 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/failover.c +++ b/src/mainboard/supermicro/x6dhr_ig2/failover.c @@ -9,7 +9,7 @@ #include "arch/i386/lib/console.c" #include "pc80/mc146818rtc_early.c" #include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/E7520/memory_initialized.c" +#include "northbridge/intel/e7520/memory_initialized.c" static unsigned long main(unsigned long bist) { diff --git a/src/northbridge/intel/E7520/chip.h b/src/northbridge/intel/E7520/chip.h index e9ee0a2e10..b02b8b8ad7 100644 --- a/src/northbridge/intel/E7520/chip.h +++ b/src/northbridge/intel/E7520/chip.h @@ -1,7 +1,7 @@ -struct northbridge_intel_E7520_config +struct northbridge_intel_e7520_config { /* Interrupt line connect */ unsigned int intrline; }; -extern struct chip_operations northbridge_intel_E7520_ops; +extern struct chip_operations northbridge_intel_e7520_ops; diff --git a/src/northbridge/intel/E7520/northbridge.c b/src/northbridge/intel/E7520/northbridge.c index 44490861f8..160c5a7d68 100644 --- a/src/northbridge/intel/E7520/northbridge.c +++ b/src/northbridge/intel/E7520/northbridge.c @@ -264,7 +264,7 @@ static void enable_dev(device_t dev) } } -struct chip_operations northbridge_intel_E7520_ops = { +struct chip_operations northbridge_intel_e7520_ops = { CHIP_NAME("Intel E7520 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/E7520/pciexp_porta.c b/src/northbridge/intel/E7520/pciexp_porta.c index 5443d66174..a86917217a 100644 --- a/src/northbridge/intel/E7520/pciexp_porta.c +++ b/src/northbridge/intel/E7520/pciexp_porta.c @@ -8,7 +8,7 @@ #include "chip.h" #include <part/hard_reset.h> -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_porta1.c b/src/northbridge/intel/E7520/pciexp_porta1.c index b4dcb2fe15..fd32919b19 100644 --- a/src/northbridge/intel/E7520/pciexp_porta1.c +++ b/src/northbridge/intel/E7520/pciexp_porta1.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_portb.c b/src/northbridge/intel/E7520/pciexp_portb.c index 7f17925212..491a075142 100644 --- a/src/northbridge/intel/E7520/pciexp_portb.c +++ b/src/northbridge/intel/E7520/pciexp_portb.c @@ -8,7 +8,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7520/pciexp_portc.c b/src/northbridge/intel/E7520/pciexp_portc.c index c46610b069..82d876917d 100644 --- a/src/northbridge/intel/E7520/pciexp_portc.c +++ b/src/northbridge/intel/E7520/pciexp_portc.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7520_config config_t; +typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/chip.h b/src/northbridge/intel/E7525/chip.h index 19d8c4e54c..7daadefefe 100644 --- a/src/northbridge/intel/E7525/chip.h +++ b/src/northbridge/intel/E7525/chip.h @@ -1,7 +1,7 @@ -struct northbridge_intel_E7525_config +struct northbridge_intel_e7525_config { /* Interrupt line connect */ unsigned int intrline; }; -extern struct chip_operations northbridge_intel_E7525_ops; +extern struct chip_operations northbridge_intel_e7525_ops; diff --git a/src/northbridge/intel/E7525/northbridge.c b/src/northbridge/intel/E7525/northbridge.c index 71f17224df..2fa6678c0e 100644 --- a/src/northbridge/intel/E7525/northbridge.c +++ b/src/northbridge/intel/E7525/northbridge.c @@ -264,7 +264,7 @@ static void enable_dev(device_t dev) } } -struct chip_operations northbridge_intel_E7525_ops = { +struct chip_operations northbridge_intel_e7525_ops = { CHIP_NAME("Intel E7525 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/E7525/pciexp_porta.c b/src/northbridge/intel/E7525/pciexp_porta.c index 093edec38f..aea9ab0580 100644 --- a/src/northbridge/intel/E7525/pciexp_porta.c +++ b/src/northbridge/intel/E7525/pciexp_porta.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_porta1.c b/src/northbridge/intel/E7525/pciexp_porta1.c index 7118caa72f..ac3c97c016 100644 --- a/src/northbridge/intel/E7525/pciexp_porta1.c +++ b/src/northbridge/intel/E7525/pciexp_porta1.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_portb.c b/src/northbridge/intel/E7525/pciexp_portb.c index f623a54416..e207c6c696 100644 --- a/src/northbridge/intel/E7525/pciexp_portb.c +++ b/src/northbridge/intel/E7525/pciexp_portb.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { diff --git a/src/northbridge/intel/E7525/pciexp_portc.c b/src/northbridge/intel/E7525/pciexp_portc.c index 05e0b68863..f211f3a4a2 100644 --- a/src/northbridge/intel/E7525/pciexp_portc.c +++ b/src/northbridge/intel/E7525/pciexp_portc.c @@ -7,7 +7,7 @@ #include <arch/io.h> #include "chip.h" -typedef struct northbridge_intel_E7525_config config_t; +typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { |