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-rw-r--r--src/northbridge/intel/x4x/early_init.c23
1 files changed, 15 insertions, 8 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index a556adca0e..66bce7234c 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -27,6 +27,7 @@
void x4x_early_init(void)
{
+ u8 gfxsize;
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
@@ -54,14 +55,20 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
- /* Enable internal GFX */
- pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from cmos */
- u8 gfxsize;
-
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
- /* 6 for 64MB, default if not set in cmos */
- gfxsize = 6;
+ if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
+ /* Enable internal GFX */
+ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
+ /* Set preallocated IGD size from cmos */
+
+ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
+ /* 6 for 64MB, default if not set in cmos */
+ gfxsize = 6;
+ }
+ pci_write_config16(d0f0, D0F0_GGC,
+ 0x0100 | ((gfxsize + 1) << 4));
+ } else { /* Does not feature internal graphics */
+ pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
+ pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
}
pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4));
}