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-rw-r--r--util/inteltool/inteltool.c5
-rw-r--r--util/inteltool/inteltool.h5
-rw-r--r--util/inteltool/memory.c5
-rw-r--r--util/inteltool/pcie.c5
4 files changed, 16 insertions, 4 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 219d84ece6..c6e2a67aed 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -74,7 +74,10 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A, "3rd generation (Ivy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B, "3rd generation (Ivy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C, "3rd generation (Ivy Bridge family) Core Processor" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, "3rd generation (Ivy Bridge family) Core Processor" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" },
/* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 88008e4e17..a06c70d5c4 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -154,7 +154,10 @@
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
-#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A 0x0150 /* Ivy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B 0x0154 /* Ivy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */
+#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x015c /* Ivy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 18382e5416..c755de7b91 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -251,7 +251,10 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
mch_registers = sandybridge_mch_registers;
size = ARRAY_SIZE(sandybridge_mch_registers);
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index cafd34ab37..346d51aeec 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -239,7 +239,10 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
dmi_registers = sandybridge_dmi_registers;
size = ARRAY_SIZE(sandybridge_dmi_registers);
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
dmibar_phys = pci_read_long(nb, 0x68);
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */