diff options
-rw-r--r-- | src/soc/intel/alderlake/chip.h | 3 | ||||
-rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 5 | ||||
-rw-r--r-- | src/soc/intel/alderlake/include/soc/usb.h | 16 |
3 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 164d1b9e4e..f7412dc055 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -9,6 +9,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/power_limit.h> #include <intelblocks/pcie_rp.h> +#include <intelblocks/tcss.h> #include <soc/gpe.h> #include <soc/pci_devs.h> #include <soc/pmc.h> @@ -87,6 +88,8 @@ struct soc_intel_alderlake_config { uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* Program OC pins for TCSS */ + struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; /* SATA related */ uint8_t SataEnable; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 19afbc4eaa..2ab182571e 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -184,6 +184,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } + for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { + if (config->tcss_ports[i].enable) + params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; + } + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 846849aa60..e339c7261e 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -135,4 +135,20 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +struct tcss_port_config { + uint8_t enable; + uint8_t ocpin; +}; + +#define TCSS_PORT_EMPTY { \ + .enable = 0, \ + .ocpin = OC_SKIP, \ +} + +#define TCSS_PORT_DEFAULT(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ +} + + #endif |