diff options
| -rw-r--r-- | src/mainboard/google/rush/bootblock.c | 21 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/bootblock.c | 21 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/bootblock.c | 21 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/bootblock.h | 32 |
4 files changed, 78 insertions, 17 deletions
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c index 51fe9b3e99..b74baeeac7 100644 --- a/src/mainboard/google/rush/bootblock.c +++ b/src/mainboard/google/rush/bootblock.c @@ -18,11 +18,12 @@ */ #include <arch/io.h> -#include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> #include <soc/addressmap.h> +#include <soc/bootblock.h> #include <soc/clock.h> +#include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra132/clk_rst.h> #include <soc/nvidia/tegra132/gpio.h> @@ -33,6 +34,24 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static const struct pad_config uart_console_pads[] = { + /* Hard coded pad usage for UARTA. */ + PAD_CFG_SFIO(KB_ROW9, 0, UA3), + PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), + /* + * Disable UART2 pads as they are default connected to UARTA controller. + */ + PAD_CFG_UNUSED(UART2_RXD), + PAD_CFG_UNUSED(UART2_TXD), + PAD_CFG_UNUSED(UART2_RTS_N), + PAD_CFG_UNUSED(UART2_CTS_N), +}; + +void bootblock_mainboard_early_init(void) +{ + soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); +} + static void set_clock_sources(void) { /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c index 51fe9b3e99..b74baeeac7 100644 --- a/src/mainboard/google/rush_ryu/bootblock.c +++ b/src/mainboard/google/rush_ryu/bootblock.c @@ -18,11 +18,12 @@ */ #include <arch/io.h> -#include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> #include <soc/addressmap.h> +#include <soc/bootblock.h> #include <soc/clock.h> +#include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra132/clk_rst.h> #include <soc/nvidia/tegra132/gpio.h> @@ -33,6 +34,24 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static const struct pad_config uart_console_pads[] = { + /* Hard coded pad usage for UARTA. */ + PAD_CFG_SFIO(KB_ROW9, 0, UA3), + PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), + /* + * Disable UART2 pads as they are default connected to UARTA controller. + */ + PAD_CFG_UNUSED(UART2_RXD), + PAD_CFG_UNUSED(UART2_TXD), + PAD_CFG_UNUSED(UART2_RTS_N), + PAD_CFG_UNUSED(UART2_CTS_N), +}; + +void bootblock_mainboard_early_init(void) +{ + soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); +} + static void set_clock_sources(void) { /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 3c484986d3..fc4c5cd4f1 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -22,25 +22,16 @@ #include <bootblock_common.h> #include <console/console.h> #include <program_loading.h> +#include <soc/bootblock.h> #include <soc/clock.h> -#include <soc/padconfig.h> #include <soc/nvidia/tegra/apbmisc.h> -#include "pinmux.h" #include "power.h" -static const struct pad_config uart_console_pads[] = { - /* Hard coded pad usage for UARTA. */ - PAD_CFG_SFIO(KB_ROW9, 0, UA3), - PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3), - /* - * Disable UART2 pads as they are default connected to UARTA controller. - */ - PAD_CFG_UNUSED(UART2_RXD), - PAD_CFG_UNUSED(UART2_TXD), - PAD_CFG_UNUSED(UART2_RTS_N), - PAD_CFG_UNUSED(UART2_CTS_N), -}; +void __attribute__((weak)) bootblock_mainboard_early_init(void) +{ + /* Empty default implementation. */ +} void main(void) { @@ -52,7 +43,7 @@ void main(void) clock_early_uart(); - soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads)); + bootblock_mainboard_early_init(); if (CONFIG_BOOTBLOCK_CONSOLE) { console_init(); diff --git a/src/soc/nvidia/tegra132/include/soc/bootblock.h b/src/soc/nvidia/tegra132/include/soc/bootblock.h new file mode 100644 index 0000000000..e225cc850d --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/bootblock.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_BOOTBLOCK_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_BOOTBLOCK_H__ + +#include <bootblock_common.h> + +/* + * Perform any necessary mainboard-specific work early in bootblock. This is + * ran before consoles are brought up so any pad configuration could be done + * in this routine to enable console hardware. + */ +void bootblock_mainboard_early_init(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_BOOTBLOCK_H__ */ |