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-rw-r--r--src/cpu/x86/16bit/entry16.inc15
-rw-r--r--src/cpu/x86/16bit/entry16.lds1
2 files changed, 15 insertions, 1 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 1eb92c82d1..9f4c0e38da 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -45,7 +45,6 @@ _start:
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB*/
-
/* Invalidating the cache here seems to be a bad idea on
* modern processors. Don't.
* If we are hyperthreaded or we have multiple cores it is bad,
@@ -55,6 +54,13 @@ _start:
* entry16.inc.
*/
+ /* Load an IDT with NULL limit to prevent the 16bit IDT being used
+ * in protected mode before c_start.S sets up a 32bit IDT when entering
+ * ram stage.
+ */
+ movw $nullidt_offset, %bx
+ lidt %cs:(%bx)
+
/* Note: gas handles memory addresses in 16 bit code very poorly.
* In particular it doesn't appear to have a directive allowing you
* associate a section or even an absolute offset with a segment register.
@@ -118,6 +124,13 @@ gdtptr16:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
+.align 4
+.globl nullidt
+nullidt:
+ .word 0 /* limit */
+ .long 0
+ .word 0
+
.globl _estart
_estart:
.code32
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
index 0580f0e803..112d429953 100644
--- a/src/cpu/x86/16bit/entry16.lds
+++ b/src/cpu/x86/16bit/entry16.lds
@@ -1 +1,2 @@
gdtptr16_offset = gdtptr16 & 0xffff;
+ nullidt_offset = nullidt & 0xffff;