summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 4f30382d2d..9eb91bdac1 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -154,6 +154,8 @@ struct soc_intel_cannonlake_config {
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+ /* PCIe LTR(Latency Tolerance Reporting) mechanism */
+ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 3314f6d989..f95745983d 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -171,6 +171,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
+ memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
+ sizeof(config->PcieRpLtrEnable));
/* eMMC and SD */
dev = dev_find_slot(0, PCH_DEVFN_EMMC);