455 files changed, 503 insertions, 510 deletions

diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c
index 3c77b11e2a..86281e3ba4 100644
--- a/src/mainboard/advantech/pcm-5820/romstage.c
+++ b/src/mainboard/advantech/pcm-5820/romstage.c
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 8b7027189b..188ec1f8f5 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 88ecd941ef..6e3d3fcad1 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index c20c0a6f7b..4ad0aa0d3b 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -43,9 +43,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 1157b00832..92502e32a4 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 #include <spd.h>
 
@@ -69,7 +69,7 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index f60313842a..7350c440c9 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 187eb207c2..291d1f4607 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -38,9 +38,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index ade6f62d0f..ecc22c08d3 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -10,8 +10,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ee78f31c5c..10b7eccdcc 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -26,7 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 2124c284c9..ff0c1da06e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -35,7 +35,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -48,7 +48,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index ddb5076c12..8e22cdab49 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index 61a0b0e5ba..56e66e1e6c 100644
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 7b213bf1c7..4df61a2679 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -33,8 +33,8 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static int spd_read_byte(unsigned device, unsigned address)
 {
diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c
index 3d3367aa85..1adca8a7ea 100644
--- a/src/mainboard/asi/mb_5blgp/romstage.c
+++ b/src/mainboard/asi/mb_5blgp/romstage.c
@@ -27,7 +27,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 
diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c
index f79c2437b9..01b5a78326 100644
--- a/src/mainboard/asi/mb_5blmp/romstage.c
+++ b/src/mainboard/asi/mb_5blmp/romstage.c
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index fcbda3ff89..c35d22b05b 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -44,9 +44,9 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
+#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 9558d055b1..f7ee69685f 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -38,7 +38,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 1f3c088858..cbba7cf5b7 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@ void soft_reset(void)
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1f3c088858..cbba7cf5b7 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -41,8 +41,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -79,7 +79,7 @@ void soft_reset(void)
 	}
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 65fdd115aa..714b0544f7 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 3176c39866..fab6d0ca34 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -45,7 +45,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/via/k8t890/k8t890_early_car.c"
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index c18b58b87b..e4514f6569 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index c18b58b87b..e4514f6569 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c
index f5eeab3c29..c79f42d9f0 100644
--- a/src/mainboard/axus/tc320/romstage.c
+++ b/src/mainboard/axus/tc320/romstage.c
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c
index f5eeab3c29..c79f42d9f0 100644
--- a/src/mainboard/bcom/winnet100/romstage.c
+++ b/src/mainboard/bcom/winnet100/romstage.c
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 7d9a5a7d57..96df58a148 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -33,7 +33,7 @@
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index e3791a79bf..d96e7ff38f 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c
index 3927cd2f33..49060ea2ea 100644
--- a/src/mainboard/dell/s1850/romstage.c
+++ b/src/mainboard/dell/s1850/romstage.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc8374/pc8374_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 823e5effa4..12d6bb430b 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -10,7 +10,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 4429914d74..93391b45f7 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -12,8 +12,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c
index 16ea548ff5..fa6f29f576 100644
--- a/src/mainboard/eaglelion/5bcm/romstage.c
+++ b/src/mainboard/eaglelion/5bcm/romstage.c
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 490a182494..649dff6ebe 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -33,7 +33,7 @@
 
 extern unsigned char AmlCode[];
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c
index c7fe3f74f1..6831d2e706 100644
--- a/src/mainboard/getac/p470/mainboard_smi.c
+++ b/src/mainboard/getac/p470/mainboard_smi.c
@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/i82801gx.h"
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 #include "northbridge/intel/i945/udelay.c"
 #include "ec.c"
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 4b31b545af..86e3f6f24c 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -39,8 +39,8 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/sis/sis966/sis966.h"
-#include "southbridge/sis/sis966/sis966_early_smbus.c"
-#include "southbridge/sis/sis966/sis966_enable_rom.c"
+#include "southbridge/sis/sis966/early_smbus.c"
+#include "southbridge/sis/sis966/enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -52,7 +52,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/sis/sis966/sis966_early_ctrl.c"
+#include "southbridge/sis/sis966/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
@@ -86,7 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
+#include "southbridge/sis/sis966/early_setup_ss.h"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b76da5533f..55d95a571f 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -36,7 +36,7 @@
 #include <usbdebug.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
@@ -69,8 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 8daa2b1dcd..10d369287d 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -43,8 +43,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -64,7 +64,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index bbf1f58a70..7245eb9d91 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index a920cc840f..59dfc0351d 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -20,7 +20,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index eeac3e5b6a..2687aea672 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -40,7 +40,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -53,7 +53,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index ae9be8aeea..902be52dd3 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -39,7 +39,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c
index f8009c3757..0089e2150a 100644
--- a/src/mainboard/ibase/mb899/acpi_tables.c
+++ b/src/mainboard/ibase/mb899/acpi_tables.c
@@ -35,7 +35,7 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));
diff --git a/src/mainboard/ibase/mb899/mainboard_smi.c b/src/mainboard/ibase/mb899/mainboard_smi.c
index 8516bdeba6..3e3bee7e6d 100644
--- a/src/mainboard/ibase/mb899/mainboard_smi.c
+++ b/src/mainboard/ibase/mb899/mainboard_smi.c
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index 83f04c06b4..590565e4cf 100644
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 68e6291878..5adc8fb22b 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -10,7 +10,7 @@
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c
index a5019ce095..54ada03b5d 100644
--- a/src/mainboard/iei/juki-511p/romstage.c
+++ b/src/mainboard/iei/juki-511p/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "northbridge/amd/gx1/raminit.c"
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 86da8f6c87..0473d5f92b 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -47,8 +47,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -70,7 +70,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c
index 1d99197293..50b114e185 100644
--- a/src/mainboard/iei/nova4899r/romstage.c
+++ b/src/mainboard/iei/nova4899r/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 #include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 0c06fd2432..d011ed13dc 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -31,8 +31,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index 9fc2adbc7c..1e8ea292fc 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -66,7 +66,7 @@ typedef struct acpi_oemb {
 } __attribute__((packed)) acpi_oemb_t;
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 #if OLD_ACPI
 static void acpi_create_oemb(acpi_oemb_t *oemb)
diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c
index 8dff64e8fa..dbd1a81a64 100644
--- a/src/mainboard/intel/d945gclf/mainboard_smi.c
+++ b/src/mainboard/intel/d945gclf/mainboard_smi.c
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 8f8cd0f00f..e91fcd052d 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -31,8 +31,8 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/acpi.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index e3ab67940e..8ce1cd24da 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 856c69950d..e397eaefb7 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -27,8 +27,8 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index d6ee7c582f..6d29c57c75 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -28,8 +28,8 @@
 #include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "southbridge/intel/i3100/i3100_early_smbus.c"
-#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "southbridge/intel/i3100/early_smbus.c"
+#include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
 #include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index e6fb83f4a6..d594091752 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -8,7 +8,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
+#include "southbridge/intel/i82801cx/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/debug.c"
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 582fed392b..3a420c03ff 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 01e747eb94..8181abc200 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 7b2db33d38..0701234ee5 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -13,7 +13,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -24,7 +24,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index b0c14968b9..401fe67617 100644
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -31,7 +31,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 #include <lib.h>
 #include <spd.h>
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 4711aecfdd..b5b9ab3d4b 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -48,8 +48,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
 #if CONFIG_TTYS0_BASE == 0x2f8
@@ -75,7 +75,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index f8009c3757..0089e2150a 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -35,7 +35,7 @@ extern const unsigned char AmlCode[];
 unsigned long acpi_create_slic(unsigned long current);
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));
diff --git a/src/mainboard/kontron/986lcd-m/mainboard_smi.c b/src/mainboard/kontron/986lcd-m/mainboard_smi.c
index 8516bdeba6..3e3bee7e6d 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard_smi.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard_smi.c
@@ -21,7 +21,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 16c8b0b455..6c9e3ef345 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -45,8 +45,8 @@
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 5406b7d05f..ba7a2959de 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -33,7 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 0abdde4372..f96b93bb60 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -11,8 +11,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
-#include "southbridge/amd/cs5535/cs5535_early_setup.c"
+#include "southbridge/amd/cs5535/early_smbus.c"
+#include "southbridge/amd/cs5535/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 35f8fe5c31..1a56251557 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum. */
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index afe5bd7c09..aa89cac523 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 32f3b3e304..331ba5dfe5 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -34,8 +34,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 #define ManualConf 1		/* No automatic strapped PLL config */
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 5f940e5661..462a2b5b9a 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -34,8 +34,8 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index c804b6c9fe..53d7e509f5 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -36,7 +36,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -60,8 +60,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 4ec8cec9f2..e5b4b47fbe 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -36,7 +36,7 @@
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -50,7 +50,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
@@ -78,8 +78,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index a27fec0118..ee2847b17e 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -34,7 +34,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -46,7 +46,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+#include "southbridge/broadcom/bcm5785/early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index f5e9f265f3..599b8b60ca 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -32,7 +32,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include <spd.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <device/pci_ids.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
 
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
@@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 5c0c9ae31a..9150a832d3 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -72,8 +72,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index b6ceed1037..1a6cdbc0a5 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -17,7 +17,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -28,7 +28,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 8e4067f1f0..508ea83bd0 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -37,7 +37,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
@@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index ed9324ea44..609baf6e5f 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -38,7 +38,7 @@
 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index ec77537113..1a0acf2386 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -38,7 +38,7 @@
 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
 static void cs5536_enable_smbus(void) { }
 
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 /* The part is a Hynix hy5du121622ctp-d43.
  *
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 1fb1440a1b..6df8d41f38 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -32,12 +32,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index 2dd7c5ccf0..d9275b5ac0 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -91,7 +91,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 }
 #endif
 
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
 	memset((void *)gnvs, 0, sizeof(*gnvs));
diff --git a/src/mainboard/roda/rk886ex/mainboard_smi.c b/src/mainboard/roda/rk886ex/mainboard_smi.c
index 17783fe6e6..6736ace09a 100644
--- a/src/mainboard/roda/rk886ex/mainboard_smi.c
+++ b/src/mainboard/roda/rk886ex/mainboard_smi.c
@@ -23,7 +23,7 @@
 #include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include "southbridge/intel/i82801gx/i82801gx_nvs.h"
+#include "southbridge/intel/i82801gx/nvs.h"
 
 /* The southbridge SMI handler checks whether gnvs has a
  * valid pointer before calling the trap handler
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index ceac91ddfb..21d50469d7 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index ff7b24f40e..8ba4f2604c 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -33,7 +33,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -45,7 +45,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -127,8 +127,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index e7875956b2..65517ec31e 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -36,7 +36,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -68,8 +68,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 966ae3b694..90f0d93a37 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -64,8 +64,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index d60350935d..e6591d90d6 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -34,7 +34,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,7 +47,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
@@ -70,8 +70,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 09e52873c1..8815d19f98 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index b6ae4df626..74e1bd8593 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -8,7 +8,7 @@
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
+#include "southbridge/intel/esb6300/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index bf2762e8c0..72e3b9da5b 100644
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 102ef8ead6..f37d565b20 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 44b9ae092d..166d56c0f1 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -6,7 +6,7 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index f9f1e70ce1..7f72a32a89 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 276ca08682..490eaa5481 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -44,8 +44,8 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/rs690/rs690_early_setup.c"
-#include "southbridge/amd/sb600/sb600_early_setup.c"
+#include "southbridge/amd/rs690/early_setup.c"
+#include "southbridge/amd/sb600/early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c
index f5eeab3c29..c79f42d9f0 100644
--- a/src/mainboard/televideo/tc7020/romstage.c
+++ b/src/mainboard/televideo/tc7020/romstage.c
@@ -28,7 +28,7 @@
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "southbridge/amd/cs5530/enable_rom.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index c9ec8a80b2..047d704073 100644
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -33,12 +33,12 @@
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
-#include "southbridge/intel/i82801dx/i82801dx_reset.c"
+#include "southbridge/intel/i82801dx/reset.c"
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
-#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#include "southbridge/intel/i82801dx/early_smbus.c"
+#include "southbridge/intel/i82801dx/tco_timer.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 3e4ffb5c4c..07962d33fd 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -32,8 +32,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index c7c5eb036a..eaddf9a290 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -9,7 +9,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
+#include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "northbridge/intel/e7501/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index b7f0716796..a45d6dfa1c 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index db54927e9b..7681e88f31 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 2ab663b0d1..a1312659f8 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index 6645c9de24..22f24bbd18 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 2ab663b0d1..a1312659f8 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -12,7 +12,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -23,7 +23,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index a4b7d076d1..963ba1b7ef 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 39bdc65e7e..c059592e8d 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -39,8 +39,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
-#include "southbridge/nvidia/ck804/ck804_early_setup.c"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 2ab6d32090..820e05ff96 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -38,7 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 7a6fcbc3a7..db534f021f 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -11,7 +11,7 @@
 #include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
+#include "southbridge/nvidia/ck804/early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+#include "southbridge/nvidia/ck804/early_setup_ss.h"
 
 //set GPIO to input mode
 #define CK804_MB_SETUP \
@@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
-#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
+#include "southbridge/nvidia/ck804/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 0dd7297ea2..aa6107637d 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -37,7 +37,7 @@
 #include <spd.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -49,7 +49,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index d5d2c4129b..c9c8561030 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -35,7 +35,7 @@
 #include <lib.h>
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -73,8 +73,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index cfa061313f..6e480699db 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -11,7 +11,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -22,7 +22,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index d83c21a893..c21388f545 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -10,7 +10,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "southbridge/amd/amd8111/early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -21,7 +21,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+#include "southbridge/amd/amd8111/early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 20b4c05675..66b607b908 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -32,8 +32,8 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 #include <spd.h>
 
 static inline int spd_read_byte(unsigned device, unsigned address)
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 2d887b3f92..b22719cedc 100644
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -14,8 +14,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8235/vt8235_early_smbus.c"
-#include "southbridge/via/vt8235/vt8235_early_serial.c"
+#include "southbridge/via/vt8235/early_smbus.c"
+#include "southbridge/via/vt8235/early_serial.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 22e12cb678..aa35858224 100644
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -33,7 +33,7 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #include <spd.h>
 
diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index 870c4e7630..9d9a3f9a9a 100644
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -12,9 +12,9 @@
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "lib/debug.c"
-#include "southbridge/via/vt8231/vt8231_early_smbus.c"
-#include "southbridge/via/vt8231/vt8231_early_serial.c"
-#include "southbridge/via/vt8231/vt8231_enable_rom.c"
+#include "southbridge/via/vt8231/early_smbus.c"
+#include "southbridge/via/vt8231/early_serial.c"
+#include "southbridge/via/vt8231/enable_rom.c"
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 2b653f79d2..0fded96d0c 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -32,7 +32,7 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include <spd.h>
 
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index cd615efa4b..318b560fba 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -33,8 +33,8 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index f876124336..6865877531 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -31,8 +31,8 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc
index b58fbaac88..cdad4a62ab 100644
--- a/src/southbridge/amd/amd8111/Makefile.inc
+++ b/src/southbridge/amd/amd8111/Makefile.inc
@@ -1,11 +1,11 @@
 driver-y += amd8111.c
-driver-y += amd8111_usb.c
-driver-y += amd8111_lpc.c
-driver-y += amd8111_ide.c
-driver-y += amd8111_acpi.c
-driver-y += amd8111_usb2.c
-driver-y += amd8111_ac97.c
-driver-y += amd8111_nic.c
-driver-y += amd8111_pci.c
-driver-y += amd8111_smbus.c
-ramstage-y += amd8111_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += acpi.c
+driver-y += usb2.c
+driver-y += ac97.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += smbus.c
+ramstage-y += reset.c
diff --git a/src/southbridge/amd/amd8111/amd8111_ac97.c b/src/southbridge/amd/amd8111/ac97.c
index f49c9bfd5f..f49c9bfd5f 100644
--- a/src/southbridge/amd/amd8111/amd8111_ac97.c
+++ b/src/southbridge/amd/amd8111/ac97.c
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 2ad54b78f6..2ad54b78f6 100644
--- a/src/southbridge/amd/amd8111/amd8111_acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 695f49898b..a11d1d30f4 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -1,4 +1,4 @@
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "southbridge/amd/amd8111/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ece99ed40a..ece99ed40a 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
index e6d70847ea..e6d70847ea 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c
+++ b/src/southbridge/amd/amd8111/early_smbus.c
diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/enable_rom.c
index 3e73112b47..3e73112b47 100644
--- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c
+++ b/src/southbridge/amd/amd8111/enable_rom.c
diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/ide.c
index 3299875187..3299875187 100644
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/lpc.c
index e9bd5fc42b..e9bd5fc42b 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/nic.c
index 4ab7212eda..4ab7212eda 100644
--- a/src/southbridge/amd/amd8111/amd8111_nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
diff --git a/src/southbridge/amd/amd8111/amd8111_pci.c b/src/southbridge/amd/amd8111/pci.c
index 9e7724980f..9e7724980f 100644
--- a/src/southbridge/amd/amd8111/amd8111_pci.c
+++ b/src/southbridge/amd/amd8111/pci.c
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/reset.c
index c96e898aea..c96e898aea 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.c b/src/southbridge/amd/amd8111/smbus.c
index 0a0c58dce3..0a0c58dce3 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.c
+++ b/src/southbridge/amd/amd8111/smbus.c
diff --git a/src/southbridge/amd/amd8111/amd8111_usb.c b/src/southbridge/amd/amd8111/usb.c
index 13dccf435b..13dccf435b 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb.c
+++ b/src/southbridge/amd/amd8111/usb.c
diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/usb2.c
index 89115c3bbe..89115c3bbe 100644
--- a/src/southbridge/amd/amd8111/amd8111_usb2.c
+++ b/src/southbridge/amd/amd8111/usb2.c
diff --git a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c b/src/southbridge/amd/amd8131-disable/bridge.c
index e90f497d95..e90f497d95 100644
--- a/src/southbridge/amd/amd8131-disable/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131-disable/bridge.c
diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc
index 395f0e0e0c..d5b3a5f88e 100644
--- a/src/southbridge/amd/amd8131/Makefile.inc
+++ b/src/southbridge/amd/amd8131/Makefile.inc
@@ -1 +1 @@
-driver-y += amd8131_bridge.c
+driver-y += bridge.c
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/bridge.c
index d258450a06..d258450a06 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/bridge.c
diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc
index f1e844af10..d5b3a5f88e 100644
--- a/src/southbridge/amd/amd8132/Makefile.inc
+++ b/src/southbridge/amd/amd8132/Makefile.inc
@@ -1 +1 @@
-driver-y += amd8132_bridge.c
+driver-y += bridge.c
diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 192137a18e..192137a18e 100644
--- a/src/southbridge/amd/amd8132/amd8132_bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc
index d9b46989c6..b25139108a 100644
--- a/src/southbridge/amd/amd8151/Makefile.inc
+++ b/src/southbridge/amd/amd8151/Makefile.inc
@@ -1 +1 @@
-driver-y += amd8151_agp3.c
+driver-y += agp3.c
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/agp3.c
index a2df7035c9..a2df7035c9 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/agp3.c
diff --git a/src/southbridge/amd/cs5530/Makefile.inc b/src/southbridge/amd/cs5530/Makefile.inc
index f51369fac1..4bde476743 100644
--- a/src/southbridge/amd/cs5530/Makefile.inc
+++ b/src/southbridge/amd/cs5530/Makefile.inc
@@ -19,7 +19,7 @@
 ##
 
 driver-y += cs5530.c
-driver-y += cs5530_isa.c
-driver-y += cs5530_ide.c
-driver-y += cs5530_vga.c
-driver-y += cs5530_pirq.c
+driver-y += isa.c
+driver-y += ide.c
+driver-y += vga.c
+driver-y += pirq.c
diff --git a/src/southbridge/amd/cs5530/cs5530_enable_rom.c b/src/southbridge/amd/cs5530/enable_rom.c
index 09ec3ed791..09ec3ed791 100644
--- a/src/southbridge/amd/cs5530/cs5530_enable_rom.c
+++ b/src/southbridge/amd/cs5530/enable_rom.c
diff --git a/src/southbridge/amd/cs5530/cs5530_ide.c b/src/southbridge/amd/cs5530/ide.c
index a1fa2dc2c3..a1fa2dc2c3 100644
--- a/src/southbridge/amd/cs5530/cs5530_ide.c
+++ b/src/southbridge/amd/cs5530/ide.c
diff --git a/src/southbridge/amd/cs5530/cs5530_isa.c b/src/southbridge/amd/cs5530/isa.c
index ff1617ddc3..ff1617ddc3 100644
--- a/src/southbridge/amd/cs5530/cs5530_isa.c
+++ b/src/southbridge/amd/cs5530/isa.c
diff --git a/src/southbridge/amd/cs5530/cs5530_pirq.c b/src/southbridge/amd/cs5530/pirq.c
index 693f7c4721..693f7c4721 100644
--- a/src/southbridge/amd/cs5530/cs5530_pirq.c
+++ b/src/southbridge/amd/cs5530/pirq.c
diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/vga.c
index 4a26251084..4a26251084 100644
--- a/src/southbridge/amd/cs5530/cs5530_vga.c
+++ b/src/southbridge/amd/cs5530/vga.c
diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc
index ba092f125b..5fecea8e7e 100644
--- a/src/southbridge/amd/cs5535/Makefile.inc
+++ b/src/southbridge/amd/cs5535/Makefile.inc
@@ -1,4 +1,4 @@
 driver-y += cs5535.c
-#driver-y += cs5535_pci.c
-#driver-y += cs5535_ide.c
+#driver-y += pci.c
+#driver-y += ide.c
 ramstage-y += chipsetinit.c
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1a612cc55f..1a612cc55f 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/early_smbus.c
index 0aab46f6a3..25b6951daa 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/early_smbus.c
@@ -1,4 +1,4 @@
-#include "cs5535_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x6000
 
diff --git a/src/southbridge/amd/cs5535/cs5535_ide.c b/src/southbridge/amd/cs5535/ide.c
index b997ca2463..b997ca2463 100644
--- a/src/southbridge/amd/cs5535/cs5535_ide.c
+++ b/src/southbridge/amd/cs5535/ide.c
diff --git a/src/southbridge/amd/cs5535/cs5535_smbus.h b/src/southbridge/amd/cs5535/smbus.h
index db35f6ee7b..db35f6ee7b 100644
--- a/src/southbridge/amd/cs5535/cs5535_smbus.h
+++ b/src/southbridge/amd/cs5535/smbus.h
diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc
index a1a36833fc..75c6e5c930 100644
--- a/src/southbridge/amd/cs5536/Makefile.inc
+++ b/src/southbridge/amd/cs5536/Makefile.inc
@@ -18,5 +18,5 @@
 ##
 
 driver-y += cs5536.c
-driver-y += cs5536_ide.c
-driver-y += cs5536_pirq.c
+driver-y += ide.c
+driver-y += pirq.c
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index 047c1a21a0..047c1a21a0 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c
index 5cb815d250..5cb815d250 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c
+++ b/src/southbridge/amd/cs5536/early_smbus.c
diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/ide.c
index c4cc652e93..c4cc652e93 100644
--- a/src/southbridge/amd/cs5536/cs5536_ide.c
+++ b/src/southbridge/amd/cs5536/ide.c
diff --git a/src/southbridge/amd/cs5536/cs5536_pirq.c b/src/southbridge/amd/cs5536/pirq.c
index b2ae1fe3af..b2ae1fe3af 100644
--- a/src/southbridge/amd/cs5536/cs5536_pirq.c
+++ b/src/southbridge/amd/cs5536/pirq.c
diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/smbus2.h
index dea08a437c..dea08a437c 100644
--- a/src/southbridge/amd/cs5536/cs5536_smbus2.h
+++ b/src/southbridge/amd/cs5536/smbus2.h
diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc
index c728be56a4..5849340ce0 100644
--- a/src/southbridge/amd/rs690/Makefile.inc
+++ b/src/southbridge/amd/rs690/Makefile.inc
@@ -1,5 +1,5 @@
 driver-y += rs690.c
-driver-y += rs690_cmn.c
-driver-y += rs690_pcie.c
-driver-y += rs690_ht.c
-driver-y += rs690_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/cmn.c
index 5e06d4f9d8..5e06d4f9d8 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/cmn.c
diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/early_setup.c
index f29d136791..f29d136791 100644
--- a/src/southbridge/amd/rs690/rs690_early_setup.c
+++ b/src/southbridge/amd/rs690/early_setup.c
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/gfx.c
index c55f2bc3d3..c55f2bc3d3 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/ht.c
index 26824b5322..26824b5322 100644
--- a/src/southbridge/amd/rs690/rs690_ht.c
+++ b/src/southbridge/amd/rs690/ht.c
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/pcie.c
index f02e0d73b4..f02e0d73b4 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc
index f76e517c82..db425702d6 100644
--- a/src/southbridge/amd/rs780/Makefile.inc
+++ b/src/southbridge/amd/rs780/Makefile.inc
@@ -1,5 +1,5 @@
 driver-y += rs780.c
-driver-y += rs780_cmn.c
-driver-y += rs780_pcie.c
-driver-y += rs780_ht.c
-driver-y += rs780_gfx.c
+driver-y += cmn.c
+driver-y += pcie.c
+driver-y += ht.c
+driver-y += gfx.c
diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/cmn.c
index 4bd870bbf2..4bd870bbf2 100644
--- a/src/southbridge/amd/rs780/rs780_cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 57a7b62427..a93ba83172 100644
--- a/src/southbridge/amd/rs780/rs780_early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -21,7 +21,7 @@
 #define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
 #endif
 
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBHTIU_INDEX		0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
 #define NBMISC_INDEX		0x60
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/gfx.c
index 1763c36047..1763c36047 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
diff --git a/src/southbridge/amd/rs780/rs780_ht.c b/src/southbridge/amd/rs780/ht.c
index 03d4f84645..03d4f84645 100644
--- a/src/southbridge/amd/rs780/rs780_ht.c
+++ b/src/southbridge/amd/rs780/ht.c
diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/pcie.c
index 9cbd832661..9cbd832661 100644
--- a/src/southbridge/amd/rs780/rs780_pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
diff --git a/src/southbridge/amd/rs780/rs780_rev.h b/src/southbridge/amd/rs780/rev.h
index 94ab752f9f..94ab752f9f 100644
--- a/src/southbridge/amd/rs780/rs780_rev.h
+++ b/src/southbridge/amd/rs780/rev.h
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index c91a4b3022..aba3e6929b 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -23,7 +23,7 @@
 #include <stdint.h>
 #include <device/pci_ids.h>
 #include "chip.h"
-#include "rs780_rev.h"
+#include "rev.h"
 
 #define NBMISC_INDEX 	0x60
 #define NBHTIU_INDEX 	0x94
diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc
index 854539b9b3..b5903616c0 100644
--- a/src/southbridge/amd/sb600/Makefile.inc
+++ b/src/southbridge/amd/sb600/Makefile.inc
@@ -1,11 +1,11 @@
 driver-y += sb600.c
-driver-y += sb600_usb.c
-driver-y += sb600_lpc.c
-driver-y += sb600_sm.c
-driver-y += sb600_ide.c
-driver-y += sb600_sata.c
-driver-y += sb600_hda.c
-driver-y += sb600_ac97.c
-driver-y += sb600_pci.c
-ramstage-y += sb600_reset.c
-romstage-y += sb600_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += ac97.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c
diff --git a/src/southbridge/amd/sb600/sb600_ac97.c b/src/southbridge/amd/sb600/ac97.c
index e9eae65fb6..e9eae65fb6 100644
--- a/src/southbridge/amd/sb600/sb600_ac97.c
+++ b/src/southbridge/amd/sb600/ac97.c
diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c
index dd943d79b7..a5eb2f2fac 100644
--- a/src/southbridge/amd/sb600/bootblock.c
+++ b/src/southbridge/amd/sb600/bootblock.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/amd/sb600/sb600_enable_rom.c"
+#include "southbridge/amd/sb600/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index 3ed8dd85de..45b29c1d58 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -20,7 +20,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */
diff --git a/src/southbridge/amd/sb600/sb600_enable_rom.c b/src/southbridge/amd/sb600/enable_rom.c
index b2668420ce..b2668420ce 100644
--- a/src/southbridge/amd/sb600/sb600_enable_rom.c
+++ b/src/southbridge/amd/sb600/enable_rom.c
diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index b4d97b0da2..b4d97b0da2 100644
--- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/hda.c
index 84df3f169f..84df3f169f 100644
--- a/src/southbridge/amd/sb600/sb600_hda.c
+++ b/src/southbridge/amd/sb600/hda.c
diff --git a/src/southbridge/amd/sb600/sb600_ide.c b/src/southbridge/amd/sb600/ide.c
index e38e83fdd7..e38e83fdd7 100644
--- a/src/southbridge/amd/sb600/sb600_ide.c
+++ b/src/southbridge/amd/sb600/ide.c
diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/lpc.c
index 6a17f72318..6a17f72318 100644
--- a/src/southbridge/amd/sb600/sb600_lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
diff --git a/src/southbridge/amd/sb600/sb600_pci.c b/src/southbridge/amd/sb600/pci.c
index 66ca29bd78..66ca29bd78 100644
--- a/src/southbridge/amd/sb600/sb600_pci.c
+++ b/src/southbridge/amd/sb600/pci.c
diff --git a/src/southbridge/amd/sb600/sb600_reset.c b/src/southbridge/amd/sb600/reset.c
index af80576204..af80576204 100644
--- a/src/southbridge/amd/sb600/sb600_reset.c
+++ b/src/southbridge/amd/sb600/reset.c
diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sata.c
index 055e7daa85..055e7daa85 100644
--- a/src/southbridge/amd/sb600/sb600_sata.c
+++ b/src/southbridge/amd/sb600/sata.c
diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sm.c
index b074edb89e..1a0d6acdd8 100644
--- a/src/southbridge/amd/sb600/sb600_sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb600.h"
-#include "sb600_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 
diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/smbus.c
index 0cc0e62c04..cdd1930b5f 100644
--- a/src/southbridge/amd/sb600/sb600_smbus.c
+++ b/src/southbridge/amd/sb600/smbus.c
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "sb600_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {
diff --git a/src/southbridge/amd/sb600/sb600_smbus.h b/src/southbridge/amd/sb600/smbus.h
index 684d0e62c4..684d0e62c4 100644
--- a/src/southbridge/amd/sb600/sb600_smbus.h
+++ b/src/southbridge/amd/sb600/smbus.h
diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/usb.c
index 7539f083c6..7539f083c6 100644
--- a/src/southbridge/amd/sb600/sb600_usb.c
+++ b/src/southbridge/amd/sb600/usb.c
diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
index dd97df31e6..8d1c20813a 100644
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -1,10 +1,10 @@
 driver-y += sb700.c
-driver-y += sb700_usb.c
-driver-y += sb700_lpc.c
-driver-y += sb700_sm.c
-driver-y += sb700_ide.c
-driver-y += sb700_sata.c
-driver-y += sb700_hda.c
-driver-y += sb700_pci.c
-ramstage-y += sb700_reset.c
-romstage-y += sb700_enable_usbdebug.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sm.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += hda.c
+driver-y += pci.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c
diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 9f8d44f6c7..81ffc1c7d5 100644
--- a/src/southbridge/amd/sb700/sb700_early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -23,7 +23,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define SMBUS_IO_BASE 0x6000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */
diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index d74a9bbc9f..d74a9bbc9f 100644
--- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
diff --git a/src/southbridge/amd/sb700/sb700_hda.c b/src/southbridge/amd/sb700/hda.c
index 417d513e90..417d513e90 100644
--- a/src/southbridge/amd/sb700/sb700_hda.c
+++ b/src/southbridge/amd/sb700/hda.c
diff --git a/src/southbridge/amd/sb700/sb700_ide.c b/src/southbridge/amd/sb700/ide.c
index 4652ca2539..4652ca2539 100644
--- a/src/southbridge/amd/sb700/sb700_ide.c
+++ b/src/southbridge/amd/sb700/ide.c
diff --git a/src/southbridge/amd/sb700/sb700_lpc.c b/src/southbridge/amd/sb700/lpc.c
index a3a50c6c9b..a3a50c6c9b 100644
--- a/src/southbridge/amd/sb700/sb700_lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
diff --git a/src/southbridge/amd/sb700/sb700_pci.c b/src/southbridge/amd/sb700/pci.c
index d1e9851b9d..d1e9851b9d 100644
--- a/src/southbridge/amd/sb700/sb700_pci.c
+++ b/src/southbridge/amd/sb700/pci.c
diff --git a/src/southbridge/amd/sb700/sb700_reset.c b/src/southbridge/amd/sb700/reset.c
index 32ee66b4b5..32ee66b4b5 100644
--- a/src/southbridge/amd/sb700/sb700_reset.c
+++ b/src/southbridge/amd/sb700/reset.c
diff --git a/src/southbridge/amd/sb700/sb700_sata.c b/src/southbridge/amd/sb700/sata.c
index 08b9aa8ad9..08b9aa8ad9 100644
--- a/src/southbridge/amd/sb700/sb700_sata.c
+++ b/src/southbridge/amd/sb700/sata.c
diff --git a/src/southbridge/amd/sb700/sb700_sm.c b/src/southbridge/amd/sb700/sm.c
index e700c0b5f3..69df215f52 100644
--- a/src/southbridge/amd/sb700/sb700_sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -30,7 +30,7 @@
 #include <arch/ioapic.h>
 #include <stdlib.h>
 #include "sb700.h"
-#include "sb700_smbus.c"
+#include "smbus.c"
 
 #define NMI_OFF 0
 
diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/smbus.c
index ee1653df3e..e47bceed47 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.c
+++ b/src/southbridge/amd/sb700/smbus.c
@@ -20,7 +20,7 @@
 #ifndef _SB700_SMBUS_C_
 #define _SB700_SMBUS_C_
 
-#include "sb700_smbus.h"
+#include "smbus.h"
 
 static inline void smbus_delay(void)
 {
diff --git a/src/southbridge/amd/sb700/sb700_smbus.h b/src/southbridge/amd/sb700/smbus.h
index c21a1dc0a2..c21a1dc0a2 100644
--- a/src/southbridge/amd/sb700/sb700_smbus.h
+++ b/src/southbridge/amd/sb700/smbus.h
diff --git a/src/southbridge/amd/sb700/sb700_usb.c b/src/southbridge/amd/sb700/usb.c
index 3b3ad584a7..3b3ad584a7 100644
--- a/src/southbridge/amd/sb700/sb700_usb.c
+++ b/src/southbridge/amd/sb700/usb.c
diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc
index 246be282e2..8e5ba7411b 100644
--- a/src/southbridge/broadcom/bcm21000/Makefile.inc
+++ b/src/southbridge/broadcom/bcm21000/Makefile.inc
@@ -1 +1 @@
-driver-y += bcm21000_pcie.c
+driver-y += pcie.c
diff --git a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c
index 72ee95b8cf..72ee95b8cf 100644
--- a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c
+++ b/src/southbridge/broadcom/bcm21000/pcie.c
diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc
index 55c6e11ec1..b8a1b96c27 100644
--- a/src/southbridge/broadcom/bcm5780/Makefile.inc
+++ b/src/southbridge/broadcom/bcm5780/Makefile.inc
@@ -1,3 +1,3 @@
-driver-y += bcm5780_nic.c
-driver-y += bcm5780_pcix.c
-driver-y += bcm5780_pcie.c
+driver-y += nic.c
+driver-y += pcix.c
+driver-y += pcie.c
diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index 387c402215..387c402215 100644
--- a/src/southbridge/broadcom/bcm5780/bcm5780_nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c
index 786ad4f431..786ad4f431 100644
--- a/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c
+++ b/src/southbridge/broadcom/bcm5780/pcie.c
diff --git a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index e500542c33..e500542c33 100644
--- a/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc
index e80ed35a34..9ad67ccf1f 100644
--- a/src/southbridge/broadcom/bcm5785/Makefile.inc
+++ b/src/southbridge/broadcom/bcm5785/Makefile.inc
@@ -1,7 +1,7 @@
 driver-y += bcm5785.c
-driver-y += bcm5785_usb.c
-driver-y += bcm5785_lpc.c
-driver-y += bcm5785_sb_pci_main.c
-driver-y += bcm5785_ide.c
-driver-y += bcm5785_sata.c
-ramstage-y += bcm5785_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += sb_pci_main.c
+driver-y += ide.c
+driver-y += sata.c
+ramstage-y += reset.c
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 40201c6072..f51fcd0ff9 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_enable_rom.c"
+#include "enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index e3edfd8635..e3edfd8635 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 3cc1292574..f235e58888 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x1000
 
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c b/src/southbridge/broadcom/bcm5785/enable_rom.c
index 1cd28498b9..1cd28498b9 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c
+++ b/src/southbridge/broadcom/bcm5785/enable_rom.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c b/src/southbridge/broadcom/bcm5785/ide.c
index a40094afde..a40094afde 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_ide.c
+++ b/src/southbridge/broadcom/bcm5785/ide.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index adf546245f..adf546245f 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index a59b23992e..a59b23992e 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 573e8475ce..573e8475ce 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 6c65fad4cf..fe809c4974 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -30,7 +30,7 @@
 #include <arch/io.h>
 #include <device/smbus.h>
 #include "bcm5785.h"
-#include "bcm5785_smbus.h"
+#include "smbus.h"
 
 #define NMI_OFF 0
 
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index f6dfffa878..f6dfffa878 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c b/src/southbridge/broadcom/bcm5785/usb.c
index a16d6fe11b..a16d6fe11b 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_usb.c
+++ b/src/southbridge/broadcom/bcm5785/usb.c
diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc
index 53cdb7e804..004ff13a55 100644
--- a/src/southbridge/intel/esb6300/Makefile.inc
+++ b/src/southbridge/intel/esb6300/Makefile.inc
@@ -1,12 +1,12 @@
 driver-y += esb6300.c
-driver-y += esb6300_reset.c
-driver-y += esb6300_uhci.c
-driver-y += esb6300_lpc.c
-driver-y += esb6300_ide.c
-driver-y += esb6300_sata.c
-driver-y += esb6300_ehci.c
-driver-y += esb6300_smbus.c
-driver-y += esb6300_pci.c
-driver-y += esb6300_pic.c
-driver-y += esb6300_bridge1c.c
-driver-y += esb6300_ac97.c
+driver-y += reset.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+driver-y += pic.c
+driver-y += bridge1c.c
+driver-y += ac97.c
diff --git a/src/southbridge/intel/esb6300/esb6300_ac97.c b/src/southbridge/intel/esb6300/ac97.c
index 7b7795f5df..7b7795f5df 100644
--- a/src/southbridge/intel/esb6300/esb6300_ac97.c
+++ b/src/southbridge/intel/esb6300/ac97.c
diff --git a/src/southbridge/intel/esb6300/esb6300_bridge1c.c b/src/southbridge/intel/esb6300/bridge1c.c
index 54c2717d89..54c2717d89 100644
--- a/src/southbridge/intel/esb6300/esb6300_bridge1c.c
+++ b/src/southbridge/intel/esb6300/bridge1c.c
diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/early_smbus.c
index f8587856e8..d0b9632f83 100644
--- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c
+++ b/src/southbridge/intel/esb6300/early_smbus.c
@@ -1,4 +1,4 @@
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/ehci.c
index c103c4bd2f..c103c4bd2f 100644
--- a/src/southbridge/intel/esb6300/esb6300_ehci.c
+++ b/src/southbridge/intel/esb6300/ehci.c
diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/ide.c
index abe86a811d..abe86a811d 100644
--- a/src/southbridge/intel/esb6300/esb6300_ide.c
+++ b/src/southbridge/intel/esb6300/ide.c
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc961..67bcadc961 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
diff --git a/src/southbridge/intel/esb6300/esb6300_pci.c b/src/southbridge/intel/esb6300/pci.c
index 64aeb0db46..64aeb0db46 100644
--- a/src/southbridge/intel/esb6300/esb6300_pci.c
+++ b/src/southbridge/intel/esb6300/pci.c
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/pic.c
index b9bfdf1fe3..b9bfdf1fe3 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/pic.c
diff --git a/src/southbridge/intel/esb6300/esb6300_reset.c b/src/southbridge/intel/esb6300/reset.c
index 8dbe6cb1d7..8dbe6cb1d7 100644
--- a/src/southbridge/intel/esb6300/esb6300_reset.c
+++ b/src/southbridge/intel/esb6300/reset.c
diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/sata.c
index 6dce2d2f3a..6dce2d2f3a 100644
--- a/src/southbridge/intel/esb6300/esb6300_sata.c
+++ b/src/southbridge/intel/esb6300/sata.c
diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.c b/src/southbridge/intel/esb6300/smbus.c
index 5b1940f93e..c7ed04f136 100644
--- a/src/southbridge/intel/esb6300/esb6300_smbus.c
+++ b/src/southbridge/intel/esb6300/smbus.c
@@ -6,7 +6,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "esb6300.h"
-#include "esb6300_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.h b/src/southbridge/intel/esb6300/smbus.h
index 4f4ec5c999..4f4ec5c999 100644
--- a/src/southbridge/intel/esb6300/esb6300_smbus.h
+++ b/src/southbridge/intel/esb6300/smbus.h
diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/uhci.c
index a8bcd888f1..a8bcd888f1 100644
--- a/src/southbridge/intel/esb6300/esb6300_uhci.c
+++ b/src/southbridge/intel/esb6300/uhci.c
diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc
index dcc1fb7357..fa6caf1b52 100644
--- a/src/southbridge/intel/i3100/Makefile.inc
+++ b/src/southbridge/intel/i3100/Makefile.inc
@@ -1,9 +1,9 @@
 driver-y += i3100.c
-driver-y += i3100_uhci.c
-driver-y += i3100_lpc.c
-driver-y += i3100_sata.c
-driver-y += i3100_ehci.c
-driver-y += i3100_smbus.c
-driver-y += i3100_pci.c
-ramstage-y += i3100_reset.c
-ramstage-y += i3100_pciexp_portb.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+ramstage-y += reset.c
+ramstage-y += pciexp_portb.c
diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c
index 3397aff1f8..3397aff1f8 100644
--- a/src/southbridge/intel/i3100/i3100_early_lpc.c
+++ b/src/southbridge/intel/i3100/early_lpc.c
diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index 79825d153a..f3d4450c5e 100644
--- a/src/southbridge/intel/i3100/i3100_early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -18,7 +18,7 @@
  *
  */
 
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
diff --git a/src/southbridge/intel/i3100/i3100_ehci.c b/src/southbridge/intel/i3100/ehci.c
index 195ea99cd1..195ea99cd1 100644
--- a/src/southbridge/intel/i3100/i3100_ehci.c
+++ b/src/southbridge/intel/i3100/ehci.c
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/lpc.c
index 1544ecd44f..1544ecd44f 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
diff --git a/src/southbridge/intel/i3100/i3100_pci.c b/src/southbridge/intel/i3100/pci.c
index 99fc95d0f6..99fc95d0f6 100644
--- a/src/southbridge/intel/i3100/i3100_pci.c
+++ b/src/southbridge/intel/i3100/pci.c
diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c
index 31502a46de..31502a46de 100644
--- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c
+++ b/src/southbridge/intel/i3100/pciexp_portb.c
diff --git a/src/southbridge/intel/i3100/i3100_reset.c b/src/southbridge/intel/i3100/reset.c
index 3f35f5fb83..3f35f5fb83 100644
--- a/src/southbridge/intel/i3100/i3100_reset.c
+++ b/src/southbridge/intel/i3100/reset.c
diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/sata.c
index af22600f90..af22600f90 100644
--- a/src/southbridge/intel/i3100/i3100_sata.c
+++ b/src/southbridge/intel/i3100/sata.c
diff --git a/src/southbridge/intel/i3100/i3100_smbus.c b/src/southbridge/intel/i3100/smbus.c
index f51363d92a..23602acb21 100644
--- a/src/southbridge/intel/i3100/i3100_smbus.c
+++ b/src/southbridge/intel/i3100/smbus.c
@@ -26,7 +26,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "i3100.h"
-#include "i3100_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
diff --git a/src/southbridge/intel/i3100/i3100_smbus.h b/src/southbridge/intel/i3100/smbus.h
index 7023a5b751..7023a5b751 100644
--- a/src/southbridge/intel/i3100/i3100_smbus.h
+++ b/src/southbridge/intel/i3100/smbus.h
diff --git a/src/southbridge/intel/i3100/i3100_uhci.c b/src/southbridge/intel/i3100/uhci.c
index 5453509769..5453509769 100644
--- a/src/southbridge/intel/i3100/i3100_uhci.c
+++ b/src/southbridge/intel/i3100/uhci.c
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index b5ac581ff1..6b27af3c4a 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -19,13 +19,13 @@
 ##
 
 driver-y +=  i82371eb.c
-driver-y +=  i82371eb_isa.c
-driver-y +=  i82371eb_ide.c
-driver-y +=  i82371eb_usb.c
-driver-y +=  i82371eb_smbus.c
-driver-y +=  i82371eb_reset.c
-driver-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
+driver-y +=  isa.c
+driver-y +=  ide.c
+driver-y +=  usb.c
+driver-y +=  smbus.c
+driver-y +=  reset.c
+driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
 
-romstage-y += i82371eb_early_pm.c
-romstage-y += i82371eb_early_smbus.c
+romstage-y += early_pm.c
+romstage-y += early_smbus.c
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index c818691639..f83b4073c1 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c
index 5e52985428..5e52985428 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
+++ b/src/southbridge/intel/i82371eb/early_pm.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index 8505762933..d11b06c4f1 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -25,7 +25,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/enable_rom.c
index 46b0144f28..46b0144f28 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
+++ b/src/southbridge/intel/i82371eb/enable_rom.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 5891440d2e..5891440d2e 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/ide.c
index f72bcb63c6..f72bcb63c6 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_ide.c
+++ b/src/southbridge/intel/i82371eb/ide.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/isa.c
index d025bf2393..d025bf2393 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_reset.c b/src/southbridge/intel/i82371eb/reset.c
index baff05b143..baff05b143 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_reset.c
+++ b/src/southbridge/intel/i82371eb/reset.c
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 4dfd2f4caf..b1a51c6a8a 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -29,7 +29,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
-#include "i82371eb_smbus.h"
+#include "smbus.h"
 
 static void pwrmgt_enable(struct device *dev)
 {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/smbus.h
index f82f2edc73..f82f2edc73 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h
+++ b/src/southbridge/intel/i82371eb/smbus.h
diff --git a/src/southbridge/intel/i82371eb/i82371eb_usb.c b/src/southbridge/intel/i82371eb/usb.c
index 1a903a95b0..1a903a95b0 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_usb.c
+++ b/src/southbridge/intel/i82371eb/usb.c
diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc
index a282dd1e36..de0c7228ed 100644
--- a/src/southbridge/intel/i82801ax/Makefile.inc
+++ b/src/southbridge/intel/i82801ax/Makefile.inc
@@ -19,15 +19,15 @@
 ##
 
 driver-y += i82801ax.c
-driver-y += i82801ax_ac97.c
-driver-y += i82801ax_ide.c
-driver-y += i82801ax_lpc.c
-driver-y += i82801ax_pci.c
-driver-y += i82801ax_smbus.c
-driver-y += i82801ax_usb.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += pci.c
+driver-y += smbus.c
+driver-y += usb.c
 
-ramstage-y += i82801ax_reset.c
-ramstage-y += i82801ax_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-romstage-y += i82801ax_early_smbus.c
+romstage-y += early_smbus.c
 
diff --git a/src/southbridge/intel/i82801ax/i82801ax_ac97.c b/src/southbridge/intel/i82801ax/ac97.c
index 826264bbfe..826264bbfe 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_ac97.c
+++ b/src/southbridge/intel/i82801ax/ac97.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c
index dca3a28eec..e894c37095 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
+++ b/src/southbridge/intel/i82801ax/early_smbus.c
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/ide.c
index c5bd2882b4..c5bd2882b4 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_ide.c
+++ b/src/southbridge/intel/i82801ax/ide.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index c9404ed3c0..c9404ed3c0 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_pci.c b/src/southbridge/intel/i82801ax/pci.c
index 293ce582c2..293ce582c2 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_pci.c
+++ b/src/southbridge/intel/i82801ax/pci.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_reset.c b/src/southbridge/intel/i82801ax/reset.c
index b30db9d9c0..b30db9d9c0 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_reset.c
+++ b/src/southbridge/intel/i82801ax/reset.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.c b/src/southbridge/intel/i82801ax/smbus.c
index 8a3155f540..d9fa970dfa 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_smbus.c
+++ b/src/southbridge/intel/i82801ax/smbus.c
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801ax.h"
-#include "i82801ax_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
diff --git a/src/southbridge/intel/i82801ax/i82801ax_smbus.h b/src/southbridge/intel/i82801ax/smbus.h
index 26893a76d9..26893a76d9 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_smbus.h
+++ b/src/southbridge/intel/i82801ax/smbus.h
diff --git a/src/southbridge/intel/i82801ax/i82801ax_usb.c b/src/southbridge/intel/i82801ax/usb.c
index 78aadb0a3e..78aadb0a3e 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_usb.c
+++ b/src/southbridge/intel/i82801ax/usb.c
diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/watchdog.c
index cd0c20d98e..cd0c20d98e 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
+++ b/src/southbridge/intel/i82801ax/watchdog.c
diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc
index 313a0896df..b3587f2228 100644
--- a/src/southbridge/intel/i82801bx/Makefile.inc
+++ b/src/southbridge/intel/i82801bx/Makefile.inc
@@ -19,16 +19,16 @@
 ##
 
 driver-y += i82801bx.c
-driver-y += i82801bx_ac97.c
-driver-y += i82801bx_ide.c
-driver-y += i82801bx_lpc.c
-driver-y += i82801bx_nic.c
-driver-y += i82801bx_pci.c
-driver-y += i82801bx_smbus.c
-driver-y += i82801bx_usb.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += smbus.c
+driver-y += usb.c
 
-ramstage-y += i82801bx_reset.c
-ramstage-y += i82801bx_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-romstage-y += i82801bx_early_smbus.c
+romstage-y += early_smbus.c
 
diff --git a/src/southbridge/intel/i82801bx/i82801bx_ac97.c b/src/southbridge/intel/i82801bx/ac97.c
index 5e2acd3310..5e2acd3310 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_ac97.c
+++ b/src/southbridge/intel/i82801bx/ac97.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c
index 6a2097ea14..4ff8d61cda 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
+++ b/src/southbridge/intel/i82801bx/early_smbus.c
@@ -26,7 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801bx.h"
-#include "i82801bx_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/ide.c
index 413984b5f4..413984b5f4 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_ide.c
+++ b/src/southbridge/intel/i82801bx/ide.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 0ff44e6054..0ff44e6054 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_nic.c b/src/southbridge/intel/i82801bx/nic.c
index b843aca328..b843aca328 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_nic.c
+++ b/src/southbridge/intel/i82801bx/nic.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_pci.c b/src/southbridge/intel/i82801bx/pci.c
index 828a668197..828a668197 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_pci.c
+++ b/src/southbridge/intel/i82801bx/pci.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_reset.c b/src/southbridge/intel/i82801bx/reset.c
index 8d85cdca75..8d85cdca75 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_reset.c
+++ b/src/southbridge/intel/i82801bx/reset.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.c b/src/southbridge/intel/i82801bx/smbus.c
index db27b094c3..d4a609ae3f 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_smbus.c
+++ b/src/southbridge/intel/i82801bx/smbus.c
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include "i82801bx.h"
-#include "i82801bx_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/smbus.h
index c04e9dc8d3..c04e9dc8d3 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h
+++ b/src/southbridge/intel/i82801bx/smbus.h
diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb.c b/src/southbridge/intel/i82801bx/usb.c
index f90f6a6906..f90f6a6906 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_usb.c
+++ b/src/southbridge/intel/i82801bx/usb.c
diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/watchdog.c
index cd0c20d98e..cd0c20d98e 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
+++ b/src/southbridge/intel/i82801bx/watchdog.c
diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc
index 1e30c681a0..9c5c7fbc45 100644
--- a/src/southbridge/intel/i82801cx/Makefile.inc
+++ b/src/southbridge/intel/i82801cx/Makefile.inc
@@ -1,8 +1,8 @@
 driver-y += i82801cx.c
-driver-y += i82801cx_usb.c
-driver-y += i82801cx_lpc.c
-driver-y += i82801cx_ide.c
-driver-y += i82801cx_ac97.c
-#driver-y += i82801cx_nic.c
-driver-y += i82801cx_pci.c
-ramstage-y += i82801cx_reset.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += ac97.c
+#driver-y += nic.c
+driver-y += pci.c
+ramstage-y += reset.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_ac97.c b/src/southbridge/intel/i82801cx/ac97.c
index 5de44fc382..5de44fc382 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_ac97.c
+++ b/src/southbridge/intel/i82801cx/ac97.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c
index b62db80f9c..b62db80f9c 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
+++ b/src/southbridge/intel/i82801cx/early_smbus.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_ide.c b/src/southbridge/intel/i82801cx/ide.c
index 74c442c52c..74c442c52c 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_ide.c
+++ b/src/southbridge/intel/i82801cx/ide.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index a1ffb8f540..a1ffb8f540 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_nic.c b/src/southbridge/intel/i82801cx/nic.c
index 00ce038143..00ce038143 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_nic.c
+++ b/src/southbridge/intel/i82801cx/nic.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_pci.c b/src/southbridge/intel/i82801cx/pci.c
index 842b214fc8..842b214fc8 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_pci.c
+++ b/src/southbridge/intel/i82801cx/pci.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_reset.c b/src/southbridge/intel/i82801cx/reset.c
index bd479de758..bd479de758 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_reset.c
+++ b/src/southbridge/intel/i82801cx/reset.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/smbus.c
index 324f82f286..324f82f286 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c
+++ b/src/southbridge/intel/i82801cx/smbus.c
diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/usb.c
index 28cb3572e5..28cb3572e5 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_usb.c
+++ b/src/southbridge/intel/i82801cx/usb.c
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index 7952b3b25c..9070158d0d 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -20,14 +20,14 @@
 ##
 
 driver-y += i82801dx.c
-driver-y += i82801dx_ac97.c
-driver-y += i82801dx_ide.c
-driver-y += i82801dx_lpc.c
-#driver-y += i82801dx_pci.c
-driver-y += i82801dx_usb.c
-driver-y += i82801dx_usb2.c
+driver-y += ac97.c
+driver-y += ide.c
+driver-y += lpc.c
+#driver-y += pci.c
+driver-y += usb.c
+driver-y += usb2.c
 
-ramstage-y += i82801dx_reset.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.c
+ramstage-y += reset.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_ac97.c b/src/southbridge/intel/i82801dx/ac97.c
index ccfccd3421..ccfccd3421 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_ac97.c
+++ b/src/southbridge/intel/i82801dx/ac97.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index f58cd86342..f58cd86342 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_ide.c b/src/southbridge/intel/i82801dx/ide.c
index 75350da058..75350da058 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_ide.c
+++ b/src/southbridge/intel/i82801dx/ide.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 768e70096b..768e70096b 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_nvs.h b/src/southbridge/intel/i82801dx/nvs.h
index 03f8de74ea..03f8de74ea 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_nvs.h
+++ b/src/southbridge/intel/i82801dx/nvs.h
diff --git a/src/southbridge/intel/i82801dx/i82801dx_pci.c b/src/southbridge/intel/i82801dx/pci.c
index 610ec1e5df..610ec1e5df 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_pci.c
+++ b/src/southbridge/intel/i82801dx/pci.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_reset.c b/src/southbridge/intel/i82801dx/reset.c
index 8dbe6cb1d7..8dbe6cb1d7 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_reset.c
+++ b/src/southbridge/intel/i82801dx/reset.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_smbus.c b/src/southbridge/intel/i82801dx/smbus.c
index 1f7e47be95..1f7e47be95 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_smbus.c
+++ b/src/southbridge/intel/i82801dx/smbus.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_smi.c b/src/southbridge/intel/i82801dx/smi.c
index 55d8a70965..55d8a70965 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5b7520f553..4875ba7480 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -47,7 +47,7 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "i82801dx_nvs.h"
+#include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c
index a778d0851d..a778d0851d 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
+++ b/src/southbridge/intel/i82801dx/tco_timer.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb.c b/src/southbridge/intel/i82801dx/usb.c
index be44a293dc..be44a293dc 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_usb.c
+++ b/src/southbridge/intel/i82801dx/usb.c
diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb2.c b/src/southbridge/intel/i82801dx/usb2.c
index a0ea5f64e1..a0ea5f64e1 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_usb2.c
+++ b/src/southbridge/intel/i82801dx/usb2.c
diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc
index ddddae37b6..e0d3148755 100644
--- a/src/southbridge/intel/i82801ex/Makefile.inc
+++ b/src/southbridge/intel/i82801ex/Makefile.inc
@@ -1,11 +1,11 @@
 driver-y += i82801ex.c
-driver-y += i82801ex_uhci.c
-driver-y += i82801ex_lpc.c
-driver-y += i82801ex_ide.c
-driver-y += i82801ex_sata.c
-driver-y += i82801ex_ehci.c
-driver-y += i82801ex_smbus.c
-driver-y += i82801ex_pci.c
-driver-y += i82801ex_ac97.c
-ramstage-y += i82801ex_watchdog.c
-ramstage-y += i82801ex_reset.c
+driver-y += uhci.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += ehci.c
+driver-y += smbus.c
+driver-y += pci.c
+driver-y += ac97.c
+ramstage-y += watchdog.c
+ramstage-y += reset.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ac97.c b/src/southbridge/intel/i82801ex/ac97.c
index 08efe1534d..08efe1534d 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ac97.c
+++ b/src/southbridge/intel/i82801ex/ac97.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index b07c77a94f..cdf1f62c57 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -1,4 +1,4 @@
-#include "i82801ex_smbus.h"
+#include "smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/ehci.c
index 8ae921d194..8ae921d194 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c
+++ b/src/southbridge/intel/i82801ex/ehci.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/ide.c
index bbab6f1cc0..bbab6f1cc0 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_ide.c
+++ b/src/southbridge/intel/i82801ex/ide.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 998360ce07..998360ce07 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_pci.c b/src/southbridge/intel/i82801ex/pci.c
index 80c6e49bc0..80c6e49bc0 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_pci.c
+++ b/src/southbridge/intel/i82801ex/pci.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892efe..9936892efe 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/sata.c
index 9b340e9afd..9b340e9afd 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_sata.c
+++ b/src/southbridge/intel/i82801ex/sata.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.c b/src/southbridge/intel/i82801ex/smbus.c
index 377df11cd0..6bb48993b6 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_smbus.c
+++ b/src/southbridge/intel/i82801ex/smbus.c
@@ -6,7 +6,7 @@
 #include <device/smbus.h>
 #include <arch/io.h>
 #include "i82801ex.h"
-#include "i82801ex_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_read_byte(device_t dev, u8 address)
 {
diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.h b/src/southbridge/intel/i82801ex/smbus.h
index f330c0a5de..f330c0a5de 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_smbus.h
+++ b/src/southbridge/intel/i82801ex/smbus.h
diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/uhci.c
index 56536b7273..56536b7273 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c
+++ b/src/southbridge/intel/i82801ex/uhci.c
diff --git a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 26f6644763..26f6644763 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index dfc9c4d3b6..d3a731b2ac 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -18,24 +18,24 @@
 ##
 
 driver-y += i82801gx.c
-driver-y += i82801gx_ac97.c
-driver-y += i82801gx_azalia.c
-driver-y += i82801gx_ide.c
-driver-y += i82801gx_lpc.c
-driver-y += i82801gx_nic.c
-driver-y += i82801gx_pci.c
-driver-y += i82801gx_pcie.c
-driver-y += i82801gx_sata.c
-driver-y += i82801gx_smbus.c
-driver-y += i82801gx_usb.c
-driver-y += i82801gx_usb_ehci.c
+driver-y += ac97.c
+driver-y += azalia.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += pcie.c
+driver-y += sata.c
+driver-y += smbus.c
+driver-y += usb.c
+driver-y += usb_ehci.c
 
-ramstage-y += i82801gx_reset.c
-ramstage-y += i82801gx_watchdog.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
 
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
-romstage-y += i82801gx_early_smbus.c
-romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c
+romstage-y += early_smbus.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
 
diff --git a/src/southbridge/intel/i82801gx/i82801gx_ac97.c b/src/southbridge/intel/i82801gx/ac97.c
index 602014bb2e..602014bb2e 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ac97.c
+++ b/src/southbridge/intel/i82801gx/ac97.c
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl b/src/southbridge/intel/i82801gx/acpi/ac97.asl
index 8a8cf82217..8a8cf82217 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ac97.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl b/src/southbridge/intel/i82801gx/acpi/audio.asl
index d03be4fdd3..d03be4fdd3 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
+++ b/src/southbridge/intel/i82801gx/acpi/audio.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index a37208c021..8387b20037 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -159,30 +159,30 @@ Scope(\)
 }
 
 // 0:1b.0 High Definition Audio (Azalia)
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/audio.asl"
 
 // PCI Express Ports
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pcie.asl"
 
 // USB
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/usb.asl"
 
 // PCI Bridge
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pci.asl"
 
 // AC97 Audio and Modem
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/ac97.asl"
 
 // LPC Bridge
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/lpc.asl"
 
 // PATA
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/pata.asl"
 
 // SATA
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/sata.asl"
 
 // SMBus
-#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl"
+#include "../../../southbridge/intel/i82801gx/acpi/smbus.asl"
 
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl
index 5fcee45f29..5fcee45f29 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
+++ b/src/southbridge/intel/i82801gx/acpi/irqlinks.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl
index a18673c679..3166a89baf 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl
@@ -51,7 +51,7 @@ Device (LPCB)
 		RCBA,	18,
 	}
 
-	#include "../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl"
+	#include "../../../southbridge/intel/i82801gx/acpi/irqlinks.asl"
 
 	#include "acpi/ec.asl"
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl b/src/southbridge/intel/i82801gx/acpi/pata.asl
index 1905ed26d2..1905ed26d2 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
+++ b/src/southbridge/intel/i82801gx/acpi/pata.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/pci.asl
index d253d51a78..d253d51a78 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
+++ b/src/southbridge/intel/i82801gx/acpi/pci.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl b/src/southbridge/intel/i82801gx/acpi/pcie.asl
index a76c7fbe4d..a76c7fbe4d 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
+++ b/src/southbridge/intel/i82801gx/acpi/pcie.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl b/src/southbridge/intel/i82801gx/acpi/sata.asl
index e0c336ac5d..e0c336ac5d 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
+++ b/src/southbridge/intel/i82801gx/acpi/sata.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl b/src/southbridge/intel/i82801gx/acpi/smbus.asl
index b6d2d6a2ab..b6d2d6a2ab 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
+++ b/src/southbridge/intel/i82801gx/acpi/smbus.asl
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl
index 9ae9909a9e..9ae9909a9e 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
+++ b/src/southbridge/intel/i82801gx/acpi/usb.asl
diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 362ffa3aa8..362ffa3aa8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 0298cc94cd..1fa88730bc 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include "i82801gx.h"
-#include "i82801gx_smbus.h"
+#include "smbus.h"
 
 void enable_smbus(void)
 {
diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/ide.c
index 6e05e0d9b5..6e05e0d9b5 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index f486c1ebf8..f486c1ebf8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_nic.c b/src/southbridge/intel/i82801gx/nic.c
index 0405294cb7..0405294cb7 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_nic.c
+++ b/src/southbridge/intel/i82801gx/nic.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index 03f8de74ea..03f8de74ea 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/pci.c
index 4c44e1e153..4c44e1e153 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index d69bc6d07d..d69bc6d07d 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_reset.c b/src/southbridge/intel/i82801gx/reset.c
index 29b69ff43a..29b69ff43a 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/sata.c
index c3908489eb..c3908489eb 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 50c6d0f342..834f310c6c 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -27,7 +27,7 @@
 #include <device/pci_ops.h>
 #include <arch/io.h>
 #include "i82801gx.h"
-#include "i82801gx_smbus.h"
+#include "smbus.h"
 
 #define SMB_BASE 0x20
 static void smbus_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smbus.h b/src/southbridge/intel/i82801gx/smbus.h
index a03e4cd957..a03e4cd957 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smbus.h
+++ b/src/southbridge/intel/i82801gx/smbus.h
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/smi.c
index 39d5c4dca2..39d5c4dca2 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smi.c
+++ b/src/southbridge/intel/i82801gx/smi.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 997ec0fd5c..aefa283571 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -44,7 +44,7 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "i82801gx_nvs.h"
+#include "nvs.h"
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb.c b/src/southbridge/intel/i82801gx/usb.c
index 00fddf7c65..00fddf7c65 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index 991aa5adaa..991aa5adaa 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index cd74e2b8f6..cd74e2b8f6 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c
index a26786d7d0..a26786d7d0 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c
+++ b/src/southbridge/intel/i82801gx/watchdog.c
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
index 8f4964573e..7ca6fb5b07 100644
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ b/src/southbridge/intel/i82870/Makefile.inc
@@ -1,3 +1,3 @@
-driver-y += p64h2_ioapic.c
-driver-y += p64h2_pcibridge.c
-#driver-y += p64h2_pci_parity.c
+driver-y += ioapic.c
+driver-y += pcibridge.c
+#driver-y += pci_parity.c
diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 6a0f0d222f..6a0f0d222f 100644
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
diff --git a/src/southbridge/intel/i82870/p64h2_pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index fe27abf280..fe27abf280 100644
--- a/src/southbridge/intel/i82870/p64h2_pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index 89b86f5966..89b86f5966 100644
--- a/src/southbridge/intel/i82870/p64h2_pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
diff --git a/src/southbridge/intel/pxhd/Makefile.inc b/src/southbridge/intel/pxhd/Makefile.inc
index 30f1f69a63..d5b3a5f88e 100644
--- a/src/southbridge/intel/pxhd/Makefile.inc
+++ b/src/southbridge/intel/pxhd/Makefile.inc
@@ -1 +1 @@
-driver-y += pxhd_bridge.c
+driver-y += bridge.c
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/bridge.c
index 1134f8f2f8..1134f8f2f8 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/bridge.c
diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index 09b20708af..b1577f553a 100644
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -1,22 +1,22 @@
 driver-y += ck804.c
-driver-y += ck804_usb.c
-driver-y += ck804_lpc.c
-driver-y += ck804_smbus.c
-driver-y += ck804_ide.c
-driver-y += ck804_sata.c
-driver-y += ck804_usb2.c
-driver-y += ck804_ac97.c
-driver-y += ck804_nic.c
-driver-y += ck804_pci.c
-driver-y += ck804_pcie.c
-driver-y += ck804_ht.c
+driver-y += usb.c
+driver-y += lpc.c
+driver-y += smbus.c
+driver-y += ide.c
+driver-y += sata.c
+driver-y += usb2.c
+driver-y += ac97.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += pcie.c
+driver-y += ht.c
 
-ramstage-y += ck804_reset.c
+ramstage-y += reset.c
 
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 
-romstage-y += ck804_enable_usbdebug.c
-romstage-y += ck804_early_smbus.c
+romstage-y += enable_usbdebug.c
+romstage-y += early_smbus.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds
diff --git a/src/southbridge/nvidia/ck804/ck804_ac97.c b/src/southbridge/nvidia/ck804/ac97.c
index 20b3cfb4b2..20b3cfb4b2 100644
--- a/src/southbridge/nvidia/ck804/ck804_ac97.c
+++ b/src/southbridge/nvidia/ck804/ac97.c
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 5c829e121d..6d4b6a4777 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -20,7 +20,7 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
+#include "southbridge/nvidia/ck804/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index 53d35feecc..53d35feecc 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 23a83ff400..23a83ff400 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h b/src/southbridge/nvidia/ck804/early_setup_ss.h
index 39ae8c1a17..39ae8c1a17 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h
+++ b/src/southbridge/nvidia/ck804/early_setup_ss.h
diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c
index 05dcd98014..70f8744c25 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c
+++ b/src/southbridge/nvidia/ck804/early_smbus.c
@@ -25,8 +25,8 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 
-#include "ck804_smbus.h"
-#include "ck804_early_smbus.h"
+#include "smbus.h"
+#include "early_smbus.h"
 
 #define SMBUS_BAR_BASE 0x20
 #define SMBUS_IO_BASE 0x1000
diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.h b/src/southbridge/nvidia/ck804/early_smbus.h
index cf25403fdd..cf25403fdd 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_smbus.h
+++ b/src/southbridge/nvidia/ck804/early_smbus.h
diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/enable_rom.c
index facf7959eb..facf7959eb 100644
--- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c
+++ b/src/southbridge/nvidia/ck804/enable_rom.c
diff --git a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 3cccded343..3cccded343 100644
--- a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
diff --git a/src/southbridge/nvidia/ck804/ck804_fadt.c b/src/southbridge/nvidia/ck804/fadt.c
index a315a32b96..a315a32b96 100644
--- a/src/southbridge/nvidia/ck804/ck804_fadt.c
+++ b/src/southbridge/nvidia/ck804/fadt.c
diff --git a/src/southbridge/nvidia/ck804/ck804_ht.c b/src/southbridge/nvidia/ck804/ht.c
index 7a63d97b56..7a63d97b56 100644
--- a/src/southbridge/nvidia/ck804/ck804_ht.c
+++ b/src/southbridge/nvidia/ck804/ht.c
diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ide.c
index 47f451e6eb..47f451e6eb 100644
--- a/src/southbridge/nvidia/ck804/ck804_ide.c
+++ b/src/southbridge/nvidia/ck804/ide.c
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index b3f14bfe18..b3f14bfe18 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/nic.c
index 8e1bddf9e2..8e1bddf9e2 100644
--- a/src/southbridge/nvidia/ck804/ck804_nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/pci.c
index 044c7100d4..044c7100d4 100644
--- a/src/southbridge/nvidia/ck804/ck804_pci.c
+++ b/src/southbridge/nvidia/ck804/pci.c
diff --git a/src/southbridge/nvidia/ck804/ck804_pcie.c b/src/southbridge/nvidia/ck804/pcie.c
index cbde9cf57c..cbde9cf57c 100644
--- a/src/southbridge/nvidia/ck804/ck804_pcie.c
+++ b/src/southbridge/nvidia/ck804/pcie.c
diff --git a/src/southbridge/nvidia/ck804/ck804_reset.c b/src/southbridge/nvidia/ck804/reset.c
index 7f73e68d35..7f73e68d35 100644
--- a/src/southbridge/nvidia/ck804/ck804_reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/sata.c
index b3ec80422d..b3ec80422d 100644
--- a/src/southbridge/nvidia/ck804/ck804_sata.c
+++ b/src/southbridge/nvidia/ck804/sata.c
diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.c b/src/southbridge/nvidia/ck804/smbus.c
index ca5305065f..b1c6e28530 100644
--- a/src/southbridge/nvidia/ck804/ck804_smbus.c
+++ b/src/southbridge/nvidia/ck804/smbus.c
@@ -27,7 +27,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include "ck804.h"
-#include "ck804_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_recv_byte(device_t dev)
 {
diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index 2cdcadce80..2cdcadce80 100644
--- a/src/southbridge/nvidia/ck804/ck804_smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
diff --git a/src/southbridge/nvidia/ck804/ck804_usb.c b/src/southbridge/nvidia/ck804/usb.c
index 45ee734eb1..45ee734eb1 100644
--- a/src/southbridge/nvidia/ck804/ck804_usb.c
+++ b/src/southbridge/nvidia/ck804/usb.c
diff --git a/src/southbridge/nvidia/ck804/ck804_usb2.c b/src/southbridge/nvidia/ck804/usb2.c
index e53f38f019..e53f38f019 100644
--- a/src/southbridge/nvidia/ck804/ck804_usb2.c
+++ b/src/southbridge/nvidia/ck804/usb2.c
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index a9dcf7f40f..a59e1486fa 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -1,21 +1,21 @@
 driver-y += mcp55.c
-driver-y += mcp55_azalia.c
-driver-y += mcp55_ht.c
-driver-y += mcp55_ide.c
-driver-y += mcp55_lpc.c
-driver-y += mcp55_nic.c
-driver-y += mcp55_pci.c
-driver-y += mcp55_pcie.c
-driver-y += mcp55_sata.c
-driver-y += mcp55_smbus.c
-driver-y += mcp55_usb2.c
-driver-y += mcp55_usb.c
+driver-y += azalia.c
+driver-y += ht.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += pci.c
+driver-y += pcie.c
+driver-y += sata.c
+driver-y += smbus.c
+driver-y += usb2.c
+driver-y += usb.c
 
-driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.c
+driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 
-ramstage-y += mcp55_reset.c
+ramstage-y += reset.c
 
-romstage-y += mcp55_enable_usbdebug.c
+romstage-y += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
diff --git a/src/southbridge/nvidia/mcp55/mcp55_azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 493c98f7b2..493c98f7b2 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index e735b4702c..139f93c99d 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "southbridge/nvidia/mcp55/enable_rom.c"
 
 static void bootblock_southbridge_init(void)
 {
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 5c5f07c81a..5c5f07c81a 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index bf778a93fa..bf778a93fa 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h b/src/southbridge/nvidia/mcp55/early_setup_ss.h
index c68e198639..c68e198639 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_ss.h
+++ b/src/southbridge/nvidia/mcp55/early_setup_ss.h
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c
index 469aa7e964..b351b58022 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/early_smbus.c
@@ -21,7 +21,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "mcp55_smbus.h"
+#include "smbus.h"
 
 #define SMBUS0_IO_BASE	0x1000
 #define SMBUS1_IO_BASE	(0x1000+(1<<8))
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/enable_rom.c
index d08b1d486b..d08b1d486b 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
+++ b/src/southbridge/nvidia/mcp55/enable_rom.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 2e78fa1ff6..2e78fa1ff6 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/fadt.c
index 753a663239..753a663239 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c
+++ b/src/southbridge/nvidia/mcp55/fadt.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_ht.c b/src/southbridge/nvidia/mcp55/ht.c
index 8b0248f8a6..8b0248f8a6 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_ht.c
+++ b/src/southbridge/nvidia/mcp55/ht.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_ide.c b/src/southbridge/nvidia/mcp55/ide.c
index 90dd2bf48d..90dd2bf48d 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_ide.c
+++ b/src/southbridge/nvidia/mcp55/ide.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 3132eedbd2..3132eedbd2 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 3533e4e25a..3533e4e25a 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_pci.c b/src/southbridge/nvidia/mcp55/pci.c
index 510d21d10b..510d21d10b 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_pci.c
+++ b/src/southbridge/nvidia/mcp55/pci.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_pcie.c b/src/southbridge/nvidia/mcp55/pcie.c
index cb60f3143a..cb60f3143a 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_pcie.c
+++ b/src/southbridge/nvidia/mcp55/pcie.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_reset.c b/src/southbridge/nvidia/mcp55/reset.c
index afc592c26b..afc592c26b 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_sata.c b/src/southbridge/nvidia/mcp55/sata.c
index eebc61e26f..eebc61e26f 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_sata.c
+++ b/src/southbridge/nvidia/mcp55/sata.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 47c422f08a..ceb5f16df9 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -30,7 +30,7 @@
 #include <bitops.h>
 #include <arch/io.h>
 #include "mcp55.h"
-#include "mcp55_smbus.h"
+#include "smbus.h"
 
 static int lsmbus_recv_byte(device_t dev)
 {
diff --git a/src/southbridge/nvidia/mcp55/mcp55_smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index d1dade9c45..d1dade9c45 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
diff --git a/src/southbridge/nvidia/mcp55/mcp55_usb.c b/src/southbridge/nvidia/mcp55/usb.c
index c005c91743..c005c91743 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_usb.c
+++ b/src/southbridge/nvidia/mcp55/usb.c
diff --git a/src/southbridge/nvidia/mcp55/mcp55_usb2.c b/src/southbridge/nvidia/mcp55/usb2.c
index cd4fe25f17..cd4fe25f17 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_usb2.c
+++ b/src/southbridge/nvidia/mcp55/usb2.c
diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc
index e51c81fa83..f796047a6f 100644
--- a/src/southbridge/sis/sis966/Makefile.inc
+++ b/src/southbridge/sis/sis966/Makefile.inc
@@ -1,15 +1,15 @@
 driver-y += sis761.c
 driver-y += sis966.c
-driver-y += sis966_lpc.c
-driver-y += sis966_ide.c
-driver-y += sis966_usb.c
-driver-y += sis966_usb2.c
-driver-y += sis966_nic.c
-driver-y += sis966_sata.c
-driver-y += sis966_pcie.c
-driver-y += sis966_aza.c
-ramstage-y += sis966_reset.c
-romstage-y += sis966_enable_usbdebug.c
+driver-y += lpc.c
+driver-y += ide.c
+driver-y += usb.c
+driver-y += usb2.c
+driver-y += nic.c
+driver-y += sata.c
+driver-y += pcie.c
+driver-y += aza.c
+ramstage-y += reset.c
+romstage-y += enable_usbdebug.c
 
 chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds
diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/aza.c
index c7573a3f7a..c7573a3f7a 100644
--- a/src/southbridge/sis/sis966/sis966_aza.c
+++ b/src/southbridge/sis/sis966/aza.c
diff --git a/src/southbridge/sis/sis966/sis966_early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index 05b53365de..05b53365de 100644
--- a/src/southbridge/sis/sis966/sis966_early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
diff --git a/src/southbridge/sis/sis966/sis966_early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c
index 9de33137a7..9de33137a7 100644
--- a/src/southbridge/sis/sis966/sis966_early_setup_car.c
+++ b/src/southbridge/sis/sis966/early_setup_car.c
diff --git a/src/southbridge/sis/sis966/sis966_early_setup_ss.h b/src/southbridge/sis/sis966/early_setup_ss.h
index c68e198639..c68e198639 100644
--- a/src/southbridge/sis/sis966/sis966_early_setup_ss.h
+++ b/src/southbridge/sis/sis966/early_setup_ss.h
diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 1c81bf16fd..8ab65483f6 100644
--- a/src/southbridge/sis/sis966/sis966_early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include "sis966_smbus.h"
+#include "smbus.h"
 
 #define SMBUS0_IO_BASE	0x8D0
 
diff --git a/src/southbridge/sis/sis966/sis966_enable_rom.c b/src/southbridge/sis/sis966/enable_rom.c
index 63ef616563..63ef616563 100644
--- a/src/southbridge/sis/sis966/sis966_enable_rom.c
+++ b/src/southbridge/sis/sis966/enable_rom.c
diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index a82e941b3a..a82e941b3a 100644
--- a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
diff --git a/src/southbridge/sis/sis966/sis966_ide.c b/src/southbridge/sis/sis966/ide.c
index c57be5ade7..c57be5ade7 100644
--- a/src/southbridge/sis/sis966/sis966_ide.c
+++ b/src/southbridge/sis/sis966/ide.c
diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/lpc.c
index 26f60dd3af..26f60dd3af 100644
--- a/src/southbridge/sis/sis966/sis966_lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/nic.c
index a7aeec37ed..a7aeec37ed 100644
--- a/src/southbridge/sis/sis966/sis966_nic.c
+++ b/src/southbridge/sis/sis966/nic.c
diff --git a/src/southbridge/sis/sis966/sis966_pcie.c b/src/southbridge/sis/sis966/pcie.c
index dedbefdbf4..dedbefdbf4 100644
--- a/src/southbridge/sis/sis966/sis966_pcie.c
+++ b/src/southbridge/sis/sis966/pcie.c
diff --git a/src/southbridge/sis/sis966/sis966_reset.c b/src/southbridge/sis/sis966/reset.c
index afc592c26b..afc592c26b 100644
--- a/src/southbridge/sis/sis966/sis966_reset.c
+++ b/src/southbridge/sis/sis966/reset.c
diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sata.c
index 57a2d8870f..57a2d8870f 100644
--- a/src/southbridge/sis/sis966/sis966_sata.c
+++ b/src/southbridge/sis/sis966/sata.c
diff --git a/src/southbridge/sis/sis966/sis966_smbus.h b/src/southbridge/sis/sis966/smbus.h
index 087ea47f23..087ea47f23 100644
--- a/src/southbridge/sis/sis966/sis966_smbus.h
+++ b/src/southbridge/sis/sis966/smbus.h
diff --git a/src/southbridge/sis/sis966/sis966_usb.c b/src/southbridge/sis/sis966/usb.c
index d49f2aabb4..d49f2aabb4 100644
--- a/src/southbridge/sis/sis966/sis966_usb.c
+++ b/src/southbridge/sis/sis966/usb.c
diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/usb2.c
index 6ede023837..6ede023837 100644
--- a/src/southbridge/sis/sis966/sis966_usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc
index 2a208f7c89..5081694808 100644
--- a/src/southbridge/ti/pci7420/Makefile.inc
+++ b/src/southbridge/ti/pci7420/Makefile.inc
@@ -17,6 +17,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-driver-y += pci7420_cardbus.c
-driver-y += pci7420_firewire.c
+driver-y += cardbus.c
+driver-y += firewire.c
 
diff --git a/src/southbridge/ti/pci7420/pci7420_cardbus.c b/src/southbridge/ti/pci7420/cardbus.c
index 2ab383b511..2ab383b511 100644
--- a/src/southbridge/ti/pci7420/pci7420_cardbus.c
+++ b/src/southbridge/ti/pci7420/cardbus.c
diff --git a/src/southbridge/ti/pci7420/pci7420_firewire.c b/src/southbridge/ti/pci7420/firewire.c
index bd09c2fde7..bd09c2fde7 100644
--- a/src/southbridge/ti/pci7420/pci7420_firewire.c
+++ b/src/southbridge/ti/pci7420/firewire.c
diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc
index b549d4af33..972ff70074 100644
--- a/src/southbridge/via/k8t890/Makefile.inc
+++ b/src/southbridge/via/k8t890/Makefile.inc
@@ -1,12 +1,12 @@
-driver-y += k8t890_ctrl.c
-driver-y += k8t890_dram.c
-driver-y += k8t890_bridge.c
-driver-y += k8t890_host.c
-driver-y += k8t890_host_ctrl.c
-driver-y += k8t890_pcie.c
-driver-y += k8t890_traf_ctrl.c
-driver-y += k8t890_error.c
-driver-y += k8m890_chrome.c
+driver-y += ctrl.c
+driver-y += dram.c
+driver-y += bridge.c
+driver-y += host.c
+driver-y += host_ctrl.c
+driver-y += pcie.c
+driver-y += traf_ctrl.c
+driver-y += error.c
+driver-y += chrome.c
 
 chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/bridge.c
index 3e1e81730d..3e1e81730d 100644
--- a/src/southbridge/via/k8t890/k8t890_bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
diff --git a/src/southbridge/via/k8t890/k8m890_chrome.c b/src/southbridge/via/k8t890/chrome.c
index 5880026552..5880026552 100644
--- a/src/southbridge/via/k8t890/k8m890_chrome.c
+++ b/src/southbridge/via/k8t890/chrome.c
diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index bb3cc02217..bb3cc02217 100644
--- a/src/southbridge/via/k8t890/k8t890_ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/dram.c
index 6c52fb1d02..6c52fb1d02 100644
--- a/src/southbridge/via/k8t890/k8t890_dram.c
+++ b/src/southbridge/via/k8t890/dram.c
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/early_car.c
index 94162cb90c..94162cb90c 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
diff --git a/src/southbridge/via/k8t890/k8t890_error.c b/src/southbridge/via/k8t890/error.c
index a9b10d56bc..a9b10d56bc 100644
--- a/src/southbridge/via/k8t890/k8t890_error.c
+++ b/src/southbridge/via/k8t890/error.c
diff --git a/src/southbridge/via/k8t890/k8t890_host.c b/src/southbridge/via/k8t890/host.c
index 9a0118c778..9a0118c778 100644
--- a/src/southbridge/via/k8t890/k8t890_host.c
+++ b/src/southbridge/via/k8t890/host.c
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 43d01ee369..43d01ee369 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/pcie.c
index 2840bf3b2d..2840bf3b2d 100644
--- a/src/southbridge/via/k8t890/k8t890_pcie.c
+++ b/src/southbridge/via/k8t890/pcie.c
diff --git a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index 55b3a13ac7..55b3a13ac7 100644
--- a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
diff --git a/src/southbridge/via/vt8231/Makefile.inc b/src/southbridge/via/vt8231/Makefile.inc
index 938d3cebe3..b9e7ef6f1d 100644
--- a/src/southbridge/via/vt8231/Makefile.inc
+++ b/src/southbridge/via/vt8231/Makefile.inc
@@ -18,8 +18,8 @@
 ##
 
 driver-y += vt8231.c
-driver-y += vt8231_lpc.c
-driver-y += vt8231_acpi.c
-driver-y += vt8231_ide.c
-driver-y += vt8231_nic.c
-#driver-y += vt8231_usb.c
+driver-y += lpc.c
+driver-y += acpi.c
+driver-y += ide.c
+driver-y += nic.c
+#driver-y += usb.c
diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/acpi.c
index 647910aef6..647910aef6 100644
--- a/src/southbridge/via/vt8231/vt8231_acpi.c
+++ b/src/southbridge/via/vt8231/acpi.c
diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/early_serial.c
index af5a7729ee..af5a7729ee 100644
--- a/src/southbridge/via/vt8231/vt8231_early_serial.c
+++ b/src/southbridge/via/vt8231/early_serial.c
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/early_smbus.c
index 7bf1267b75..7bf1267b75 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/early_smbus.c
diff --git a/src/southbridge/via/vt8231/vt8231_enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c
index bb43420610..bb43420610 100644
--- a/src/southbridge/via/vt8231/vt8231_enable_rom.c
+++ b/src/southbridge/via/vt8231/enable_rom.c
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/ide.c
index 46479c4af3..46479c4af3 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/ide.c
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/lpc.c
index 40854dbcf7..40854dbcf7 100644
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/nic.c
index 5cd6cd8ca1..5cd6cd8ca1 100644
--- a/src/southbridge/via/vt8231/vt8231_nic.c
+++ b/src/southbridge/via/vt8231/nic.c
diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/usb.c
index e12a8db85a..e12a8db85a 100644
--- a/src/southbridge/via/vt8231/vt8231_usb.c
+++ b/src/southbridge/via/vt8231/usb.c
diff --git a/src/southbridge/via/vt8235/Makefile.inc b/src/southbridge/via/vt8235/Makefile.inc
index 06d533560b..02e22640bf 100644
--- a/src/southbridge/via/vt8235/Makefile.inc
+++ b/src/southbridge/via/vt8235/Makefile.inc
@@ -18,7 +18,7 @@
 ##
 
 driver-y += vt8235.c
-driver-y += vt8235_ide.c
-driver-y += vt8235_lpc.c
-driver-y += vt8235_nic.c
-driver-y += vt8235_usb.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += nic.c
+driver-y += usb.c
diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/early_serial.c
index 11f98fae39..11f98fae39 100644
--- a/src/southbridge/via/vt8235/vt8235_early_serial.c
+++ b/src/southbridge/via/vt8235/early_serial.c
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c
index d091099fdb..d091099fdb 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/early_smbus.c
diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/ide.c
index 961f860fed..961f860fed 100644
--- a/src/southbridge/via/vt8235/vt8235_ide.c
+++ b/src/southbridge/via/vt8235/ide.c
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/lpc.c
index b355ad0d88..b355ad0d88 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/nic.c
index 71f169c055..71f169c055 100644
--- a/src/southbridge/via/vt8235/vt8235_nic.c
+++ b/src/southbridge/via/vt8235/nic.c
diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/usb.c
index c712136c72..c712136c72 100644
--- a/src/southbridge/via/vt8235/vt8235_usb.c
+++ b/src/southbridge/via/vt8235/usb.c
diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc
index 04adb4b6d9..dd14a00fdc 100644
--- a/src/southbridge/via/vt8237r/Makefile.inc
+++ b/src/southbridge/via/vt8237r/Makefile.inc
@@ -18,10 +18,10 @@
 ##
 
 driver-y += vt8237r.c
-driver-y += vt8237_ctrl.c
-driver-y += vt8237r_ide.c
-driver-y += vt8237r_lpc.c
-driver-y += vt8237r_sata.c
-driver-y += vt8237r_usb.c
-driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c
+driver-y += ctrl.c
+driver-y += ide.c
+driver-y += lpc.c
+driver-y += sata.c
+driver-y += usb.c
+driver-$(CONFIG_PIRQ_ROUTE) += pirq.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
diff --git a/src/southbridge/via/vt8237r/vt8237_ctrl.c b/src/southbridge/via/vt8237r/ctrl.c
index f3cc30ed88..f3cc30ed88 100644
--- a/src/southbridge/via/vt8237r/vt8237_ctrl.c
+++ b/src/southbridge/via/vt8237r/ctrl.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index a298e84676..a298e84676 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
diff --git a/src/southbridge/via/vt8237r/vt8237_fadt.c b/src/southbridge/via/vt8237r/fadt.c
index 6976f4d447..6976f4d447 100644
--- a/src/southbridge/via/vt8237r/vt8237_fadt.c
+++ b/src/southbridge/via/vt8237r/fadt.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/ide.c
index 209437b729..209437b729 100644
--- a/src/southbridge/via/vt8237r/vt8237r_ide.c
+++ b/src/southbridge/via/vt8237r/ide.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 72b85b37d5..72b85b37d5 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_nic.c b/src/southbridge/via/vt8237r/nic.c
index 6771895916..6771895916 100644
--- a/src/southbridge/via/vt8237r/vt8237r_nic.c
+++ b/src/southbridge/via/vt8237r/nic.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_pirq.c b/src/southbridge/via/vt8237r/pirq.c
index 9915da4835..9915da4835 100644
--- a/src/southbridge/via/vt8237r/vt8237r_pirq.c
+++ b/src/southbridge/via/vt8237r/pirq.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_sata.c b/src/southbridge/via/vt8237r/sata.c
index 777d605a6b..777d605a6b 100644
--- a/src/southbridge/via/vt8237r/vt8237r_sata.c
+++ b/src/southbridge/via/vt8237r/sata.c
diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/usb.c
index 6e8d9e5dd0..6e8d9e5dd0 100644
--- a/src/southbridge/via/vt8237r/vt8237r_usb.c
+++ b/src/southbridge/via/vt8237r/usb.c
diff --git a/src/southbridge/via/vt82c686/vt82c686_early_serial.c b/src/southbridge/via/vt82c686/early_serial.c
index 70c68aaaf5..70c68aaaf5 100644
--- a/src/southbridge/via/vt82c686/vt82c686_early_serial.c
+++ b/src/southbridge/via/vt82c686/early_serial.c