diff options
| -rw-r--r-- | src/southbridge/amd/cs5530/cs5530.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ax/i82801ax.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801bx/i82801bx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 5 |
7 files changed, 7 insertions, 10 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530.h b/src/southbridge/amd/cs5530/cs5530.h index 283b64de33..e95d88e15b 100644 --- a/src/southbridge/amd/cs5530/cs5530.h +++ b/src/southbridge/amd/cs5530/cs5530.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H #define SOUTHBRIDGE_AMD_CS5530_CS5530_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" void cs5530_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index f105571380..cb4356ef8a 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h index 7df86d2f23..2ead33f02a 100644 --- a/src/southbridge/intel/i82801ax/i82801ax.h +++ b/src/southbridge/intel/i82801ax/i82801ax.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H #define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801ax_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h index 6d77f81985..8c2c30794c 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.h +++ b/src/southbridge/intel/i82801bx/i82801bx.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H #define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801bx_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index b9b3511a4a..4cb215efbb 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -1,7 +1,7 @@ #ifndef I82801CX_H #define I82801CX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801cx_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a1c30c290e..885f9de0f1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,7 +31,7 @@ #ifndef I82801DX_H #define I82801DX_H -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); #endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3ae440d568..b5a2054526 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,10 +39,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -/* __ROMCC__ is set by romstage.c to make sure - * none of the stage2 data structures are included. - */ -#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif |