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-rw-r--r--src/arch/riscv/Makefile.inc3
-rw-r--r--src/arch/riscv/bootblock.S143
-rw-r--r--src/arch/riscv/id.S33
3 files changed, 55 insertions, 124 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index c1c62efb7c..718aad9582 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -28,6 +28,9 @@ endif
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
+bootblock-y += id.S
+$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
+
bootblock-y = bootblock.S stages.c
bootblock-y += trap_util.S
bootblock-y += trap_handler.c
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 5092ec0405..514511ed0d 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -1,7 +1,8 @@
/*
- * Early initialization code for aarch64 (a.k.a. armv8)
+ * Early initialization code for RISC-V
*
* Copyright 2013 Google Inc.
+ * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -13,7 +14,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
-// See LICENSE for license details. relating to the _start code in this file.
+
#include <arch/encoding.h>
.section ".text._start", "ax", %progbits
@@ -24,130 +25,24 @@ _start:
#define STACK_START 0x80800000 /* 2GiB + 8MiB */
#define STACK_SIZE 0x0000fff0
- // pending figuring out this f-ing toolchain. Hardcode what we know works.
- li sp, STACK_START + STACK_SIZE
-
- # make room for HLS and initialize it
- addi sp, sp, -64 // MENTRY_FRAME_SIZE
- csrr a0, mhartid
- call hls_init
-
- //poison the stack
- li t1, STACK_START
- li t0, 0xdeadbeef
- sd t0, 0(t1)
-
- la t0, exception_handler
- csrw mtvec, t0
-
- # clear any pending interrupts
- csrwi mip, 0
-
- # set up the mstatus register for VM
- call mstatus_init
- call main
-.=0x2000
- .space 0x800
-# sbi interface lives here
-
-# hart_id
-.align 5
-li a7, 0
-ecall
-ret
-
-# num_harts
-.align 4
-li a0, 1
-ret
-
-# query_memory
-.align 4
-li a7, 8
-ecall
-ret
-
-# console_putchar
-.align 4
-li a7, 1
-ecall
-ret
-
-# send_device_request
-.align 4
-li a7, 2
-ecall
-ret
-
-# receive_device_response
-.align 4
-li a7, 3
-ecall
-ret
-
-# send ipi
-.align 4
-li a7, 4
-ecall
-ret
-
-# clear ipi
-.align 4
-li a7, 5
-ecall
-ret
-
-# timebase
-.align 4
-li a0, 10000000 # temporary, we should provide the correct answer
-ret
-
-# shutdown
-.align 4
-li a7, 6
-ecall
-
-# set_timer
-.align 4
-li a7, 7
-ecall
-ret
+ li sp, STACK_START + STACK_SIZE
-# end of SBI trampolines
-.=0x4000
-.stack:
-.align 8
- .space 0xf00
-.stacktop:
- .quad 0
-.align 3
-.stack_size:
- .quad 0xf00
-.globl test_trap
-exception_handler:
- call trap_handler
-reset:
-init_stack_loop:
+ # make room for HLS and initialize it
+ addi sp, sp, -64 // MENTRY_FRAME_SIZE
+ csrr a0, mhartid
+ call hls_init
- .word CONFIG_STACK_SIZE
- .section ".id", "a", %progbits
+ # poison the stack
+ li t1, STACK_START
+ li t0, 0xdeadbeef
+ sd t0, 0(t1)
- .section ".id", "a", @progbits
+ la t0, trap_entry
+ csrw mtvec, t0
- .globl __id_start
- // fix this bs later. What's wrong with the riscv gcc?
-__id_start:
-ver:
- .asciz "1" //COREBOOT_VERSION
-vendor:
- .asciz "ucb" //CONFIG_MAINBOARD_VENDOR
-part:
- .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
-.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
-.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
-.long CONFIG_ROM_SIZE /* Size of this romimage */
- .globl __id_end
+ # clear any pending interrupts
+ csrwi mip, 0
-__id_end:
-.previous
+ # set up the mstatus register for VM
+ call mstatus_init
+ tail main
diff --git a/src/arch/riscv/id.S b/src/arch/riscv/id.S
new file mode 100644
index 0000000000..798aa8967c
--- /dev/null
+++ b/src/arch/riscv/id.S
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <build.h>
+
+ .section ".id", "a", %progbits
+
+ .globl __id_start
+__id_start:
+ver:
+ .asciz "1" //COREBOOT_VERSION
+vendor:
+ .asciz "ucb" //CONFIG_MAINBOARD_VENDOR
+part:
+ .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE /* Size of this romimage */
+ .globl __id_end
+
+__id_end:
+.previous