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-rw-r--r--src/southbridge/intel/lynxpoint/pch.h42
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c20
2 files changed, 5 insertions, 57 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 429dcc032b..283335605d 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -215,51 +215,11 @@ void mainboard_config_rcba(void);
/* PCI Configuration Space (D31:F2): SATA */
#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
-#define INTR_LN 0x3c
+
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
#define IDE_DECODE_ENABLE (1 << 15)
-#define IDE_SITRE (1 << 14)
-#define IDE_ISP_5_CLOCKS (0 << 12)
-#define IDE_ISP_4_CLOCKS (1 << 12)
-#define IDE_ISP_3_CLOCKS (2 << 12)
-#define IDE_RCT_4_CLOCKS (0 << 8)
-#define IDE_RCT_3_CLOCKS (1 << 8)
-#define IDE_RCT_2_CLOCKS (2 << 8)
-#define IDE_RCT_1_CLOCKS (3 << 8)
-#define IDE_DTE1 (1 << 7)
-#define IDE_PPE1 (1 << 6)
-#define IDE_IE1 (1 << 5)
-#define IDE_TIME1 (1 << 4)
-#define IDE_DTE0 (1 << 3)
-#define IDE_PPE0 (1 << 2)
-#define IDE_IE0 (1 << 1)
-#define IDE_TIME0 (1 << 0)
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
-#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
-#define IDE_SSDE1 (1 << 3)
-#define IDE_SSDE0 (1 << 2)
-#define IDE_PSDE1 (1 << 1)
-#define IDE_PSDE0 (1 << 0)
-
-#define IDE_SDMA_TIM 0x4a
-
-#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
-#define SIG_MODE_SEC_NORMAL (0 << 18)
-#define SIG_MODE_SEC_TRISTATE (1 << 18)
-#define SIG_MODE_SEC_DRIVELOW (2 << 18)
-#define SIG_MODE_PRI_NORMAL (0 << 16)
-#define SIG_MODE_PRI_TRISTATE (1 << 16)
-#define SIG_MODE_PRI_DRIVELOW (2 << 16)
-#define FAST_SCB1 (1 << 15)
-#define FAST_SCB0 (1 << 14)
-#define FAST_PCB1 (1 << 13)
-#define FAST_PCB0 (1 << 12)
-#define SCB1 (1 << 3)
-#define SCB0 (1 << 2)
-#define PCB1 (1 << 1)
-#define PCB0 (1 << 0)
-
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
#define SATA_SP 0xd0 /* Scratchpad */
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index d8eb2a814b..6899e81351 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -58,22 +58,10 @@ static void sata_init(struct device *dev)
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */
- pci_write_config8(dev, INTR_LN, 0x0a);
-
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
+
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */
pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map);