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-rw-r--r--src/soc/intel/fsp_broadwell_de/acpi.c30
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/irq.h10
2 files changed, 39 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c
index afa4048f09..1e088684c0 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi.c
+++ b/src/soc/intel/fsp_broadwell_de/acpi.c
@@ -78,7 +78,35 @@ static acpi_cstate_t cstate_map[] = {
static int acpi_sci_irq(void)
{
- return 9;
+ uint8_t actl = 0;
+ static uint8_t sci_irq = 0;
+ device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+
+ /* If this function was already called, just return the stored value. */
+ if (sci_irq)
+ return sci_irq;
+ /* Get contents of ACPI control register. */
+ actl = pci_read_config8(dev, ACPI_CNTL_OFFSET) & SCIS_MASK;
+ /* Determine how SCI is routed. */
+ switch (actl) {
+ case SCIS_IRQ9:
+ case SCIS_IRQ10:
+ case SCIS_IRQ11:
+ sci_irq = actl + 9;
+ break;
+ case SCIS_IRQ20:
+ case SCIS_IRQ21:
+ case SCIS_IRQ22:
+ case SCIS_IRQ23:
+ sci_irq = actl - SCIS_IRQ20 + 20;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
+ sci_irq = 9;
+ break;
+ }
+ printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
+ return sci_irq;
}
void acpi_create_intel_hpet(acpi_hpet_t *hpet)
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h
index ea043267e3..1344f3b880 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h
@@ -51,6 +51,16 @@
#define PIRQG 6
#define PIRQH 7
+#define ACPI_CNTL_OFFSET 0x44
+#define SCIS_MASK 0x07
+#define SCIS_IRQ9 0x00
+#define SCIS_IRQ10 0x01
+#define SCIS_IRQ11 0x02
+#define SCIS_IRQ20 0x04
+#define SCIS_IRQ21 0x05
+#define SCIS_IRQ22 0x06
+#define SCIS_IRQ23 0x07
+
/* In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
* consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */